1
2
3
4
8
7
6
5
GND
IN
IN
EN
†
OUT
OUT
OUT
OC
TPS2045A, TPS2055A
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
GND
IN
EN1
†
EN2
†
OC1
OUT1
OUT2
OC2
TPS2046A, TPS2056A
D PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
EN1
†
EN2
†
GNDB
IN2
EN3
†
EN4
†
OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4
TPS2048A, TPS2058A
D PACKAGE
(TOP VIEW)
†
All enable inputs are active high for the TPS205xA series.
NC – No connect
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GNDA
IN1
EN1
†
EN2
†
GNDB
IN2
EN3
†
NC
OC1
OUT1
OUT2
OC2
OC3
OUT3
NC
NC
TPS2047A, TPS2057A
D PACKAGE
(TOP VIEW)
www.ti.com
CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
1
FEATURES
• 80-m Ω High-Side MOSFET Switch
• 250 mA Continuous Current Per Channel
• Independent Thermal and Short-Circuit
Protection With Overcurrent Logic Output
• Operating Range: 2.7-V to 5.5-V
• CMOS- and TTL-Compatible Enable Inputs
• 2.5-ms Typical Rise Time
• Undervoltage Lockout
• 10 µ A Maximum Standby Supply Current
for Single and Dual
(20 µ A for Triple and Quad)
• Bidirectional Switch
• Ambient Temperature Range, 0 ° C to 85 ° C
• ESD Protection
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
DESCRIPTION
The TPS2045A through TPS2048A and TPS2055A
through TPS2058A power-distribution switches are
intended for applications where heavy capacitive
loads and short circuits are likely to be encountered.
These devices incorporate 80-m Ω N-channel MOSFET high-side power switches for power-distribution systems
that require multiple power switches in a single package. Each switch is controlled by an independent logic
enable input. Gate drive is provided by an internal charge pump designed to control the power-switch rise times
and fall times to minimize current surges during switching. The charge pump requires no external components
and allows operation from supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, these devices limit the output
current to a safe level by switching into a constant-current mode, pulling the overcurrent ( OCx) logic output low.
When continuous heavy overloads and short circuits increase the power dissipation in the switch, causing the
junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage. Recovery from a
thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry ensures the switch
remains off until valid input voltage is present. These power-distribution switches are designed to current limit at
0.5 A.
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2000 – 2008, Texas Instruments Incorporated
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
RECOMMENDED PACKAGED DEVICES
T
A
0 ° C to 85 ° C 0.25 0.5
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com .
(2) The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2045ADR)
ENABLE CURRENT LIMIT AT 25 ° C
Active low TPS2045AD
Active high TPS2055AD
Active low TPS2046AD
Active high TPS2056AD
Active low TPS2047AD
Active high TPS2057AD
Active low TPS2048AD
Active high TPS2058AD
MAXIMUM CONTINUOUS NUMBER OF
LOAD CURRENT SWITCHES
(A)
TYPICAL SHORT-CIRCUIT
(1)
(A)
Single
Dual
Triple
Quad
SOIC (D)
(2)
2 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
OUT
OC
IN
EN
‡
GND
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
‡
Active high for TPS205xA series
†
Current sense
Thermal
Sense
Driver
Current
Limit
Charge
Pump
UVLO
CS
†
Driver
Current
Limit
CS
†
Thermal
Sense
Charge
Pump
Power Switch
GND
EN1
‡
IN
EN2
‡
OC1
OUT1
OUT2
OC2
‡
Active high for TPS205xA series
†
Current sense
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
FUNCTIONAL BLOCK DIAGRAMS
TPS2045A
TPS2046A
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Thermal
Sense
Driver
Current
Limit
Charge
Pump
UVLO
CS
†
Driver
Current
Limit
CS
†
Thermal
Sense
Charge
Pump
Power Switch
GNDA
EN1
‡
IN1
EN2
‡
OC1
OUT1
OUT2
OC2
OUT3
OC3
IN2
EN3
‡
GNDB
Current
Limit
Driver
UVLO
Charge
Pump
CS
Thermal
Sense
Power Switch
†
‡
Active high for TPS205xA series
†
Current sense
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TPS2047A
4 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Thermal
Sense
Driver
Current
Limit
Charge
Pump
UVLO
CS
†
Driver
Current
Limit
CS
†
Thermal
Sense
Charge
Pump
Power Switch
GNDA
EN1
‡
IN1
EN2
‡
OC1
OUT
1
OUT
2
OC2
Thermal
Sense
Driver
Current
Limit
Charge
Pump
UVLO
CS
†
Driver
Current
Limit
CS
†
Thermal
Sense
Charge
Pump
Power Switch
GNDB
EN3
‡
IN2
EN4
‡
OC3
OUT3
OUT4
OC4
TPS2048A
‡
Active high for TPS205xA series
†
Current sense
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Terminal Functions
TPS2045A AND TPS2055A
TERMINAL
NAME
EN 4 - I Enable input. Logic low turns on power switch.
EN - 4 I Enable input. Logic high turns on power switch.
GND 1 1 I Ground
IN 2, 3 2, 3 I Input voltage
OC 5 5 O Overcurrent. Open drain output active low
OUT 6, 7, 8 6, 7, 8 O Power-switch output
TPS2046A AND TPS2056A
NAME
EN1 3 - I Enable input. Logic low turns on power switch, IN-OUT1.
EN2 4 - I Enable input. Logic low turns on power switch, IN-OUT2.
EN1 - 3 I Enable input. Logic high turns on power switch, IN-OUT1.
EN2 - 4 I Enable input. Logic high turns on power switch, IN-OUT2.
GND 1 1 I Ground
IN 2 2 I Input voltage
OC1 8 8 O Overcurrent. Open drain output active low, for power switch, IN-OUT1
OC2 5 5 O Overcurrent. Open drain output active low, for power switch, IN-OUT2
OUT1 7 7 O Power-switch output
OUT2 6 6 O Power-switch output
TPS2045A TPS2055A
TERMINAL
TPS2046A TPS2056A
NO. I/O DESCRIPTION
NO. I/O DESCRIPTION
6 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Terminal Functions (continued)
TPS2047A AND TPS2057A
TERMINAL
NAME
EN1 3 - I Enable input, logic low turns on power switch, IN1-OUT1.
EN2 4 - I Enable input, logic low turns on power switch, IN1-OUT2.
EN3 7 - I Enable input, logic low turns on power switch, IN2-OUT3.
EN1 - 3 I Enable input, logic high turns on power switch, IN1-OUT1.
EN2 - 4 I Enable input, logic high turns on power switch, IN1-OUT2.
EN3 - 7 I Enable input, logic high turns on power switch, IN2-OUT3.
GNDA 1 1 Ground for IN1 switch and circuitry.
GNDB 5 5 Ground for IN2 switch and circuitry.
IN1 2 2 I Input voltage
IN2 6 6 I Input voltage
NC 8, 9, 10 8, 9, 10 No connection
OC1 16 16 O Overcurrent, open drain output active low, IN1-OUT1
OC2 13 13 O Overcurrent, open drain output active low, IN1-OUT2
OC3 12 12 O Overcurrent, open drain output active low, IN2-OUT3
OUT1 15 15 O Power-switch output, IN1-OUT1
OUT2 14 14 O Power-switch output, IN1-OUT2
OUT3 11 11 O Power-switch output, IN2-OUT3
TPS2048A AND TPS2058A
NAME
EN1 3 - I Enable input. logic low turns on power switch, IN1-OUT1.
EN2 4 - I Enable input. Logic low turns on power switch, IN1-OUT2.
EN3 7 - I Enable input. Logic low turns on power switch, IN2-OUT3.
EN4 8 - I Enable input. Logic low turns on power switch, IN2-OUT4.
EN1 - 3 I Enable input. Logic high turns on power switch, IN1-OUT1.
EN2 - 4 I Enable input. Logic high turns on power switch, IN1-OUT2.
EN3 - 7 I Enable input. Logic high turns on power switch, IN2-OUT3.
EN4 - 8 I Enable input. Logic high turns on power switch, IN2-OUT4.
GNDA 1 1 Ground for IN1 switch and circuitry.
GNDB 5 5 Ground for IN2 switch and circuitry.
IN1 2 2 I Input voltage
IN2 6 6 I Input voltage
OC1 16 16 O Overcurrent. Open drain output active low, IN1-OUT1
OC2 13 13 O Overcurrent. Open drain output active low, IN1-OUT2
OC3 12 12 O Overcurrent. Open drain output active low, IN2-OUT3
OC4 9 9 O Overcurrent. Open drain output active low, IN2-OUT4
OUT1 15 15 O Power-switch output, IN1-OUT1
OUT2 14 14 O Power-switch output, IN1-OUT2
OUT3 11 11 O Power-switch output, IN2-OUT3
OUT4 10 10 O Power-switch output, IN2-OUT4
TPS2047A TPS2057A
TERMINAL
TPS2048A TPS2058A
NO. I/O DESCRIPTION
NO. I/O DESCRIPTION
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
DETAILED DESCRIPTION
POWER SWITCH
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 m Ω (V
Configured as a high-side switch, the power switch prevents current flow from OUT to IN and IN to OUT when
disabled. The power switch supplies a minimum of 250 mA per switch.
CHARGE PUMP
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
DRIVER
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall
times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
ENABLE ( ENx, ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current. The supply current is reduced to less than 10 µ A on the single and dual devices (20 µ A on
the triple and quad devices) when a logic high is present on ENx (TPS204xA
(TPS205xA
turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
1
). A logic zero input on ENx or a logic high on ENx restores bias to the drive and control circuits and
1
) or a logic low is present on ENx
= 5 V).
I(IN)
OVERCURRENT ( OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or over temperature condition is
encountered. The output will remain asserted until the overcurrent or over temperature condition is removed.
CURRENT SENSE
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its
saturation region, which switches the output into a constant-current mode and holds the current constant while
varying the voltage on the load.
THERMAL SENSE
The TPS204xA and TPS205xA implement a dual-threshold thermal trip to allow fully independent operation of
the power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140 ° C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The ( OCx) open-drain output is asserted (active low) when over temperature or overcurrent occurs.
UNDERVOLTAGE LOCKOUT
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.
8 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
I(IN)
V
O(OUT)
V
or V
I( ENx)
I
O(OUT)
I(ENx)
Input voltage range
Output voltage range
Input voltage range – 0.3 V to 6 V
Continuous output current internally limited
Continuous total power dissipation See Dissipation Rating Table
T
J
T
stg
Operating virtual junction temperature range 0 ° C to 125 ° C
Storage temperature range – 65 ° C to 150 ° C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
ESD Electrostatic discharge protection
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
(2)
(2)
(1)
UNIT
0.3 V to 6 V
– 0.3 V to V
Human body model MIL-STD-883C 2 kV
Machine model 0.2 kV
DISSIPATION RATING TABLE
PACKAGE
D-8 725 mW 5.9 mW/ ° C 464 mW 377 mW
D-16 1123 mW 9 mW/ ° C 719 mW 584 mW
TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C
POWER RATING ABOVE TA= 25 ° C POWER RATING POWER RATING
+ 0.3 V
I(IN)
RECOMMENDED OPERATING CONDITIONS
V
I(IN)
V
or V
I( EN)
I
O(OUT)
T
J
Input voltage 2.7 5.5 V
Input voltage 0 5.5 V
I(EN)
Continuous output current (per switch) 0 250 mA
Operating virtual junction temperature 0 125 ° C
MIN MAX UNIT
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING JUNCTION
TEMPERATURE RANGE
V
= 5.5 V, IO= rated current, V
I(IN)
PARAMETER TEST CONDITIONS
Static drain-source on-state resistance, V
5-V operation IO= 0.25 A
r
DS(on)
Static drain-source on-state resistance, V
3.3-V operation IO= 0.25 A
t
t
Rise time, output ms
r
Fall time, output ms
f
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
I( EN)
= V
(unless otherwise noted)
I(IN)
V
= 5 V, TJ= 25 ° C,
I(IN)
IO= 0.25 A
= 5 V, TJ= 85 ° C,
I(IN)
V
= 5 V, TJ= 125 ° C,
I(IN)
IO= 0.25 A
V
= 3.3 V, TJ= 25 ° C,
I(IN)
IO= 0.25 A
= 3.3 V, TJ= 85 ° C,
I(IN)
V
= 3.3 V, TJ= 125 ° C,
I(IN)
IO= 0.25 A
V
= 5.5 V, TJ= 25 ° C,
I(IN)
CL= 1 µ F, RL= 20 Ω
V
= 2.7 V, TJ= 25 ° C,
I(IN)
CL= 1 µ F, RL= 20 Ω
V
= 5.5 V, TJ= 25 ° C,
I(IN)
CL= 1 µ F, RL= 20 Ω
V
= 2.7 V, TJ= 25 ° ° C,
I(IN)
CL= 1 µ F, RL= 20 Ω
(1)
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
80 100 80 100
90 120 90 120
100 135 100 135
90 125 90 125
110 145 110 145
120 160 120 160
2.5 2.5
3 3
4.4 4.4
2.5 2.5
UNIT
m Ω
ENABLE INPUT ENx OR ENx
PARAMETER TEST CONDITIONS UNIT
V
high-level input voltage 2.7 V ≤ V
IH
V
Low-level input voltage V
IL
I
Input current µ A
I
t
Turnon time CL= 100 µ F, RL= 20 Ω 20 20
on
t
Turnoff time CL= 100 µ F, RL= 20 Ω 40 40
off
TPS204xA V
TPS205xA V
4.5 V ≤ V
2.7 V ≤ V
I( ENx)
I(ENx)
≤ 5.5 V 2 2 V
I(IN)
≤ 5.5 V 0.8 0.8
I(IN)
≤ 4.5 V 0.4 0.4
I(IN)
= 0 V or V
= V
I(IN)
= V
I( ENx)
or V
I(IN)
= 0 V – 0.5 0.5
I(ENx)
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
– 0.5 0.5
CURRENT LIMIT
PARAMETER TEST CONDITIONS
V
= 5 V, OUT connected to GND,
I
Short-circuit output current 0.3 0.5 0.7 0.3 0.5 0.7 A
OS
I(IN)
Device enabled into short circuit
(1)
(1) Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account
separately.
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
ms
UNIT
10 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
SUPPLY CURRENT (TPS2045A, TPS2055A)
PARAMETER TEST CONDITIONS UNIT
V
= V
I( EN)
Supply current, No Load
I(IN)
low-level output on OUT
V
= 0 V
I(EN)
V
= 0 V
Supply current, No Load
I( EN)
high-level output on OUT
V
= V
I(EN)
I(IN)
Leakage current connected µ A
OUT V
to ground
Reverse leakage IN = High
current impedance
= V
I( EN)
I(IN)
V
= 0 V 40 ° C ≤ TJ≤ 125 ° C 100
I(EN)
V
= 0 V 0.3
I( EN)
V
= V
I(EN)
I(IN)
TJ= 25 ° C 0.025 1
40 ° C ≤ TJ≤ 125 ° C 10
TJ= 25 ° C 0.025 1
40 ° C ≤ TJ≤ 125 ° C 10
TJ= 25 ° C 85 110
40 ° C ≤ TJ≤ 125 ° C 100
TJ= 25 ° C 85 110
40 ° C ≤ TJ≤ 125 ° C 100
40 ° C ≤ TJ≤ 125 ° C 100
TJ= 25 ° C µ A
SUPPLY CURRENT (TPS2046A, TPS2056A)
PARAMETER TEST CONDITIONS UNIT
Supply current, No Load
I( ENx)
I(IN)
V
= V
low-level output on OUT
V
= 0 V
I(ENx)
V
= 0 V
Supply current, No Load
I( ENx)
high-level output on OUT
V
= V
I(ENx)
Leakage current connected µ A
OUT V
to ground
Reverse leakage IN = high
current impedance
I( ENx)
V
I(ENx)
V
I( EN)
V
I(EN)
I(IN)
= V
I(IN)
= 0 V 40 ° C ≤ TJ≤ 125 ° C 100
= 0 V 0.3
= V
I(IN)
TJ= 25 ° C 0.025 1
40 ° C ≤ TJ≤ 125 ° C 10
TJ= 25 ° C 0.025 1
40 ° C ≤ TJ≤ 125 ° C 10
TJ= 25 ° C 85 110
40 ° C ≤ TJ≤ 125 ° C 100
TJ= 25 ° C 85 110
40 ° C ≤ TJ≤ 125 ° C 100
40 ° C ≤ TJ≤ 125 ° C 100
TJ= 25 ° C µ A
TPS2045A TPS2055A
MIN TYP MAX MIN TYP MAX
0.3
TPS2046A TPS2056A
MIN TYP MAX MIN TYP MAX
0.3
µ A
µ A
µ A
µ A
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
SUPPLY CURRENT (TPS2047A, TPS2057A)
PARAMETER TEST CONDITIONS UNIT
Supply current, No load on
I( ENx)
I(INx)
V
= V
low-level output OUTx
V
= 0 V
I(ENx)
V
= 0 V
Supply current, No load on
I(E Nx)
high-level output OUTx
V
= V
I(ENx)
Leakage current connected µ A
OUTx V
to ground
Reverse leakage IN = high
current impedance
I( ENx)
V
I(ENx)
V
I( ENx)
V
I(ENx)
I(INx)
= V
I(INx)
= 0 V 40 ° C ≤ TJ≤ 125 ° C 200
= 0 V 0.3
= V
I(IN)
TJ= 25 ° C 0.05 2
40 ° C ≤ TJ≤ 125 ° C 20
TJ= 25 ° C 0.05 2
40 ° C ≤ TJ≤ 125 ° C 20
TJ= 25 ° C 160 200
40 ° C ≤ TJ≤ 125 ° C 200
TJ= 25 ° C 160 200
40 ° C ≤ TJ≤ 125 ° C 200
40 ° C ≤ TJ≤ 125 ° C 200
TJ= 25 ° C µ A
SUPPLY CURRENT (TPS2048A, TPS2058A)
PARAMETER TEST CONDITIONS UNIT
Supply current, No Load on
I( ENx)
I(INx)
V
= V
low-level output OUTx
V
= 0 V
I(ENx)
V
= 0 V
Supply current, No Load on
I( ENx)
high-level output OUTx
V
= V
I(ENx)
Leakage current connected µ A
OUTx V
to ground
Reverse leakage IN = high
current impedance
V
V
V
I( ENx)
I(ENx)
I( EN)
I(EN)
I(INx)
= V
I(INx)
= 0 V 40 ° C ≤ TJ≤ 125 ° C 200
= 0 V 0.3
= V
I(IN)
TJ= 25 ° C 0.05 2
40 ° C ≤ TJ≤ 125 ° C 20
TJ= 25 ° C 0.05 2
40 ° C ≤ TJ≤ 125 ° C 20
TJ= 25 ° C 170 220
40 ° C ≤ TJ≤ 125 ° C 200
TJ= 25 ° C 170 220
40 ° C ≤ TJ≤ 125 ° C 200
40 ° C ≤ TJ≤ 125 ° C 200
TJ= 25 ° C µ A
TPS2047A TPS2057A
MIN TYP MAX MIN TYP MAX
0.3
TPS2048A TPS2058A
MIN TYP MAX MIN TYP MAX
0.3
µ A
µ A
µ A
µ A
UNDERVOLTAGE LOCKOUT
PARAMETER TEST CONDITIONS UNIT
Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ= 25 ° C 100 100 mV
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
OVERCURRENT OC
PARAMETER TEST CONDITIONS UNIT
Sink current
Output low voltage IO= 5 V, V
Off-state current
(1)
(1)
VO= 5 V 10 10 mA
OL( OC)
VO= 5 V, VO= 3.3 V 1 1 µ A
(1) Specified by design, not production tested.
12 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
TPS204xA TPS205xA
MIN TYP MAX MIN TYP MAX
0.5 0.5 V
PARAMETER MEASUREMENT INFORMATION
RL CL
OUT
t
r
t
f
90%
90%
10%
10%
50%
50%
90%
10%
V
O(OUT)
V
I(EN)
V
O(OUT)
VOLTAGE WAVEFORMS
TEST CIRCUIT
t
on
t
off
50%
50%
90%
10%
V
I(EN)
V
O(OUT)
t
on
t
off
0 4 8 12
t − Time − ms
16 20
V
I(IN)
= 5 V
TA = 25°C
CL = 0.1 µF
RL = 20 Ω
V
I(EN)
(5 V/div)
V
O(OUT)
(2 V/div)
2 6 10 14 18
V
O(OUT)
(2 V/div)
0 1 2 3 4 5 6
t − Time − ms
7 8 9 10
V
I(IN)
= 5 V
TA = 25°C
CL = 0.1 µF
RL = 20 Ω
V
I(EN)
(5 V/div)
Figure 1. Test Circuit and Voltage Waveforms
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Rise Time
With 0.1- µ F Load With 0.1- µ F Load
0 2 4 6 8 10 12
t − Time − ms
14 16 18 20
V
I(IN)
= 5 V
TA = 25°C
CL = 1 µF
RL = 20 Ω
V
I(EN)
(5 V/div)
V
O(OUT)
(2 V/div)
0 1 2 3 4 5 6
t − Time − ms
7 8 9 10
V
I(EN)
(5 V/div)
V
O(OUT)
(2 V/div)
V
I(IN)
= 5 V
TA = 25°C
CL = 1 µF
RL = 20 Ω
0 1 2 3 4 5 6
t − Time − ms
7 8 9 10
I
O(OUTx)
(0.2 A/div)
V
I(ENx)
(5 V/div)
V
I(IN)
= 5 V
TA = 25°C
0 10 20 30 40 50 60
t − Time − ms
70 80 90 100
I
O(OUT)
(0.2 A/div)
V
I(IN)
= 5 V
TA = 25°C
RAMP: 1A/10ms
V
O(OUT)
(2 V/div)
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Turnon Delay and Rise Time Figure 5. Turnoff Delay and Fall Time
With 1- µ F Load With 1- µ F Load
Figure 6. TPS2055A, Short-Circuit Current, Figure 7. TPS2055A, Threshold Trip Current
Device Enabled Into Short With Ramped Load on Enabled Device
14 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
V
O(OC)
(5 V/div)
I
O(OUT)
(0.2 A/div)
V
I(IN)
= 5 V
TA = 25°C
RAMP: 1A/100 ms
0 20 40 60 80 100 120
t − Time − ms
140 160 180 200
0 2 4 6 8 10 12
t − Time − ms
14 16 18 20
V
I(EN)
(5 V/div)
I
O(OUT)
(0.2 A/div)
47 µF
220 µF
V
I(IN)
= 5 V
TA = 25°C
RL = 20 Ω
100 µF
I
O(OUT)
(0.5 A/div)
V
I(IN)
= 5 V
TA = 25°C
0 200 400 600 800 1000
V
O(OC)
(5 V/div)
t − Time − µs
I
O(OUT)
(1 A/div)
V
I(IN)
= 5 V
TA = 25°C
0 200 400 600 800 1000
V
O(OC)
(5 V/div)
t − Time − µs
PARAMETER MEASUREMENT INFORMATION (continued)
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 8. OC Response With Ramped Load Figure 9. Inrush Current With 47- µ F, 100- µ F
on Enabled Device and 220- µ F Load Capacitance
Figure 10. 4- Ω Load Connected to Figure 11. 1- Ω Load Connected to
Enabled Device Enabled Device
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
2
4
6
8
10
2.5 3 3.5 4 4.5 5 5.5 6
Turnon Delay Time − ms
VI − Input Voltage − V
CL = 1 µF
RL = 20 Ω
TA = 25°C
3.3
3
2.7
2.4
2.5 3 3.5 4 4.5
Turnon Delay Time − ms
3.6
3.9
5 5.5 6
VI − Input Voltage − V
CL = 1 µF
RL = 20 Ω
TA = 25°C
1.3
1.4
1.5
1.6
1.8
1.9
2.5 3 3.5 4 4.5 5 5.5 6
− Fall Time − ms
f
t
V
I
− Input Voltage − V
1.7
CL = 1 µF
RL = 20 Ω
TA = 25°C
2
2.1
2.3
2.5
2.7
2.5 3 3.5 4 4.5 5 5.5 6
− Rise Time − ms r
t
V
I
− Input Voltage − V
2.2
2.4
2.6
CL = 1 µF
RL = 20 Ω
TA = 25°C
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS
TURNON DELAY TIME TURNOFF DELAY TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
Figure 12. Figure 13.
RISE TIME FALL TIME
vs vs
INPUT VOLTAGE INPUT VOLTAGE
16 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Figure 14. Figure 15.
40
50
60
70
80
90
100
−40 0 25 85 125
V
I(IN)
= 5.5 V
V
I(IN)
= 5 V
V
I(IN)
= 4.5 V
V
I(IN)
= 3.3 V
V
I(IN)
= 2.7 V
− Supply Current, Output Enabled −
I
I(IN)
Aµ
TJ − Junction Temperature − °C
V
I(IN)
= 4.5 V
0
20
40
60
80
100
120
140
160
−40 0 25 85 125
V
I(IN)
= 5.5 V
V
I(IN)
= 5 V
V
I(IN)
= 3.3 V
V
I(IN)
= 2.7 V
− Supply Current, Output Disabled − nA
I
I(IN)
TJ − Junction Temperature − °C
0
20
40
60
80
100
120
140
160
0 25 85 125
V
I(IN)
= 3 V
V
I(IN)
= 4.5 V
V
I(IN)
= 5 V
V
I(IN)
= 2.7 V
V
I(IN)
= 3.3 V
− Static Drain-Source On-State Resistance − m
Ω
r
DS(on)
TJ − Junction Temperature − ° C
0
10
20
30
40
50
60
70
100 200 300 400 500
TA = 25°C
V
I(IN)
= 2.7 V
V
I(IN)
= 3.3 V
V
I(IN)
= 4.5 V
V
I(IN)
= 5 V
− Input-to-Output Voltage − mV V
I(IN)
−
V
O(OUT)
IL − Load Current − A
TYPICAL CHARACTERISTICS (continued)
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLED
vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
Figure 16. Figure 17.
STATIC DRAIN-SOURCE ON-STATE RESISTANCE INPUT-TO-OUTPUT VOLTAGE
vs vs
JUNCTION TEMPERATURE LOAD CURRENT
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Figure 18. Figure 19.
Threshold Trip Current − A
VI − Input Voltage − V
0.57
0.59
0.61
0.63
0.65
0.67
2.5 3 3.5 4 4.5 5 5.5 6
TA = 25°C
Load Ramp = 1 A/10 ms
400
410
420
430
440
450
460
470
480
490
500
−40 0 25 85 125
TJ − Junction Temperature − °C
− Short-Circuit Output Current − mA
I
OS
V
I(IN)
= 3.3 V
V
I(IN)
= 2.7 V
V
I(IN)
= 5 .5V
V
I(IN)
= 4 .5V
V
I(IN)
= 5V
0
50
100
150
200
250
300
0 2 4 6 8 10
Current-Limit Response −
Peak Current − A
sµ
2.16
2.18
2.2
2.22
2.24
2.26
2.28
2.3
2.32
2.34
2.36
−40 0 25 85 125
UVLO − Undervoltage Lockout − V
TJ − Junction Temperature − °C
Start Threshold
Stop Threshold
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
TYPICAL CHARACTERISTICS (continued)
SHORT-CIRCUIT OUTPUT CURRENT THRESHOLD TRIP CURRENT
JUNCTION TEMPERATURE INPUT VOLTAGE
UNDERVOLTAGE LOCKOUT CURRENT-LIMIT RESPONSE
JUNCTION TEMPERATURE PEAK CURRENT
vs vs
Figure 20. Figure 21.
vs vs
18 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Figure 22. Figure 23.
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
IN
OC
EN
GND
0.1 µF
2,3
5
4
6,7,8
0.1 µF 22 µF
Load
1
OUT
TPS2045A
Power Supply
2.7 V to 5.5 V
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
APPLICATION INFORMATION
Figure 24. Typical Application (Example, TPS2045A)
POWER-SUPPLY CONSIDERATIONS
A 0.01- µ F to 0.1- µ F ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing the
output with a 0.01- µ F to 0.1- µ F ceramic capacitor improves the immunity of the device to short-circuit transients.
OVERCURRENT
A sense FET is employed to check for overcurrent conditions. Unlike current-sense resistors, sense FETs do not
increase the series resistance of the current path. When an overcurrent condition is detected, the device
maintains a constant output current and reduces the output voltage accordingly. Complete shutdown occurs only
if the fault is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before V
has been applied (see Figure 6). The TPS204xA and TPS205xA sense the
I(IN)
short and immediately switch into a constant-current output.
In the second condition, a short or an overload occurs while the device is enabled. At the instant the overload
occurs, very high currents may flow for a short time before the current-limit circuit can react. After the
current-limit circuit has tripped (reached the overcurrent trip threshold) the device switches into constant-current
mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS204xA and TPS205xA are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.
OC RESPONSE
The OC open-drain output is asserted (active low) when an overcurrent or over temperature condition is
encountered. The output will remain asserted until the overcurrent or over temperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. The TPS204xA and
TPS205xA family of devices are designed to reduce false overcurrent reporting. An internal overcurrent transient
filter eliminates the need for external components to remove unwanted pulses. Using low-ESR electrolytic
capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing a
low-impedance energy source, also reducing erroneous overcurrent reporting.
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
GND
IN
IN
EN
OUT
OC
OUT
OUT
TPS2045A
R
pullup
V+
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 25. Typical Circuit for OC Pin (Example, TPS2045A)
POWER DISSIPATION AND JUNCTION TEMPERATURE
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistance of these packages is high compared to those of power packages; it is
good design practice to check power dissipation and junction temperature. Begin by determining the r
N-channel MOSFET relative to the input voltage and operating temperature. As an initial estimate, use the
highest operating ambient temperature of interest and read r
from Figure 18. Using this value, the power
DS(on)
dissipation per switch can be calculated by:
of the
DS(on)
Depending on which device is being used, multiply this number by the number of switches being used. This step
will render the total power dissipation from the N-channel MOSFETs.
Finally, calculate the junction temperature:
Where: T
pin) P
= Ambient temperature ° C R
A
= Total power dissipation based on number of switches being used.
D
= Thermal resistance SOIC = 172 ° C/W (for 8 pin), 111 ° C/W (for 16
Θ JA
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.
THERMAL PROTECTION
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS204xA and TPS205xA into constant-current mode, which
causes the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the
switch is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high
levels. The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into
the thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on.
The switch continues to cycle in this manner until the load fault or input power is removed.
The TPS204xA and TPS205xA implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140 ° C, the internal thermal sense circuitry checks which power switch is in an
overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation of the
adjacent power switch. Should the die temperature exceed the first thermal trip point of 140 ° C and reach 160 ° C,
both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or overcurrent
occurs.
UNDERVOLTAGE LOCKOUT (UVLO)
An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input
voltage falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if the
switch is enabled. Upon reinsertion, the power switch will be turned on, with a controlled rise time to reduce EMI
and voltage overshoots.
20 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
IN
OC
EN
GND
0.1 µF
2,3
5
4
6, 7, 8
0.1 µF 10 µF
GND
1
OUT
TPS2045A
Power Supply
D+
D–
V
BUS
USB
Control
3.3 V
10 µF
Internal
Function
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
UNIVERSAL SERIAL BUS (USB) APPLICATIONS
The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
• Hosts/self-powered hubs (SPH)
• Bus-powered hubs (BPH)
• Low-power, bus-powered functions
• High-power, bus-powered functions
• Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS204xA and
TPS205xA can provide power-distribution solutions for many of these classes of devices.
HOST/SELF-POWERED AND BUS-POWERED HUBS
Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports. This power supply must provide from 5.25 V to 4.75 V to the board side of the downstream
connection under full-load and no-load conditions. Hosts and SPHs are required to have current-limit protection
and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs, monitors, printers,
and stand-alone hubs.
Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs are
required to power up with less than one unit load. The BPH usually has one embedded function, and power is
always available to the controller of the hub. If the embedded function and hub require more than 100 mA on
power up, the power to the embedded function may need to be kept off until enumeration is completed. This can
be accomplished by removing power or by shutting off the clock to the embedded function. Power switching the
embedded function is not necessary if the aggregate power draw for the function and controller is less than one
unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.
LOW-POWER BUS-POWERED FUNCTIONS AND HIGH-POWER BUS-POWERED FUNCTIONS
Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA (see Figure 26); high-power functions must draw less than 100 mA at
power up and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel
combination of 44 Ω and 10 µ F at power up, the device must implement inrush current limiting.
Figure 26. Low-Power Bus-Powered Function (Example, TPS2045A)
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
USB POWER-DISTRIBUTION REQUIREMENTS
USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
• Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB V
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µ F)
– Limit inrush currents
– Power up at <100 mA
• Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µ F)
– Limit inrush currents
– Power up at <100 mA
• Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS204xA and TPS205xA allows them to meet each of these requirements. The
integrated current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level
enable and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the
input ports for bus-power functions.
BUS
22 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
†
USB rev 1.1 requires 120 µ F per hub.
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
ABC
D
33 µF
†
SN75240
ABC
D
GND
GND
GND
33 µF
†
33 µF
†
33 µF
†
D +
D −
Upstream
Port
SN75240
A
B
5 V
GND
C
D
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGE
D
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
GND
EN
OC
IN
TPS2045A
OUT
EN
OC
IN
TPS2045A
OUT
EN
OC
IN
TPS2045A
OUT
EN
OC
IN
TPS2045A
OUT
TPS76333
0.1 µF
0.1 µF
0.1 µF
0.1 µF
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Figure 27. Bus-Powered Hub Implementation, TPS2045A
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
SN75240
EN1
IN
OC1
OUT1
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
TPS2046A
Tuning
Circuit
ABC
D
33 µF
†
SN75240
ABC
D
GND
GND
GND
33 µF
†
33 µF
†
33 µF
†
D +
D −
Upstream
Port
SN75240
A
B
5 V
GND
C
D
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGE
D
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN2
OC2
OUT2
EN1
IN
OC1
OUT1
TPS2046A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†
USB rev 1.1 requires 120 µ F per hub.
TPS76333
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
24 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Figure 28. Bus-Powered Hub Implementation, TPS2046A
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
DM4
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
ABC
D
47 µF
†
1/2 SN75240
ABC
D
GND
GND
47 µF
†
47 µF
†
D +
D −
Upstream
Port
1/2 SN75240
A
B
5 V
GND
C
D
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGE
D
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN1
OC1
OUT1
TPS2047A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†
USB rev 1.1 requires 120 µ F per hub.
EN3
OC3
OUT3
IN2
GNDA
GNDB
TPS76333
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 29. Bus-Powered Hub Implementation, TPS2047A
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
DP1
DM1
DP2
DM2
DP3
DM3
DP4
PWRON1
OVRCUR1
PWRON2
OVRCUR2
PWRON3
OVRCUR3
PWRON4
OVRCUR4
DM4
DP0
DM0
V
CC
XTAL1
XTAL2
OCSOFF
SN75240
D +
D −
5 V
GND
D +
D −
5 V
D +
D −
5 V
D +
D −
5 V
48-MHz
Crystal
Downstream
Ports
TUSB2040
Hub Controller
Tuning
Circuit
ABC
D
33 µF
†
SN75240
ABC
D
GND
GND
GND
33 µF
†
33 µF
†
33 µF
†
D +
D −
Upstream
Port
TPS2041A
SN75240
A
B
5 V
GND
C
D
GND
Ferrite Beads
Ferrite Beads
Ferrite Beads
Ferrite Beads
BUSPWR
GANGE
D
IN
GND
3.3 V
4.7 µF
0.1 µF
4.7 µF
EN1
IN1
OC1
OUT1
TPS2048A
EN2
OC2
OUT2
0.1 µF
0.1 µF
GND
†
USB rev 1.1 requires 120 µ F per hub.
EN3
OC3
OUT3
EN4
OC4
OUT4
IN2
GNDA
GNDB
TPS76333
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
Figure 30. Bus-Powered Hub Implementation, TPS2048A
26 Submit Documentation Feedback Copyright © 2000 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
Power
Supply
Block of
Circuitry
TPS2045A
GND
IN
IN
EN
OUT
OUT
OUT
OC
0.1 µF
1000 µF
Optimum
2.7 V to 5.5 V
PC Board
Overcurrent Response
TPS2045A , , TPS2046A
TPS2047A , TPS2048A , TPS2055A
TPS2056A , TPS2057A , TPS2058A
SLVS251C – SEPTEMBER 2000 – REVISED JANUARY 2008
GENERIC HOT-PLUG APPLICATIONS (see Figure 31 )
In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen by
the main power supply and the card being inserted. The most effective way to control these surges is to limit and
slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS204xA and TPS205xA, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS204xA and TPS205xA also ensures the switch will be off after the card has been removed, and the
switch will be off during the next insertion. The UVLO feature insures a soft start with a controlled rise time for
every insertion of the card or module.
Figure 31. Typical Hot-Plug Implementation (Example, TPS2045A)
By placing the TPS204xA and TPS205xA between the V
input and the rest of the circuitry, the input power will
CC
reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing a
slow voltage ramp at the output of the device. This implementation controls system surge currents and provides
a hot-plugging mechanism for any device.
Copyright © 2000 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): TPS2045A TPS2046A TPS2047A TPS2048A TPS2055A TPS2056A TPS2057A TPS2058A
PACKAGE OPTION ADDENDUM
www.ti.com
PACKAGING INFORMATION
Orderable Device Status
TPS2045AD ACTIVE SOIC D 8 75 Green (RoHS &
TPS2045ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
TPS2045ADR ACTIVE SOIC D 8 2500 Green (RoHS &
TPS2045ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
TPS2046AD NRND SOIC D 8 75 Green (RoHS &
TPS2046ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
TPS2046ADR NRND SOIC D 8 2500 Green (RoHS &
TPS2046ADRG4 NRND SOIC D 8 2500 Green (RoHS &
TPS2047AD NRND SOIC D 16 40 Green (RoHS &
TPS2047ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
TPS2047ADR NRND SOIC D 16 2500 Green (RoHS &
TPS2047ADRG4 NRND SOIC D 16 2500 Green (RoHS &
TPS2048AD ACTIVE SOIC D 16 40 Green (RoHS &
TPS2048ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
TPS2048ADR ACTIVE SOIC D 16 2500 Green (RoHS &
TPS2048ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
TPS2055AD ACTIVE SOIC D 8 75 Green (RoHS &
TPS2055ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
TPS2055ADR ACTIVE SOIC D 8 2500 Green (RoHS &
TPS2055ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
TPS2056AD NRND SOIC D 8 75 Green (RoHS &
TPS2056ADG4 ACTIVE SOIC D 8 75 Green (RoHS &
TPS2056ADR ACTIVE SOIC D 8 2500 Green (RoHS &
TPS2056ADRG4 ACTIVE SOIC D 8 2500 Green (RoHS &
TPS2057AD ACTIVE SOIC D 16 40 Green (RoHS &
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
no Sb/Br)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
14-Jan-2008
(3)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TPS2057ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
14-Jan-2008
(3)
no Sb/Br)
TPS2057ADR ACTIVE SOIC D 16 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2057ADRG4 ACTIVE SOIC D 16 2500 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2058AD ACTIVE SOIC D 16 40 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2058ADG4 ACTIVE SOIC D 16 40 Green (RoHS &
CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TPS2058ADRG4 ACTIVE SOIC D 16 TBD Call TI Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
11-Mar-2008
*All dimensions are nominal
Device Package
Type
TPS2045ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2046ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2047ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2048ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2048ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
TPS2055ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2056ADR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TPS2057ADR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2045ADR SOIC D 8 2500 342.9 338.1 20.6
TPS2046ADR SOIC D 8 2500 342.9 338.1 20.6
TPS2047ADR SOIC D 16 2500 342.9 345.9 28.6
TPS2048ADR SOIC D 16 2500 346.0 346.0 33.0
TPS2048ADR SOIC D 16 2500 342.9 345.9 28.6
TPS2055ADR SOIC D 8 2500 342.9 338.1 20.6
TPS2056ADR SOIC D 8 2500 346.0 346.0 29.0
TPS2057ADR SOIC D 16 2500 346.0 346.0 33.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Clocks and Timers www.ti.com/clocks Digital Control www.ti.com/digitalcontrol
Interface interface.ti.com Medical www.ti.com/medical
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
RFID www.ti-rfid.com Telephony www.ti.com/telephony
RF/IF and ZigBee® Solutions www.ti.com/lprf Video & Imaging www.ti.com/video
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
Wireless www.ti.com/wireless