Texas Instruments TPS2044DR, TPS2044D, TPS2054DR, TPS2054D Datasheet

TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

135-mΩ -Maximum (5-V Input) High-Side
MOSFET Switch

D

500 mA Continuous Current per Channel

D

Short-Circuit and Thermal Protection With
Overcurrent Logic Output

D

Operating Range...2.7-V to 5.5-V

D

Logic-Level Enable Input

D

2.5-ms Typical Rise Time

D

Undervoltage Lockout

D

20-µA-Maximum Standby Supply Current

D

Bidirectional Switch

D

16-pin SOIC Package

D

Ambient Temperature Range, –40°C to 85°C

D

2-kV Human-Body-Model, 200-V
Machine-Model ESD Protection

D

UL Listed – File No. E169910

description

The TPS2044 and TPS2054 quad power­distribution switches are intended for applications
where heavy capacitive loads and short circuits
are likely to be encountered. The TPS2044 and the TPS2054 incorporate in single packages four 135-mΩ
N-channel MOSFET high-side power switches for power-distribution systems that require multiple power
switches. Each switch is controlled by a logic enable that is compatible with 5-V logic and 3-V logic. Gate drive
is provided by an internal charge pump that controls the power-switch rise times and fall times to minimize
current surges during switching. The charge pump, requiring no external components, allows operation from
supplies as low as 2.7 V.

When the output load exceeds the current-limit threshold or a short is present, the TPS2044 and TPS2054 limit
the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx

) logic
output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch
causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage.
Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry
ensures the switch remains off until valid input voltage is present.

The TPS2044 and TPS2054 are designed to limit at 0.9-A load. These power-distribution switches are available
in 16-pin small-outline integrated-circuit (SOIC) packages and operate over an ambient temperature range of
–40°C to 85°C.

AVAILABLE OPTIONS

RECOMMENDED

TYPICAL SHORT-CIRCUIT

PACKAGED DEVICES

T

A

ENABLE

MAXIMUM CONTINUOUS

LOAD CURRENT

(A)

CURRENT LIMIT AT 25°C

(A)

SOIC

(D)

†

–40°C to 85°C Active low 0.5 0.9 TPS2044D
–40°C to 85°C Active high 0.5 0.9 TPS2054D

†

The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2044DR)

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

GND1

IN1
EN1
EN2

GND2

IN2
EN3
EN4

OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4

TPS2044

D PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

GND1

IN1
EN1
EN2

GND2

IN2
EN3
EN4

OC1
OUT1
OUT2
OC2
OC3
OUT3
OUT4
OC4

TPS2054

D PACKAGE

(TOP VIEW)

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS2044 functional block diagram

Thermal

Sense

Driver

Current

Limit

Charge

Pump

UVLO

CS

†

Driver

Current

Limit

CS

†

Thermal

Sense

Charge

Pump

Power Switch

GND1

EN1

IN1

EN2

OC1

OUT1

OUT2

OC2

†

Current sense

Thermal

Sense

Driver

Current

Limit

Charge

Pump

UVLO

CS

†

Driver

Current

Limit

CS

†

Thermal

Sense

Charge

Pump

Power Switch

GND2

EN3

IN2

EN4

OC3

OUT3

OUT4

OC4

TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NO.

I/O DESCRIPTION

NAME

TPS2044 TPS2054

EN1 3 – I Enable input. logic low turns on power switch, IN1-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN1-OUT2.
EN3 7 – I Enable input. Logic low turns on power switch, IN2-OUT3.
EN4 8 – I Enable input. Logic low turns on power switch, IN2-OUT4.
EN1 – 3 I Enable input. Logic high turns on power switch, IN1-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN1-OUT2.
EN3 – 7 I Enable input. Logic high turns on power switch, IN2-OUT3.
EN4 – 8 I Enable input. Logic high turns on power switch, IN2-OUT4.
GND1 1 1 Ground.
GND2 5 5 Ground.
IN1 2 2 I Input voltage.
IN2 6 6 I Input voltage.
OC1 16 16 O Overcurrent. Logic output active low, IN1-OUT1
OC2 13 13 O Overcurrent. Logic output active low, IN1-OUT2
OC3 12 12 O Overcurrent. Logic output active low, IN2-OUT3
OC4 9 9 O Overcurrent. Logic output active low, IN2-OUT4
OUT1 15 15 O Power-switch output, IN1-OUT1
OUT2 14 14 O Power-switch output, IN1-OUT2
OUT3 11 11 O Power-switch output, IN2-OUT3
OUT4 10 10 O Power-switch output, IN2-OUT4

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

power switch

The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (V

I(INx)

= 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUTx to INx and INx to OUTx
when disabled. The power switch supplies a minimum of 500 mA per switch.

charge pump

An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.

driver

The driver controls the gate voltage of the power switch. T o limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.

enable (ENx

or ENx)

The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 20 µA when a logic high is present on ENx

(TPS2044) or a logic low is present

on ENx (TPS2054). A logic zero input on ENx

or logic high on ENx restores bias to the drive and control circuits

and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.

overcurrent (OCx

)

The OCx

open-drain output is asserted (active low) when an overcurrent or overtemperature condition is

encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.

current sense

A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.

thermal sense

The TPS2044 and TPS2054 implement a dual-threshold thermal trip to allow fully independent operation of the
power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The (OCx

) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.

undervoltage lockout

A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V , a control
signal turns off the power switch.

TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Input voltage range, V

I(INx)

(see Note1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O(OUTx)

(see Note1) –0.3 V to V

I(INx)

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I(ENx)

or V

I(ENx)

–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O(OUTx)

Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T

J

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C 2 kV. . . . . . . . . . . . . . . . . . . . . .

Machine model 0.2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

D 725 mW 5.6 mW/°C 464 mW 377 mW

recommended operating conditions

TPS2044 TPS2054

MIN MAX MIN MAX

UNIT

Input voltage, V

I(INx)

2.7 5.5 2.7 5.5 V

Input voltage, V

I(ENx)

or V

I(ENx)

0 5.5 0 5.5 V

Continuous output current, I

O(OUTx)

0 500 0 500 mA

Operating virtual junction temperature, T

J

–40 125 –40 125 °C

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, V

I(ENx)

= 0 V, V

I(ENx)

= Hi (unless otherwise noted)

power switch

TPS2044 TPS2054

PARAMETER

TEST CONDITIONS

†

MIN TYP MAX MIN TYP MAX

UNIT

V

I(INx)

= 5 V,

IO = 0.5 A

TJ = 25°C,

80 95 80 95

Static drain-source on-state
resistance, 5-V operation

V

I(INx)

= 5 V,

IO = 0.5 A

TJ = 85°C,

90 120 90 120

V

I(INx)

= 5 V,

IO = 0.5 A

TJ = 125°C,

100 135 100 135

mΩ

r

DS(on)

V

I(INx)

= 3.3 V,

IO = 0.5 A

TJ = 25°C,

85 105 85 105

Static drain-source on-state
resistance, 3.3-V operation

V

I(INx)

= 3.3 V,

IO = 0.5 A

TJ = 85°C,

100 135 100 135

V

I(INx)

= 3.3 V,

IO = 0.5 A

TJ = 125°C,

115 150 115 150

p

V

I(INx)

= 5.5 V,

CL = 1 µF,

TJ = 25°C,
RL = 10 Ω

2.5 2.5

trRise time, output

V

I(INx)

= 2.7 V,

CL = 1 µF,

TJ = 25°C,
RL = 10 Ω

3 3

ms

p

V

I(INx)

= 5.5 V,

CL = 1 µF,

TJ = 25°C,
RL = 10 Ω

4.4 4.4

tfFall time, output

V

I(INx)

= 2.7 V,

CL = 1 µF,

TJ = 25°C,
RL = 10 Ω

2.5 2.5

ms

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

enable input ENx or ENx

TPS2044 TPS2054

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

V

IH

High-level input voltage 2.7 V ≤ V

I(INx)

≤ 5.5 V 2 2 V

p

4.5 V ≤ V

I(INx)

≤ 5.5 V 0.8 0.8 V

VILLow-level input voltage

2.7 V≤ V

I(INx)

≤ 4.5 V 0.4 0.4

p

TPS2044 V

I(ENx

)

= 0 V or V

I(ENx)

= V

I(IN)

–0.5 0.5

IIInput current

TPS2054 V

I(ENx)

= V

I(INx)

or V

I(ENx)

= 0 V –0.5 0.5

µ

A

t

on

Turnon time CL = 100 µF, RL=10 Ω 20 20 ms

t

off

Turnoff time CL = 100 µF, RL=10 Ω 40 40

current limit

TPS2044 TPS2054

PARAMETER

TEST CONDITIONS

†

MIN TYP MAX MIN TYP MAX

UNIT

I

OS

Short-circuit output current

V

I(INx)

= 5 V, OUT connected to GND,

Device enable into short circuit

0.7 0.9 1.1 0.7 0.9 1.1 A

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, V

I(ENx)

= 0 V, V

I(ENx)

= Hi (unless otherwise noted) (continued)

supply current

TPS2044 TPS2054

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

pp

TJ = 25°C

0.03 2

Su ly

current,

No Load

V

I(ENx)

= V

I(INx)

–40°C ≤ TJ ≤ 125°C

TPS2044

20

,

low-level

on OUTx

TJ = 25°C

0.03 2

µ

A

output

V

I(ENx)

= 0

V

–40°C ≤ TJ ≤ 125°C

TPS2054

20

pp

TJ = 25°C

160 200

Su ly

current,

No Load

V

I(ENx)

= 0

V

–40°C ≤ TJ ≤ 125°C

TPS2044

200

,

high-level

on OUTx

TJ = 25°C

160 200

µ

A

output

V

I(ENx)

=

V

I(INx)

–40°C ≤ TJ ≤ 125°C

TPS2054

200

Leakage

OUTx

V

I(ENx)

= V

I(INx)

–40°C ≤ TJ ≤ 125°C TPS2044 200

g

current

connecte

d

to ground

V

I(ENx)

= 0 V –40°C ≤ TJ ≤ 125°C TPS2054 200

µ

A

Reverse

IN = high

V

I(EN

)

= 0 V

°

TPS2044 0.3

leak

age

current

g

impedance

V

I(EN)

= Hi

T

J

=

25°C

TPS2054 0.3

µ

A

undervoltage lockout

TPS2044 TPS2054

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ = 25°C 100 100 mV

overcurrent OCx

TPS2044 TPS2054

PARAMETER

TEST CONDITIONS

MIN TYP MAX MIN TYP MAX

UNIT

Sink current

†

VO = 5 V 10 10 mA

Output low voltage IO = 5 mA, V

OL(OCx)

0.5 0.5 V

Off-state current

†

VO = 5 V, VO = 3.3 V 1 1 µA

†

Specified by design, not production tested.

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

RL CL

OUTx

t

r

t

f

90%

90%

10%

10%

50%

50%

90%

10%

V

O(OUTx)

V

I(ENx)

V

O(OUTx)

VOLTAGE WAVEFORMS

TEST CIRCUIT

t

on

t

off

50%

50%

90%

10%

V

I(ENx)

V

O(OUTx)

t

on

t

off

Figure 1. Test Circuit and Voltage Waveforms

Figure 2. Turnon Delay and Rise Time

with 0.1-µF Load

Figure 3. Turnoff Delay and Fall Time

with 0.1-µF Load

V

O(OUT)

(2 V/div)

0123456

t – Time – ms

78910

V

I(IN)

= 5 V
TA = 25°C
CL = 0.1 µF

V

I(EN)

(5 V/div)

0 1000 2000 3000

t – Time – ms

4000 5000

V

I(IN)

= 5 V
TA = 25°C
CL = 0.1 µF

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Figure 4. Turnon Delay and Rise Time

with 1-µF Load

Figure 5. Turnoff Delay and Fall Time

with 1-µF Load

0123456

t – Time – ms

78910

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

V

I(IN)

= 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω

0 2 4 6 8 10 12

t – Time – ms

14 16 18 20

V

I(IN)

= 5 V
TA = 25°C
CL = 1 µF
RL = 10 Ω

V

I(EN)

(5 V/div)

V

O(OUT)

(2 V/div)

Figure 6. TPS2044, Short-Circuit Current,

Device Enabled into Short

012 34 56

t – Time – ms

78910

I

O(OUT)

(0.2 A/div)

V

I(IN)

= 5 V

TA = 25°C

V

I(EN)

(5 V/div)

Figure 7. TPS2044, Threshold Trip Current

with Ramped Load on Enabled Device

01020 30405060

t – Time – ms

70 80 90 100

I

O(OUT)

(0.5 A/div)

V

I(IN)

= 5 V

TA = 25°C

V

O(OUT)

(2 V/div)

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

Figure 8. Inrush Current with 100-µF, 220-µF

and 470-µF Load Capacitance

0 2 4 6 8 10 12

t – Time – ms

14 16 18 20

V

I(IN)

= 5 V
TA = 25°C
RL = 10 Ω

V

I(EN)

(5 V/div)

I

O(OUT)

(o.2 A/div)

470 µF

220 µF

100 µF

Figure 9. Ramped Load on Enabled Device

V

O(OC)

(5 V/div)

I

O(OUT)

(0.5 A/div)

V

I(IN)

= 5 V
Load Ramp,1A/100 ms
TA = 25°C

0 20 40 60 80 100 120

t – Time – ms

140 160 180 200

Figure 10. 4-Ω Load Connected to Enabled Device

I

O(OUT)

(0.5 A/div)

V

I(IN)

= 5 V

TA = 25°C

0 400 800 1200 1600 2000

V

O(OC)

(5 V/div)

t – Time – µs

Figure 11. 1-Ω Load Connected

to Enabled Device

I

O(OUT)

(1 A/div)

V

I(IN)

= 5 V

TA = 25°C

0 20 40 60 80 100 120 140 160 180 200

V

O(OC)

(5 V/div)

t – Time – µs

TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 12

4.5

4

3.5

3

2.5 3 3.5 4 4.5

Turn-On Delay – ms

5

5.5

TURNON DELAY

vs

INPUT VOLTAGE

6

5 5.5 6

VI – Input Voltage – V

CL = 1 µF
RL = 10 Ω
TA = 25°C

Figure 13

13

12

10

3

2.5 3 3.5 4 4.5

Turn-Off Delay – ms

15

16

TURNOFF DELAY

vs

INPUT VOLTAGE

17

5 5.5 6

14

11

VI – Input Voltage – V

CL = 1 µF
RL = 10 Ω
TA = 25°C

Figure 14

2.7

2.6

2.5

0.1 0.2 0.3 0.4 0.5

– Rise Time – ms

2.8

2.9

RISE TIME

vs

LOAD CURRENT

3

0.6 0.7 0.8 0.9

r

t

IL – Load Current – A

V

I(INx)

= 5 V
CL = 1 µF
TA = 25°C

Figure 15

2.9

2.7

2.5

0.1 0.2 0.3 0.4 0.5

– Fall Time – ms

3.1

3.3

FALL TIME

vs

LOAD CURRENT

3.5

0.6 0.7 0.8 0.9

f

t

IL – Load Current – A

V

I(INx)

= 5 V
TA = 25°C
CL = 1 µF

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 16

140

120

100

–50 –25 0 25 50

– Supply Current, Output Enabled –

160

180

SUPPLY CURRENT, OUTPUT ENABLED

vs

JUNCTION TEMPERATURE

200

75 100 125 150

I

I(IN)

Aµ

TJ – Junction Temperature – °C

V

I(INx)

= 5.5 V

V

I(INx)

= 5 V

V

I(INx)

= 4 V

V

I(INx)

= 3.3 V

V

I(INx)

= 2.7 V

Figure 17

1000

600

200

–200

–50 –25 0 25 50 75

1400

1800

SUPPLY CURRENT, OUTPUT DISABLED

vs

JUNCTION TEMPERATURE

2000

100 125 150

1600

1200

800

400

0

– Supply Current, Output Disabled – nA

I

I(IN)

TJ – Junction Temperature – °C

V

I(INx)

= 5.5 V

V

I(INx)

= 5 V

V

I(INx)

= 4 V

V

I(INx)

= 2.7 V

Figure 18

140

120

100

2.5 3 3.5 4

4.5

– Supply Current, Output Enabled –

160

180

SUPPLY CURRENT, OUTPUT ENABLED

vs

INPUT VOLTAGE

200

5 5.5 6

I

I(IN)

Aµ

VI – Input Voltage – V

TJ = –40°C

TJ = 125°C

TJ = 85°C

TJ = 25°C

TJ = 0°C

Figure 19

800

400

0

–400

2.5 3 3.5 4 4.5

1200

1600

SUPPLY CURRENT, OUTPUT DISABLED

vs

INPUT VOLTAGE

2000

5 5.5 6

– Supply Current, Output Disabled – nA
I

I(IN)

VI – Input Voltage – V

TJ = –40°C

TJ = 125°C

TJ = 85°C

TJ = 25°C

TJ = 0°C

TPS2044, TPS2054

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TYPICAL CHARACTERISTICS

Figure 20

100

75

50

–50 –25 0 25 50 75

– Static Drain-Source On-State Resistance – m

125

150

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs

JUNCTION TEMPERATURE

175

100 125 150

Ω

r

DS(on)

TJ – Junction Temperature –°C

V

I(INx)

= 5 V

V

I(INx)

= 4.5 V

V

I(INx)

= 3.3 V

V

I(INx)

= 2.7 V

IO = 0.5 A

Figure 21

100

75

50

2.5 3 3.5 4 4.5

125

150

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs

INPUT VOLTAGE

175

5 5.5 6

– Static Drain-Source On-State Resistance – m

Ω

r

DS(on)

VI – Input Voltage – V

TJ = –40°C

TJ = 125°C

TJ = 85°C

TJ = 25°C

TJ = 0°C

IO = 0.5 A

Figure 22

50

25

0

0.1 0.2 0.4

– Input-to-Output Voltage – mV

75

INPUT-TO-OUTPUT VOLTAGE

vs

LOAD CURRENT

100

0.5 0.6

V

I(INx)

–

V

I(OUTx)

IL – Load Current – A

TA = 25°C

V

I(INx)

= 5 V

V

I(INx)

= 2.7 V

V

I(INx)

= 4.5 V

V

I(INx)

= 3.3 V

Figure 23

0.85

0.8

2.5 3 3.5 4

– Short-circuit Output Current – A

0.9

SHORT-CURCUIT OUTPUT CURRENT

vs

INPUT VOLTAGE

0.95

4.5 5 65.5

I

OS

VI – Input Voltage – V

TJ = –40°C

TJ = 125°C

TJ = 25°C

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

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TYPICAL CHARACTERISTICS

Figure 24

1.15

1.125

1.1

2.5 3 3.5 4

Threshold Trip Current – A

1.175

THRESHOLD TRIP CURRENT

vs

INPUT VOLTAGE

1.2

4.5 5 65.5

VI – Input Voltage – V

TA = 25°C
Load Ramp = 1 A/10 ms

Figure 25

0.8
–50 –25 0 25 50

0.9

SHORT-CIRCUIT OUTPUT CURRENT

vs

JUNCTION TEMPERATURE

0.95

75 100 125

0.85

TJ – Junction Temperature – °C

– Short-circuit Output Current – A

I

OS

V

I(INx)

= 5 V

V

I(INx)

= 4 V

V

I(INx)

= 2.7 V

Figure 26

2.2

2.1

2

–50 –25 0 25 50 75

UVLO – Undervoltage Lockout – V

2.3

2.4

UNDERVOLTAGE LOCKOUT

vs

JUNCTION TEMPERATURE

2.5

100 125 150

TJ – Junction Temperature – °C

Start Threshold

Stop Threshold

Figure 27

250

150
100

0

0 2.5 5 7.5

Current Limit Response –

350

450

Peak Current – A

CURRENT LIMIT RESPONSE

vs

PEAK CURRENT

500

10 12.5

400

300

200

50

sµ

V

I(INx)

= 5 V

TA = 25°C

TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

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TYPICAL CHARACTERISTICS

4

2

0

0 2.5 5 7.5

Response Time –

6

Peak Current – A

OVERCURRENT RESPONSE TIME (OCx)

vs

PEAK CURRENT

8

10 12.5

sµ

V

I(INx)

= 5 V

TA = 25°C

Figure 28

APPLICATION INFORMATION

IN1

OC1

EN1

OC3

EN3

2

16
13

12

9

15

6

0.1 µF 22 µF

0.1 µF 22 µF

Load

Load

OUT1

OUT2

Power Supply

2.7 V to 5.5 V
IN2

OC2

OC4

14

11

0.1 µF 22 µF

0.1 µF 22 µF

Load

Load

OUT3

OUT4

10EN2

EN4

3
4

7
8

GND1

GND2

1
5

Figure 29. Typical Application

TPS2044, TPS2054
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APPLICATION INFORMATION

power-supply considerations

A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy .
This precaution reduces power-supply transients that may cause ringing on the input. Additionally , bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.

overcurrent

A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FET s do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a
constant output current and reduces the output voltage accordingly . Complete shutdown occurs only if the fault
is present long enough to activate thermal limiting.

Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before V

I(INx)

has been applied (see Figure 6). The TPS2044 and TPS2054 sense the short

and immediately switch into a constant-current output.
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high

currents may flow for a short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode.

In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS2044 and TPS2054 are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.

TPS2044, TPS2054

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APPLICATION INFORMATION

OC

response

The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter of 500 µs (see
Figure 30) can be connected to the OC

pin to reduce false overcurrent reporting. Using low-ESR electrolytic
capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing
a low impedance energy source, thereby reducing erroneous overcurrent reporting.

GND1
IN1
EN1

EN2

OC1

OC2

OUT1
OUT2

TPS2044

GND1
IN1
EN1

EN2

OC1

OC2

OUT1
OUT2

TPS2044

R

pullup

V+

R

filter

R

pullup

C

filter

To USB
Controller

V+

OC3

OC4

OUT3
OUT4

GND2
IN2
EN3

EN4

GND2
IN2
EN3

EN4

OC3

OC4

OUT3
OUT4

Figure 30. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses

power dissipation and junction temperature

The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. The first step is to find r

DS(on)

at
the input voltage and operating temperature. As an initial estimate, use the highest operating ambient
temperature of interest and read r

DS(on)

from Figure 21. Next, calculate the power dissipation using:

P

D

+

r

DS(on

)

I

2

Finally, calculate the junction temperature:

T

J

+

P

D

R

q

JA

)

T

A

Where:

T

A

= Ambient Temperature °C

R

θJA

= Thermal resistance SOIC = 172°C/W

Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

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APPLICATION INFORMATION

thermal protection

Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS2044 and TPS2054 into constant current mode, which causes
the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch
is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.

The TPS2044 and TPS2054 implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach
160°C, both switches turn off. The OC

open-drain output is asserted (active low) when overtemperature or

overcurrent occurs.

undervoltage lockout (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.

universal serial bus (USB) applications

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.

USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.

The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:

D

Hosts/self-powered hubs (SPH)

D

Bus-powered hubs (BPH)

D

Low-power, bus-powered functions

D

High-power, bus-powered functions

D

Self-powered functions

Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2044 and
TPS2054 can provide power-distribution solutions for many of these classes of devices.

TPS2044, TPS2054

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APPLICATION INFORMATION

host/self-powered and bus-powered hubs

Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 31). This power supply must provide from 5.25 V to 4.75 V to the board side of
the downstream connection under full-load and no-load conditions. Hosts and SPHs must have current-limit
protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs,
monitors, printers, and stand-alone hubs.

IN1

OC1
EN1
OC2
EN2

GND1

0.1 µF

2

11

3

13

4

15

14

33 µF

33 µF

GND

1

OUT1

OUT2

TPS2044

Power Supply

D+
D–

V

BUS

GND

D+
D–

V

BUS

Downstream

USB Ports

USB

Controller

3.3 V 5 V

OC3
EN3
OC4
EN4

12

7
9

8

6

IN2

+

+

5

GND2

11

10

33 µF

33 µF

GND

OUT3

OUT4

D+
D–

V

BUS

GND

D+
D–

V

BUS

+

+

†

†

†

†

†

An RC filter may be needed, see Figure 36

Figure 31. Typical Four-Port USB Host/Self-Powered Hub

Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on power up, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

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APPLICATION INFORMATION

low-power bus-powered functions and high-power bus-powered functions

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA, and high-power functions must draw less than 100 mA at powerup
and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination
of 44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 32).

IN1

OC1

EN1

OC3

EN3

2

16
13

12

9

15

6

0.1 µF 10 µF

0.1 µF 10 µF

Internal

Function

OUT1

OUT2

Power Supply

3.3 V

IN2

OC2

OC4

14

11

0.1 µF 10 µF

0.1 µF 10 µF

OUT3

OUT4

10

EN2

EN4

3
4

7
8

GND1

GND2

1
5

Internal

Function

Internal

Function

Internal

Function

0.1 µF

10 µF

USB

Control

GND

V

BUS

D–

D+

TPS2044

Figure 32. High-Power Bus-Powered Function

TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

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APPLICATION INFORMATION

USB power-distribution requirements

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.

D

Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB V

BUS

D

Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µF)

D

Functions must:
– Limit inrush currents
– Power up at <100 mA

The feature set of the TPS2044 and TPS2054 allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable
and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input
ports for bus-power functions (see Figure 33).

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

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APPLICATION INFORMATION

Figure 33. Hybrid Self/Bus-Powered Hub Implementation

DP1

DM1

DP2

DM2

DP3

DM3

DP4

PWRON1

OVRCUR1

PWRON2

OVRCUR2

PWRON3

OVRCUR3

PWRON4

OVRCUR4

DM4

DP0
DM0

V

CC

XTAL1

XTAL2

OCSOFF

SN75240

D +
D –

5 V

GND

D +
D –

5 V

D +
D –

5 V

D +
D –

5 V

48-MHz
Crystal

Downstream

Ports

TUSB2040

Hub Controller

Tuning
Circuit

ABC

D

33 µF

†

SN75240

ABC

D

GND

GND

GND

33 µF

†

33 µF

†

33 µF

†

D +
D –

Upstream
Port

TPS2041

SN75240

A

B

5 V

GND

C
D

1 µF

IN

GND

Ferrite Beads

Ferrite Beads

Ferrite Beads

Ferrite Beads

BUSPWR

GANGED

Tie to TPS2041 EN

Input

OC EN

OUT

5 V Power

Supply

IN

GND

3.3 V

4.7 µF

0.1 µF

4.7 µF

EN1

IN1

OC1

OUT1

TPS2044

EN2

OC2

OUT2

0.1 µF

0.1 µF

GND

†

USB rev 1.1 requires 120 µF per hub.

EN3

OC3

OUT3

EN4

OC4

OUT4

IN2

GND1
GND2

TPS76333

TPS2044, TPS2054

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APPLICATION INFORMATION

generic hot-plug applications (see Figure 34)

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS2044 and TPS2054, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS2044 and TPS2054 also ensures the switch will be off after the card has been removed, and the switch
will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every
insertion of the card or module.

Power

Supply

Block of
Circuitry

0.1 µF

1000 µF
Optimum

2.7 V to 5.5 V

PC Board

Overcurrent Response

TPS2044

GND1
IN1
EN1

OC1
OUT1
OUT2

OC2

EN2
GND2

EN3

IN2

EN4

OC3
OUT3
OUT4

OC4

Block of
Circuitry

Block of
Circuitry

Block of
Circuitry

Figure 34. Typical Hot-Plug Implementation

By placing the TPS2044 and TPS2054 between the V

CC

input and the rest of the circuitry , the input power will
reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing
a slow voltage ramp at the output of the device. This implementation controls system surge currents and
provides a hot-plugging mechanism for any device.

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES

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MECHANICAL DATA

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

4040047/D 10/96

0.228 (5,80)

0.244 (6,20)

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

1

14

0.014 (0,35)

0.020 (0,51)

A

0.157 (4,00)

0.150 (3,81)

7

8

0.044 (1,12)

0.016 (0,40)

Seating Plane

0.010 (0,25)

PINS **

0.008 (0,20) NOM

A MIN

A MAX

DIM

Gage Plane

0.189

(4,80)

(5,00)

0.197

8

(8,55)

(8,75)

0.337

14

0.344

(9,80)

16

0.394

(10,00)

0.386

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated