Texas Instruments TPS2010D, TPS2012PWLE, TPS2012PWR, TPS2012DR, TPS2012D Datasheet

TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

95-mΩ Max (5.5-V Input) High-Side MOSFET
Switch With Logic Compatible Enable Input

D

Short-Circuit and Thermal Protection

D

Typical Short-Circuit Current Limits:

0.4 A, TPS2010; 1.2 A, TPS2011;
2 A, TPS2012; 2.6 A, TPS2013

D

Electrostatic-Discharge Protection, 12-kV
Output, 6-kV All Other Terminals

D

Controlled Rise and Fall Times to Limit
Current Surges and Minimize EMI

D

SOIC-8 Package Pin Compatible With the
Popular Littlefoot Series When GND Is
Connected

D

2.7-V to 5.5-V Operating Range

D

10-µA Maximum Standby Current

D

Surface-Mount SOIC-8 and TSSOP-14
Packages

D

–40°C to 125°C Operating Junction
T emperature Range

description

The TPS201x family of power-distribution switches is intended for applications where heavy capacitive loads
and short circuits are likely to be encountered. The high-side switch is a 95-mΩ N-channel MOSFET . Gate drive
is provided by an internal driver and charge pump designed to control the power switch rise times and fall times
to minimize current surges during switching. The charge pump operates at 100 kHz, requires no external
components, and allows operation from supplies as low as 2.7 V . When the output load exceeds the current-limit
threshold or a short circuit is present, the TPS201x limits the output current to a safe level by switching into a
constant-current mode. Continuous heavy overloads and short circuits increase power dissipation in the switch
and cause the junction temperature to rise. If the junction temperature reaches approximately 180°C, a thermal
protection circuit shuts the switch off to prevent damage. Recovery from thermal shutdown is automatic once
the device has cooled sufficiently.

The members of the TPS201x family differ only in short-circuit current threshold. The TPS2010 is designed to
limit at 0.4-A load; the other members of the family limit at 1.2 A, 2 A, and 2.6 A (see the available options table).
The TPS201x family is available in 8-pin small-outline integrated circuit (SOIC) and 14-pin thin shink
small-outline (TSSOP) packages and operates over a junction temperature range of –40°C to 125°C. Versions
in the 8-pin SOIC package are drop-in replacements for Siliconix’s Littlefoot power PMOS switches, except
that GND must be connected.

Copyright  1995, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4

8
7
6
5

GND

IN
IN

EN

OUT
OUT
OUT
OUT

D PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7

14
13
12
11
10

9
8

GND

IN
IN
IN
IN
IN

EN

OUT
OUT
OUT
OUT
OUT
OUT
OUT

PW PACKAGE

(TOP VIEW)

TPS2010, TPS2011, TPS2012, TPS2013
POWER-DISTRIBUTION

SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

RECOMMENDED MAXIMUM TYPICAL SHORT-CIRCUIT

PACKAGED DEVICES

CHIP

T

J

CONTINUOUS LOAD CURRENT

(A)

OUTPUT CURRENT LIMIT AT 25°C

(A)

SOIC

(D)

†

TSSOP

(PW)

‡

FORM

(Y)

0.2 0.4 TPS2010D TPS2010PWLE TPS2010Y

°

°

0.6 1.2 TPS2011D TPS2011PWLE TPS2011Y

–

40°C to 125°C

1 2 TPS2012D TPS2012PWLE TPS2012Y

1.5 2.6 TPS2013D TPS2013PWLE TPS2013Y

†

The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2010DR).

‡

The PW package is only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TPS2010PWLE).

functional block diagram

Power Switch

Current

Limit

Driver

Thermal

Sense

Charge

Pump

IN

EN

GND

OUT

CS

†

†

Current sense

Terminal Functions

TERMINAL

NO.

I/O DESCRIPTION

NAME

D PW

EN 4 7 I Enable input. Logic low turns power switch on.
GND 1 1 I Ground
IN 2, 3 2–6 I Input voltage
OUT 5–8 8–14 O Power-switch output

detailed description

power switch

The power switch is an N-channel MOSFET with a maximum on-state resistance of 95 mΩ (V

I(IN)

= 5.5 V),

configured as a high-side switch.

charge pump

An internal 100-kHz charge pump supplies power to the driver circuit and provides the necessary voltage to pull
the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and
requires very little supply current.

TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

driver

The driver controls the gate voltage of the power switch. T o limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range instead of the
microsecond or nanosecond range for a standard FET.

enable (EN)

A logic high on the EN input turns off the power switch and the bias for the charge pump, driver , and other circuitry
to reduce the supply current to less than 10 µA. A logic zero input restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.

current sense

A sense FET monitors the current supplied to the load. The sense FET is a much more efficient way to measure
current than conventional resistance methods. When an overload or short circuit is encountered, the
current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives
the power FET into its linear region, which switches the output into a constant current mode and simply holds
the current constant while varying the voltage on the load.

thermal sense

An internal thermal-sense circuit shuts the power switch off when the junction temperature rises to
approximately 180°C. Hysteresis is built into the thermal sense, and after the device has cooled approximately
20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed.

TPS201xY chip information

This chip, when properly assembled, displays characteristics similar to the TPS201xC. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.

TPS2010, TPS2011, TPS2012, TPS2013
POWER-DISTRIBUTION

SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS

81

72

TPS201xY

(2)

(6)

(1)

(3)

(7)

(8)

(5)(4)

OUTGND

IN
IN

EN

OUT
OUT

OUT

(2)

(1)

(3)

(4)

(6)

(7)(8)

(5)

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Input voltage range, V

I(IN)

(see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(see Note 1) –0.3 V to V

I(IN)

+0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI at EN –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T

J

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 125°C

POWER RATING

D 725 mW 5.8 mW/°C 464 mW 145 mW

PW 700 mW 5.6 mW/°C 448 mW 140 mW

TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN MAX UNIT

Input voltage, V

I(IN)

2.7 5.5 V

Input voltage, VI at EN 0 5.5 V

TPS2010 0 0.2

p

TPS2011 0 0.6

Continuous output current, I

O

TPS2012 0 1

A

TPS2013 0 1.5

Operating virtual junction temperature, T

J

–40 125 °C

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, EN = 0 V (unless otherwise noted)

power switch

PARAMETER

TEST CONDITIONS

†

TPS2010, TPS2011
TPS2012, TPS2013

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

V

I(IN)

= 5.5 V, TJ = 25°C 75 95

V

I(IN)

= 4.5 V, TJ = 25°C 80 110

On-state resistance

V

I(IN)

= 3 V, TJ = 25°C 120 175

mΩ

V

I(IN)

= 2.7 V, TJ = 25°C 140 215

p

TJ = 25°C 0.001 1

Output leakage current

EN

=

V

I(IN)

–40°C ≤ TJ ≤ 125°C 10

µ

A

p

V

I(IN)

= 5.5 V, TJ = 25°C, CL = 1 µF 4

trOutput rise time

V

I(IN)

= 2.7 V, TJ = 25°C, CL = 1 µF 3.8

ms

p

V

I(IN)

= 5.5 V, TJ = 25°C, CL = 1 µF 3.9

tfOutput fall time

V

I(IN)

= 2.7 V, TJ = 25°C, CL = 1 µF 3.5

ms

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

enable input (EN)

PARAMETER TEST CONDITIONS

TPS2010, TPS2011
TPS2012, TPS2013

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

High-level input voltage 2.7 V ≤ V

I(IN)

≤ 5.5 V 2 V

p

4.5 V ≤ V

I(IN)

≤ 5.5 V 0.8

Low-level input voltage

2.7 V ≤ V

I(IN)

< 4.5 V 0.4

V

Input current

EN = 0 V or EN = V

I(IN)

–0.5 0.5 µA

t

PLH

Propagation (delay) time, low-to-high-level output CL = 1 µF 20

t

PHL

Propagation (delay) time, high-to-low-level output CL = 1 µF 40

ms

current limit

PARAMETER

TEST CONDITIONS

†

TPS2010, TPS2011
TPS2012, TPS2013

UNIT

TEST CONDITIONS

MIN TYP MAX

°

TPS2010 0.22 0.4 0.6

T

J

=

25 C

,

V

I

(IN)

= 5.5 V,

TPS2011 0.66 1.2 1.8

Short-circuit current

I(IN)

OUT connected to GND, device

TPS2012 1.1 2 3

A

enabled into short circu

it

TPS2013 1.65 2.6 4.5

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

TPS2010, TPS2011, TPS2012, TPS2013
POWER-DISTRIBUTION

SLVS097A – DECEMBER 1994 – REVISED AUGUST 1995

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, EN = 0 V (unless otherwise noted) (continued)

supply current

PARAMETER TEST CONDITIONS

TPS2010, TPS2011
TPS2012, TPS2013

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

pp

p

TJ = 25°C 0.015 1

Supply current, low-level output

EN

=

V

I(IN)

–40°C ≤ TJ ≤ 125°C 10

µ

A

pp

p

TJ = 25°C 73 100

Supply current, high-level output

EN

= 0

V

–40°C ≤ TJ ≤ 125°C 100

µ

A

electrical characteristics over recommended operating junction temperature range, V

I(IN)

= 5.5 V,

I

O

= rated current, EN = 0 V, TJ = 25°C (unless otherwise noted)

power switch

PARAMETER

TEST CONDITIONS

†

TPS2010Y, TPS201 1Y

TPS2012Y, TPS2013Y

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

V

I(IN)

= 5.5 V, 75

V

I(IN)

= 4.5 V, 80

On-state resistance

V

I(IN)

= 3 V, 120

mΩ

V

I(IN)

= 2.7 V, 140

Output leakage current

EN = V

I(IN)

0.001 µA

p

V

I(IN)

= 5.5 V, CL = 1 µF 4

Output rise time

V

I(IN)

= 2.7 V, CL = 1 µF 3.8

ms

p

V

I(IN)

= 5.5 V, CL = 1 µF 3.9

Output fall time

V

I(IN)

= 2.7 V, CL = 1 µF 3.5

ms

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

current limit

PARAMETER

TEST CONDITIONS

†

TPS2010Y, TPS201 1Y

TPS2012Y, TPS2013Y

UNIT

MIN TYP MAX

Short-circuit current

V

I(IN)

= 5.5 V,
OUT connected to GND,
Device enabled into short circuit

0.4 A

†

Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

supply current

PARAMETER TEST CONDITIONS

TPS2010Y, TPS201 1Y

TPS2012Y, TPS2013Y

UNIT

PARAMETER

TEST CONDITIONS

MIN TYP MAX

UNIT

Supply current, low-level output

EN = V

I(IN)

0.015 µA

Supply current, high-level output

EN = 0 V

73 µA