Texas Instruments TMS320DM6441ZWT, TMS320DM6441 Datasheet

www.ti.com

1 Digital Media System-on-Chip (DMSoC)

1.1 Features

• High-Performance Digital Media SoC

– C64x+™ DSP Clock Rate

• 405-MHz (Max) at 1.05 V or 513-MHz

(Max) at 1.2 V

– ARM926EJ-S™ Clock Rate

• 202.5-MHz (Max) at 1.05 V or 256-MHz

(Max) at 1.2 V
– Eight 32-Bit C64x+ Instructions/Cycle
– 4752 C64x+ MIPS
– Fully Software-Compatible With C64x /

ARM9™

• Advanced Very-Long-Instruction-Word (VLIW)

TMS320C64x+™ DSP Core
– Eight Highly Independent Functional Units

• Six ALUs (32-/40-Bit), Each Supports

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

Arithmetic per Clock Cycle

• Two Multipliers Support Four 16 x 16-Bit

Multiplies (32-Bit Results) per Clock

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit

Results) per Clock Cycle
– Load-Store Architecture With Non-Aligned

Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Additional C64x+™ Enhancements

• Protected Mode Operation

• Exceptions Support for Error Detection

and Program Redirection

• Hardware Support for Modulo Loop

Operation

• C64x+ Instruction Set Features

– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– Compact 16-Bit Instructions
– Additional Instructions to Support Complex

Multiplies

• C64x+ L1/L2 Memory Architecture

– 32K-Byte L1P Program RAM/Cache (Direct

Mapped)
– 80K-Byte L1D Data RAM/Cache (2-Way

Set-Associative)
– 64K-Byte L2 Unified Mapped RAM/Cache

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

(Flexible RAM/Cache Allocation)

• ARM926EJ-S Core

– Support for 32-Bit and 16-Bit (Thumb®

Mode) Instruction Sets

– DSP Instruction Extensions and Single

Cycle MAC
– ARM® Jazelle® Technology
– Embedded ICE-RT™ Logic for Real-Time

Debug

• ARM9 Memory Architecture

– 16K-Byte Instruction Cache
– 8K-Byte Data Cache
– 16K-Byte RAM
– 8K-Byte ROM

• Embedded Trace Buffer™ (ETB11™) With 4KB

Memory for ARM9 Debug

• Endianness: Little Endian for ARM and DSP

• Video Processing Subsystem

– Front End Provides:

• CCD and CMOS Imager Interface

• BT.601/BT.656 Digital YCbCr 4:2:2

(8-/16-Bit) Interface

• Preview Engine for Real-Time Image

Processing

• Glueless Interface to Common Video

Decoders

• Histogram Module

• Auto-Exposure, Auto-White Balance,

and Auto-Focus Module

• Resize Engine

• Resize Images From 1/4x to 4x

• Separate Horizontal/Vertical Control

• Video Processing Subsystem (Continued)

– Back End Provides:

• Hardware On-Screen Display (OSD)

• Four 54-MHz DACs for a Combination of

• Composite NTSC/PAL Video

• Luma/Chroma Separate Video

(S-video)

• Component (YPbPr or RGB) Video

(Progressive)

• Digital Output

• 8-/16-bit YUV or up to 24-Bit RGB

• HD Resolution

• Up to Two Video Windows

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2006–2007, Texas Instruments Incorporated

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

• External Memory Interfaces (EMIFs) • 10/100 Mb/s Ethernet MAC (EMAC)

– 32-Bit DDR2 SDRAM Memory Controller – IEEE 802.3 Compliant

With 256M-Byte Address Space (1.8-V I/O)

– Asynchronous16-Bit Wide EMIF (EMIFA)

With 128M-Byte Address Reach

• Flash Memory Interfaces

• NOR (8-/16-Bit-Wide Data)

• NAND (8-/16-Bit-Wide Data)

• Flash Card Interfaces

– Multimedia Card (MMC)/Secure Digital (SD)

with Secure Data I/O (SDIO)

– CompactFlash Controller With True IDE

Mode
– SmartMedia
– Memory Stick® and Memory Stick Pro™

• Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

• Two 64-Bit General-Purpose Timers (Each

Configurable as Two 32-Bit Timers)

• One 64-Bit Watch Dog Timer

• Three UARTs (One with RTS and CTS Flow

Control)

• One Serial Port Interface (SPI) With Two

Chip-Selects

• Master/Slave Inter-Integrated Circuit

(I2C Bus™)

• Audio Serial Port (ASP)

– I2S
– AC97 Audio Codec Interface
– Standard Voice Codec Interface (AIC12)

– Media Independent Interface (MII)

• VLYNQ™ Interface (FPGA Interface)

• Host Port Interface (HPI) with 16-Bit

Multiplexed Address/Data

• USB Port With Integrated 2.0 PHY

– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host

• Three Pulse Width Modulator (PWM) Outputs

• On-Chip ARM ROM Bootloader (RBL) to Boot

From NAND Flash or UART

• ATA/ATAPI I/F (ATA/ATAPI-5 Specification)

• Individual Power-Saving Modes for ARM/DSP

• Flexible PLL Clock Generators

• IEEE-1149.1 (JTAG) Boundary-

Scan-Compatible

• Up to 71 General-Purpose I/O (GPIO) Pins

(Multiplexed With Other Device Functions)

• 361-Pin Pb-Free BGA Package

(ZWT Suffix), 0.8-mm Ball Pitch

• 0.09-µm/6-Level Cu Metal Process (CMOS)

• 3.3-V and 1.8-V I/O, 1.05-V or 1.2-V internal

• Applications:

– Digital Media
– Networked Media Encode/Decode
– Video Imaging
– Portable Media Players

2 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback

www.ti.com

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

1.2 Description

The TMS320DM6441 (also referenced as DM6441) leverages TI’s DaVinci™ technology to meet the

networked media encode and decode application processing needs of next-generation embedded devices.

The DM6441 enables OEMs and ODMs to quickly bring to market devices featuring robust operating

systems support, rich user interfaces, high processing performance, and long battery life through the

maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6441 provides benefits of both DSP and Reduced Instruction Set

Computer (RISC) technologies, incorporating a high-performance TMS320C64x+ DSP core and an

ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and

processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and

memory system can operate continuously.

The ARM core incorporates:

• A coprocessor 15 (CP15) and protection module

• Data and program memory management units (MMUs) with table look-aside buffers.

• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual

index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the

TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation

high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas

Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a

code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of

the C64x+ DSP with added functionality and an expanded instruction set.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and

C64x+ CPU, respectively.

With performance of up to 4104 million instructions per second (MIPS) at a clock rate of 513 MHz, the

C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses

the operational flexibility of high-speed controllers and the numerical capability of array processors. The

C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly

independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The

eight functional units include instructions to accelerate the performance in video and imaging applications.

The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2052 million

MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4104 MMACS. For more details

on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide

(literature number SPRU732 ).

The DM6441 also has application-specific hardware logic, on-chip memory, and additional on-chip

peripherals similar to the other C6000 DSP platform devices. The DM6441 core uses a two-level

cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the

Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2)

consists of an 512K-bit memory space that is shared between program and data space. L2 memory can

be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: two configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a

management data input/output (MDIO) module; an inter-integrated circuit (I2C) bus interface; one audio

serial port (ASP); two 64-bit general-purpose timers each configurable as two independent 32-bit timers;

one 64-bit watchdog timer; up to 71 pins of general-purpose input/output (GPIO) with programmable

interrupt/event generation modes, multiplexed with other peripherals; three UARTs with hardware

handshaking support on one UART; three pulse width modulator (PWM) peripherals; and two external

memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals,

and a higher speed synchronous memory interface for DDR2.

Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) 3

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

The DM6441 device includes a video processing subsystem (VPSS) with two configurable video/imaging

peripherals: one video processing front-end (VPFE) input used for video capture, one video processing

back-end (VPBE) output with imaging coprocessor (VICP) used for display.

The video processing front-end (VPFE) consists of a CCD controller (CCDC), a preview engine

(previewer), histogram module, auto-exposure/white balance/focus module (H3A), and resizer. The CCDC

is capable of interfacing to common video decoders, CMOS sensors, and charge coupled devices (CCDs).

The previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or

CCD and converts from an RGB Bayer pattern to YUV4:2:2. The histogram and H3A modules provide

statistical information on the raw color data for use by the DM6441. The resizer accepts image data for

separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64

and 1024.

The video processing back-end (VPBE) consists of an on-screen display engine (OSD) and a video

encoder (VENC). The OSD engine is capable of handling two separate video windows and two separate

OSD windows. Other configurations include two video windows, one OSD window, and one attribute

window allowing up to eight levels of alpha blending. The VENC provides four analog DACs that run at 54

MHz, providing a means for composite NTSC/PAL video, S-Video, and/or component video output. The

VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is

capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs. VFocus

(part of the VPBE functionality and operationally (e.g., 16-bit multiplexed address/data) is also provided.

The Ethernet media access controller (EMAC) provides an efficient interface between the DM6441 and the

network. The DM6441 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and

100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS)

support.

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to

enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the

MDIO module transparently monitors its link state by reading the PHY status register. Link change events

are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link

status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6441 to easily control peripheral devices and/or

communicate with host processors. The DM6441 also provides Memory Stick/Memory Stick Pro card

support, MMC/SD with SDIO support, and a universal serial bus (USB).

The DM6441 also includes a video/imaging coprocessor (VICP) to offload many video and imaging

processing tasks from the DSP core, making more DSP MIPS available for common video and imaging

algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please

contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with

external processors. For details on each of the peripherals, see the related sections later in this document

and the associated peripheral reference guides.

The DM6441 has a complete set of development tools for both the ARM and DSP. These include C

compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™

debugger interface for visibility into source code execution.

Digital Media System-on-Chip (DMSoC)4 Submit Documentation Feedback

www.ti.com

1.3 Functional Block Diagram

JTAG Interface

System Control

PLLs/Clock

Generator

Input

Clock(s)

Power/Sleep

Controller

Pin

Multiplexing

ARM Subsystem

ARM926EJ-S CPU

16 KB

I-Cache

16 KB RAM

8 KB

D-Cache

16 KB ROM

DSP Subsystem

C64x+t DSP CPU

32 KB

L1 Pgm

64 KB L2 RAM

80 KB

L1 Data

Video-Imaging

Coprocessor (VICP)

BT.656,
Y/C,
Raw (Bayer)

Video Processing Subsystem (VPSS)

CCD

Controller

Video

Interface

Front End

Resizer

Histogram/

3A

Preview

10b DAC

On-Screen

Display

(OSD)

Video

Encoder

(VENC)

10b DAC

10b DAC
10b DAC

Back End 8b BT.656,

Y/C,
24b RGB

NTSC/
PAL,
S-Video,
RGB,
YPbPr

Switched Central Resource (SCR)

Peripherals

EDMA

Audio
Serial

Port

I2C SPI

UART

Serial Interfaces

DDR2

Mem Ctlr

(16b/32b)

Async EMIF/

NAND/

SmartMedia

ATA/

Compact

Flash

MMC/

SD/

SDIO

Program/Data Storage

Watchdog

Timer

PWM

System

General­Purpose

Timer

USB 2.0

PHY

VLYNQ

EMAC

With

MDIO

Connectivity

MS/

MS PRO

HPI

Figure 1-1 shows the functional block diagram of the device.

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Figure 1-1. TMS320DM6441 Functional Block Diagram

Submit Documentation Feedback Digital Media System-on-Chip (DMSoC) 5

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Contents

1 Digital Media System-on-Chip (DMSoC) ............ 1 5.3 Power Supplies ...................................... 83

1.1 Features .............................................. 1 5.4 Reset ................................................ 94

1.2 Description ............................................ 3 5.5 Oscillators ........................................... 97

1.3 Functional Block Diagram ............................ 5 5.6 Clock PLLs .......................................... 99

2 Device Overview ......................................... 7 5.7 Interrupts ........................................... 104

2.1 Device Characteristics ................................ 7 5.8 General-Purpose Input/Output (GPIO) ............. 112

2.2 Device Compatibility .................................. 8

2.3 ARM Subsystem ...................................... 8

2.4 DSP Subsystem ..................................... 12

2.5 Memory Map Summary ............................. 16

2.6 Pin Assignments .................................... 20

2.7 Terminal Functions .................................. 24

2.8 Device Support ...................................... 53

3 Device Configurations ................................. 56

3.1 System Module Registers ........................... 56

3.2 Power Considerations ............................... 56

3.3 Bootmode ........................................... 58

3.4 Configurations at Reset ............................. 60

3.5 Configurations After Reset .......................... 64

3.6 Emulation Control ................................... 76

4 Device Operating Conditions ........................ 79

4.1 Absolute Maximum Ratings Over Operating Case
Temperature Range

(Unless Otherwise Noted) .......................... 79 5.24 Memory Stick/Memory Stick PRO ................. 214

4.2 Recommended Operating Conditions ............... 80 5.25 Video Processing Sub-System (VPSS) Overview . 217

4.3 Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) ............ 81

5 Peripheral and Electrical Specifications ........... 82

5.1 Parameter Information .............................. 82

5.2 Recommended Clock and Control Signal Transition

Behavior ............................................. 83

5.9 Enhanced Direct Memory Access (EDMA)

Controller ........................................... 115

5.10 External Memory Interface (EMIF) ................. 127

5.11 ATA/CF ............................................ 135

5.12 MMC/SD/SDIO ..................................... 149

5.13 Video Processing Subsystem (VPSS) Overview .. 151

5.14 USB 2.0 ............................................ 172

5.15 Universal Asynchronous Receiver/Transmitter

(UART) ............................................. 182

5.16 Serial Port Interface (SPI) .......................... 185

5.17 Inter-Integrated Circuit (I2C) ....................... 189

5.18 Audio Serial Port (ASP) ............................ 193

5.19 Ethernet Media Access Controller (EMAC) ........ 197

5.20 Management Data Input/Output (MDIO) ........... 204

5.21 Timer ............................................... 206

5.22 Pulse Width Modulator (PWM) ..................... 208

5.23 VLYNQ ............................................. 210

5.26 Host-Port Interface (HPI) ........................... 221

5.27 IEEE 1149.1 JTAG ................................ 223

6 Mechanical Packaging and Orderable

Information ............................................. 226

6.1 Thermal Data for ZWT ............................. 226

6.1.1 Packaging Information ............................. 226

6 Contents Submit Documentation Feedback

www.ti.com

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the TMS320DM6441 SoC. The table shows significant features of the

device, including the capacity of on-chip RAM, peripherals, internal peripheral bus frequency relative to the
C64x+ DSP, and the package type with pin count.

Table 2-1. Characteristics of the Processor

HARDWARE FEATURES DM6441

DDR2 Memory Controller DDR2 (16/32-bit bus width)
Asynchronous EMIF (EMIFA)

Flash Cards

EDMA

Peripherals
Not all peripherals pins

are available at the
same time (For more
detail, see the Device
Configuration section).

On-Chip Memory

CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x1000
JTAG BSDL_ID 0x0B70 002F

CPU Frequency MHz

Cycle Time ns

Timers separate 32-bit timers)

UART 3 (one with RTS and CTS flow control)
SPI 1 (supports 2 slave devices)
I2C 1 (master/slave)
Audio Serial Port [ASP] 1
10/100 Ethernet MAC with Management Data Input/Output 1
VLYNQ 1
HPI 1 (16-bit multiplexed address/data)
General-Purpose Input/Output Port Up to 71
PWM 3 outputs
ATA/CF 1 (ATA/ATAPI-5)

Configurable Video Ports
USB 2.0 High speed client

Size (Bytes) 160KB RAM, 8KB ROM

Organization

JTAGID register
(address location: 0x01C4 0028)

Asynchronous (8/16-bit bus width) RAM, Flash

Compact Flash

MMC/SD with secure data input/output (SDIO)

SmartMedia/xD

Memory Stick/Memory Stick Pro

64 independent channels

8 QDMA channels

2 64-bit general purpose (each configurable as 2

64-bit watch dog

1 input (VPFE)

1 output (VPBE)

DSP

• 32KB L1 program (L1P)/cache (up to 32KB)

• 80KB L1 data (L1D)/cache (up to 32KB)

• 64KB unified mapped RAM/cache (L2)

ARM

• 16KB I-cache

• 8KB D-cache

• 16KB RAM

• 8KB ROM

DSP 405 MHz , ARM 202.5 MHz at 1.05 V

DSP 513 MHz, ARM 256 MHz at 1.2 V

DSP 2.47 ns, ARM 4.94 ns at 1.05 V

DSP 1.9 ns, ARM 3.9 ns at 1.2V

TMS320DM6441

(NOR, NAND)

Submit Documentation Feedback Device Overview 7

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-1. Characteristics of the Processor (continued)

HARDWARE FEATURES DM6441

Voltage

PLL Options x1 (bypass), x15 (1.05 V), x19 (1.2 V)
BGA Package 16 x 16 mm 361-pin BGA (ZWT)

Process Technology µm 0.09 µm

Product Status

(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(1)

2.2 Device Compatibility

The ARM926EJ-S RISC CPU is compatible with other ARM9 CPUs from ARM Holdings plc.
The C64x+ DSP core is code-compatible with the C6000™ DSP platform and supports features of the

C64x DSP family.

2.3 ARM Subsystem

Core (V) 1.05 V, 1.2 V
I/O (V) 1.8 V, 3.3 V, 1.2 V
CLKIN frequency multiplier

(27 MHz reference)

Product Preview (PP),
Advance Information (AI), PD
Production Data (PD)

The ARM subsystem is designed to give the ARM926EJ-S (ARM9) master control of the device. In
general, the ARM is responsible for configuration and control of the device; including the DSP subsystem,
the VPSS subsystem, and a majority of the peripherals and external memories.

The ARM subsystem includes the following features:

• ARM926EJ-S RISC processor

• ARMv5TEJ (32/16-bit) instruction set

• Little endian

• Coprocessor 15 (CP15)

• MMU

• 16KB instruction cache

• 8KB data cache

• Write buffer

• 16KB internal RAM (32-bit wide access)

• 8KB internal ROM (ARM bootloader for non-EMIFA boot options)

• Embedded trace module and embedded trace buffer (ETM/ETB)

• ARM interrupt controller

• PLL controller

• Power and sleep controller (PSC)

• System module

2.3.1 ARM926EJ-S RISC CPU

The ARM subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.

Device Overview8 Submit Documentation Feedback

www.ti.com

2.3.2 CP15

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory management unit (MMU)

• Separate instruction and data caches

• Write buffer

• Separate instruction and data tightly-coupled memories (TCMs) [internal RAM] interfaces

• Separate instruction and data AHB bus interfaces

• Embedded trace module and embedded trace buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, tightly-coupled memories (TCMs), memory management unit (MMU), and other ARM
subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,
when the ARM in a privileged mode such as supervisor or system mode.

2.3.3 MMU

The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux™,
WindowCE®, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is used
to control the address translation, permission checks and memory region attributes for both data and
instruction accesses. The MMU uses a single unified translation lookaside buffer (TLB) to cache the
information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are:

– 1MB (sections)
– 64KB (large pages)
– 4KB (small pages)
– 1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

2.3.4 Caches and Write Buffer

The size of the instruction cache is 16KB, data cache is 8KB. Additionally, the caches have the following
features:

• Virtual index, virtual tag, and addressed using the modified virtual address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with

two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables.

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,

Submit Documentation Feedback Device Overview 9

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

providing a mechanism for both lockdown, and controlling cache corruption

• Dcache stores the physical address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the virtual address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.

• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.

The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.

2.3.5 Tightly Coupled Memory (TCM)

ARM internal RAM is provided for storing real-time and performance-critical code/data and the interrupt
vector table. ARM internal ROM enables non-EMIFA boot options, such as NAND and UART. The RAM
and ROM memories interfaced to the ARM926EJ-S via the tightly coupled memory interface that provides
for separate instruction and data bus connections. Since the ARM TCM does not allow instructions on the
D-TCM bus or data on the I-TCM bus, an arbiter is included so that both data and instructions can be
stored in the internal RAM/ROM. The arbiter also allows accesses to the RAM/ROM from extra-ARM
sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA support for direct accesses to
the ARM internal memory from a non-ARM master. Because of the time-critical nature of the TCM link to
the ARM internal memory, all accesses from non-ARM devices are treated as DMA transfers.

Instruction and data accesses are differentiated via accessing different memory map regions, with the
instruction region from 0x0000 through 0x7FFF and data from 0x8000 through 0xFFFF. The instruction
region at 0x0000 and data region at 0x8000 map to the same physical 16K-byte TCM RAM. Placing the
instruction region at 0x0000 is necessary to allow the ARM interrupt vector table to be placed at 0x0000,
as required by the ARM architecture. The internal 16K-byte RAM is split into two physical banks of 8KB
each, which allows simultaneous instruction and data accesses to be accomplished if the code and data
are in separate banks.

2.3.6 Advanced High-performance Bus (AHB)

The ARM subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the config bus and
the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB by the
config bus and the external memories bus.

2.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)

To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
embedded trace macrocell (ETM). The ARM926ES-J subsystem in the DM6441 also includes the
embedded trace buffer (ETB). The ETM consists of two parts:

• Trace port provides real-time trace capability for the ARM9.

• Triggering facilities provide trigger resources, which include address and data comparators, counter,

and sequencers.

The DM6441 trace port is not pinned out and is instead only connected to the embedded trace buffer. The
ETB has a 4K-byte buffer memory. ETB enabled debug tools are required to read/interpret the captured
trace data.

2.3.8 ARM Memory Mapping

The ARM memory map is shown in Section 2.5 , Memory Map Summary, of this document. The ARM has
access to memories shown in the following sections.

Device Overview10 Submit Documentation Feedback

www.ti.com

2.3.8.1 ARM Internal Memories

The ARM has access to the following ARM internal memories:

• 16KB ARM internal RAM on TCM interface, logically separated into two 8-KB pages to allow
simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data
(D-TCM) to the different memory regions.

• 8KB ARM internal ROM

2.3.8.2 External Memories

The ARM has access to the following external memories:

• DDR2 synchronous DRAM

• Asynchronous EMIF / NOR flash / NAND flash

• ATA/CF

• Flash card devices:

– MMC/SD with SDIO
– Memory Stick/Memory Stick PRO
– xD
– SmartMedia

2.3.8.3 DSP Memories

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

The ARM has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

2.3.8.4 VICP Registers and Memories

The ARM has access to the registers and memories of the video/imaging coprocessor (VICP) subsystem.

2.3.8.5 ARM-DSP Integration

DM6441 ARM and DSP integration features are as follows:

• DSP visibility from ARM’s memory map, see Section 2.5 , Memory Map Summary, for details

• Boot modes for DSP - see Device Configurations section, Section 3.3.3 , DSP Boot, for details

• ARM control of DSP boot / reset - see Device Configurations section, Section 3.3.2 , ARM Boot, for

details

• ARM control of DSP isolation and powerdown / powerup - see Section 3 , Device Configurations, for
details

• ARM & DSP Interrupts - see Section 5.7.1 , ARM CPU Interrupts, and Section 5.7.2 , DSP Interrupts, for
details

2.3.9 Peripherals

The ARM9 has access to all of the peripherals on the DM6441 device with the exception of the VICP.

2.3.10 PLL Controller (PLLC)

The ARM subsystem includes the PLL controller. The PLL controller contains a set of registers for
configuring DM6441’s two internal PLLs (PLL1 and PLL2). The PLL controller provides the following
configuration and control:

• PLL bypass mode

• Set PLL multiplier parameters

• Set PLL divider parameters

• PLL power down

• Oscillator power down

Submit Documentation Feedback Device Overview 11

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

The PLLs are briefly described in this document in Section 5.6 , Clock PLLs. For more detailed information
on the PLLs and PLL Controller register descriptions, see Section 2.8.3 , Documentation Support, of this
document for the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14 ).

2.3.11 Power and Sleep Controller (PSC)

The ARM subsystem includes the power and sleep controller (PSC). Through register settings accessible
by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating and power
domain shut-off. Brief details on the PSC are given in Section 5.3 , Power Supplies. For more detailed
information and complete register descriptions for the PSC, see Section 2.8.3 , Documentation Support, for
the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14 ).

2.3.12 ARM Interrupt Controller (AINTC)

The ARM interrupt controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ
(interrupt request) or FIQ (fast interrupt request). The ARM interrupt controller is briefly described in this
document in the Interrupts section. For detailed information on the ARM interrupt controller, see

Section 2.8.3 , Documentation Support, for the ARM subsystem guide.

2.3.13 System Module

The ARM subsystem includes the system module. The system module consists of a set of registers for
configuring and controlling a variety of system functions. For details and register descriptions for the
system module, see Section 3 , Device Configurations, and see Section 2.8.3 , Documentation Support, for
the TMS320DM644x ARM Subsystem Reference Guide (literature number SPRUE14 ).

2.3.14 Power Management

DM6441 has several means of managing power consumption. There is extensive use of clock gating,
which reduces the power used by global device clocks and individual peripheral clocks. Clock
management can be utilized to reduce clock frequencies in order to reduce switching power. For more
details on power management techniques, see Section 3 , Device Configurations, Section 5 , Peripheral

and Electrical Specifications, and see Section 2.8.3 , Documentation Support, for the TMS320DM644x
ARM Subsystem Reference Guide (literature number SPRUE14 ).

2.4 DSP Subsystem

The DSP subsystem includes the following features:

• C64x+ DSP CPU

• 32KB L1 program (L1P)/cache (up to 32KB)

• 80KB L1 data (L1D)/cache (up to 32KB)

• 64KB unified mapped RAM/cache (L2)

• Little endian

2.4.1 C64x+ DSP CPU Description

The C64x+ central processing unit (CPU) consists of eight functional units, two register files, and two data
paths as shown in Figure 2-1 . The two general-purpose register files (A and B) each contain 32 32-bit
registers for a total of 64 registers. The general-purpose registers can be used for data or can be data
address pointers. The data types supported include packed 8-bit data, packed 16-bit data, 32-bit data,
40-bit data, and 64-bit data. Values larger than 32 bits, such as 40-bit-long or 64-bit-long values are stored
in register pairs, with the 32 LSBs of data placed in an even register and the remaining eight or 32 MSBs
in the next upper register (which is always an odd-numbered register).

The eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, and .S2) are each capable of executing one
instruction every clock cycle. The .M functional units perform all multiply operations. The .S and .L units
perform a general set of arithmetic, logical, and branch functions. The .D units primarily load data from
memory to the register file and store results from the register file into memory.

Device Overview12 Submit Documentation Feedback

www.ti.com

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

The C64x+ CPU extends the performance of the C64x core through enhancements and new features.
Each C64x+ .M unit can perform one of the following each clock cycle: one 32 x 32 bit multiply, one 16 x

32 bit multiply, two 16 x 16 bit multiplies, two 16 x 32 bit multiplies, two 16 x 16 bit multiplies with
add/subtract capabilities, four 8 x 8 bit multiplies, four 8 x 8 bit multiplies with add operations, and four
16 x 16 multiplies with add/subtract capabilities (including a complex multiply). There is also support for
Galois field multiplication for 8-bit and 32-bit data. Many communications algorithms such as FFTs and
modems require complex multiplication. The complex multiply (CMPY) instruction takes four 16-bit inputs
and produces a 32-bit real and a 32-bit imaginary output. There are also complex multiplies with rounding
capability that produces one 32-bit packed output that contain 16-bit real and 16-bit imaginary values. The
32 x 32 bit multiply instructions provide the extended precision necessary for audio and other
high-precision algorithms on a variety of signed and unsigned 32-bit data types.

The .L or (Arithmetic Logic Unit) now incorporates the ability to do parallel add/subtract operations on a
pair of common inputs. Versions of this instruction exist to work on 32-bit data or on pairs of 16-bit data
performing dual 16-bit add and subtracts in parallel. There are also saturated forms of these instructions.

The C64x+ core enhances the .S unit in several ways. In the C64x core, dual 16-bit MIN2 and MAX2
comparisons were only available on the .L units. On the C64x+ core they are also available on the .S unit
which increases the performance of algorithms that do searching and sorting. Finally, to increase data
packing and unpacking throughput, the .S unit allows sustained high performance for the quad 8-bit/16-bit
and dual 16-bit instructions. Unpack instructions prepare 8-bit data for parallel 16-bit operations. Pack
instructions return parallel results to output precision including saturation support.

Other new features include:

• SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where
multiple iterations of a loop are executed in parallel. The SPLOOP buffer reduces the code size
associated with software pipelining. Furthermore, loops in the SPLOOP buffer are fully interruptible.

• Compact instructions - The native instruction size for the C6000 devices is 32 bits. Many common
instructions such as MPY, AND, OR, ADD, and SUB can be expressed as 16 bits if the C64x+
compiler can restrict the code to use certain registers in the register file. This compression is
performed by the code generation tools.

• Instruction set enhancement - As noted above, there are new instructions such as 32-bit
multiplications, complex multiplications, packing, sorting, bit manipulation, and 32-bit Galois field
multiplication.

• Exceptions handling - Intended to aid the programmer in isolating bugs. The C64x+ CPU is able to
detect and respond to exceptions, both from internally detected sources (such as illegal op-codes) and
from system events (such as a watchdog time expiration).

• Privilege - Defines user and supervisor modes of operation, allowing the operating system to give a
basic level of protection to sensitive resources. Local memory is divided into multiple pages, each with
read, write, and execute permissions.

• Time-stamp counter - Primarily targeted for real-time operating system (RTOS) robustness, a
free-running time-stamp counter is implemented in the CPU which is not sensitive to system stalls.

For more details on the C64x+ CPU and its enhancements over the C64x architecture, see the following
documents:

• TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732 )

• TMS320C64x Technical Overview (literature number SPRU395 )

Submit Documentation Feedback Device Overview 13

www.ti.com

src2

src2

.D1

.M1

.S1

.L1

long src

odd dst

src2

src1

src1

src1

src1

even dst

even dst

odd dst

dst1

dst

src2

src2

src2

long src

DA1

ST1b

LD1b
LD1a

ST1a

Data path A

Odd

register

file A

(A1, A3,

A5...A31)

Odd

register

file B

(B1, B3,

B5...B31)

.D2

src1

dst

src2

DA2

LD2a
LD2b

src2

.M2

src1

dst1

.S2

src1

even dst

long src

odd dst

ST2a
ST2b

long src

.L2

even dst

odd dst

src1

Data path B

Control Register

32 MSB
32 LSB

dst2

(A)

32 MSB
32 LSB

2x

1x

32 LSB

32 MSB

32 LSB

32 MSB

dst2

(B)

(B)
(A)

8

8

8

8

32

32

32

32

(C)

(C)

Even

register

file A

(A0, A2,

A4...A30)

Even

register

file B

(B0, B2,

B4...B30)

(D)

(D)

(D)

(D)

A. On .M unit, dst2 is 32 MSB.
B. On .M unit, dst1 is 32 LSB.
C. On C64x CPU .M unit, src2 is 32 bits; on C64x+ CPU .M unit, src2 is 64 bits.
D. On .L and .S units, odd dst connects to odd register files and even dst connects to even register files.

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Figure 2-1. TMS320C64x+™ CPU (DSP Core) Data Paths

14 Device Overview Submit Documentation Feedback

www.ti.com

2.4.2 DSP Memory Mapping

The DSP memory map is shown in Table 2-3 . Configuration of the control registers for DDR2, EMIFA, and
ARM internal RAM is supported by the ARM. The DSP has access to memories shown in the following
sections.

2.4.2.1 ARM Internal Memories

The DSP has access to the 16KB ARM internal RAM on the ARM D-TCM interface (i.e., data only).

2.4.2.2 External Memories

The DSP has access to the following external memories:

• DDR2 synchronous DRAM

• Asynchronous EMIF / NOR Flash

2.4.2.3 DSP Internal Memories

The DSP has access to the following DSP memories:

• L2 RAM

• L1P RAM

• L1D RAM

2.4.2.4 C64x+ CPU

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

The C64x+ core uses a two-level cache-based architecture. The Level 1 program cache (L1D) is 32 KB
direct mapped cache and the Level 1 data cache (L1D) is 80 KB 2-way set associated cache. The Level 2
memory/cache (L2) consists of a 64 KB memory space that is shared between program and data space.
L2 memory can be configured as mapped memory, cache, or a combination of both.

Table 2-2 shows a memory map of the C64x+ CPU cache registers for the device.

Table 2-2. C64x+ Cache Registers

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 0000 L2CFG L2 cache configuration register
0x0184 0020 L1PCFG L1P size cache configuration register
0x0184 0024 L1PCC L1P freeze mode cache configuration register
0x0184 0040 L1DCFG L1D size cache configuration register
0x0184 0044 L1DCC L1D freeze mode cache configuration register

0x0184 0048 - 0x0184 0FFC - Reserved

0x0184 1000 EDMAWEIGHT L2 EDMA access control register

0x0184 1004 - 0x0184 1FFC - Reserved

0x0184 2000 L2ALLOC0 L2 allocation register 0
0x0184 2004 L2ALLOC1 L2 allocation register 1
0x0184 2008 L2ALLOC2 L2 allocation register 2

0x0184 200C L2ALLOC3 L2 allocation register 3

0x0184 2010 - 0x0184 3FFF - Reserved

0x0184 4000 L2WBAR L2 writeback base address register
0x0184 4004 L2WWC L2 writeback word count register
0x0184 4010 L2WIBAR L2 writeback invalidate base address register
0x0184 4014 L2WIWC L2 writeback invalidate word count register
0x0184 4018 L2IBAR L2 invalidate base address register

0x0184 401C L2IWC L2 invalidate word count register

0x0184 4020 L1PIBAR L1P invalidate base address register
0x0184 4024 L1PIWC L1P invalidate word count register
0x0184 4030 L1DWIBAR L1D writeback invalidate base address register

Submit Documentation Feedback Device Overview 15

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-2. C64x+ Cache Registers (continued)

HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION

0x0184 4034 L1DWIWC L1D writeback invalidate word count register
0x0184 4038 - Reserved
0x0184 4040 L1DWBAR L1D block writeback
0x0184 4044 L1DWWC L1D block writeback
0x0184 4048 L1DIBAR L1D invalidate base address register

0x0184 404C L1DIWC L1D invalidate word count register

0x0184 4050 - 0x0184 4FFF - Reserved

0x0184 5000 L2WB L2 writeback all register
0x0184 5004 L2WBINV L2 writeback invalidate all register
0x0184 5008 L2INV L2 global invalidate without writeback

0x0184 500C - 0x0184 5027 - Reserved

0x0184 5028 L1PINV L1P global invalidate

0x0184 502C - 0x0184 5039 - Reserved

0x0184 5040 L1DWB L1D global writeback
0x0184 5044 L1DWBINV L1D global writeback with invalidate

0x0184 5048 L1DINV L1D global invalidate without writeback
0x0184 8000 - 0x0184 8004 MAR0 - MAR1 Reserved 0x0000 0000 - 0x01FF FFFF
0x0184 8008 - 0x0184 8024 MAR2 - MAR9 Memory attribute registers for EMIFA 0x0200 0000 - 0x09FF FFFF
0x0184 8028 - 0x0184 802C MAR10 - MAR11 Reserved 0x0A00 0000 - 0x0BFF FFFF
0x0184 8030 - 0x0184 803C MAR12 - MAR15 Memory attribute registers for VLYNQ 0x0C00 0000 - 0x0FFF FFFF
0x0184 8040 - 0x0184 8104 MAR16 - MAR65 Reserved 0x1000 0000 - 0x41FF FFFF

0x0184 8108 - 0x0184 813C MAR66 - MAR79

0x0184 8140- 0x0184 81FC MAR80 - MAR127 Reserved 0x5000 0000 - 0x7FFF FFFF
0x0184 8200 - 0x0184 823C MAR128 - MAR143 Memory attribute registers for DDR2 0x8000 0000 - 0x8FFF FFFF
0x0184 8240 - 0x0184 83FC MAR144 - MAR255 Reserved 0x9000 0000 - 0xFFFF FFFF

Memory attribute registers for EMIFA/VLYNQ shadow 0x4200 0000 ­0x4FFF FFFF

2.4.3 Peripherals

The DSP has controllability for the following peripherals:

• VICP

• EDMA

• ASP

• Two Timers (Timer 0 and Timer1) that can each be configured as one 64-bit or two 32-bit timers

2.4.4 DSP Interrupt Controller

The DSP interrupt controller accepts device interrupts and appropriately maps them to available DSP
interrupts. The DSP interrupt controller is briefly described in this document in the Interrupts section. For
more detailed on the DSP interrupt controller, see Section 2.8.3 , Documentation Support, of this document
for the C64x+ CPU user's guide.

2.5 Memory Map Summary

Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of

the configuration space (0x0180 0000 through 0x0FFF FFFF). The device has multiple on-chip memories
associated with its two processors and various subsystems. To help simplify software development a
unified memory map is used where possible to maintain a consistent view of device resources across all
bus masters.

Device Overview16 Submit Documentation Feedback

www.ti.com

Table 2-3. Memory Map Summary

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

START END SIZE EDMA/

ADDRESS ADDRESS (Bytes) PERIPHERAL

0x0000 0000 0x0000 1FFF 8K ARM RAM0 (Instruction)
0x0000 2000 0x0000 3FFF 8K ARM RAM1 (Instruction)
0x0000 4000 0x0000 5FFF 8K ARM ROM (Instruction)
0x0000 6000 0x0000 7FFF 8K Reserved
0x0000 8000 0x0000 9FFF 8K ARM RAM0 (Data) Reserved ARM RAM0 ARM RAM0
0x0000 A000 0x0000 BFFF 8K ARM RAM1 (Data) ARM RAM1 ARM RAM1
0x0000 C000 0x0000 DFFF 8K ARM ROM (Data) ARM ROM ARM ROM
0x0000 E000 0x0000 FFFF 8K
0x0001 0000 0x000F FFFF 960K
0x0010 0000 0x001F FFFF 1M VICP
0x0020 0000 0x007F FFFF 6M Reserved
0x0080 0000 0x0080 FFFF 64K L2 RAM/Cache
0x0081 0000 0x00E0 7FFF 6112K Reserved
0x00E0 8000 0x00E0 FFFF 32K L1P Cache
0x00E1 0000 0x00F0 3FFF 976K Reserved
0x00F0 4000 0x00F0 FFFF 48K L1D RAM
0x00F1 0000 0x00F1 7FFF 32K L1D Cache
0x00F1 8000 0x017F FFFF 9120K Reserved
0x0180 0000 0x01BB FFFF 3840K
0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory
0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers CFG Space
0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher
0x01BC 1900 0x01BF FFFF 255744 Reserved
0x01C0 0000 0x01FF FFFF 4M CFG Bus Peripherals CFG Bus Peripherals CFG Bus Peripherals
0x0200 0000 0x09FF FFFF 128M EMIFA (Code and Data) EMIFA (Data) EMIFA (Data) Reserved
0x0A00 0000 0x0BFF FFFF 32M Reserved Reserved
0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote) Reserved VLYNQ (Remote)
0x1000 0000 0x1000 7FFF 32K Reserved
0x1000 8000 0x1000 9FFF 8K ARM RAM0 ARM RAM0
0x1000 A000 0x1000 BFFF 8K ARM RAM1 ARM RAM1
0x1000 C000 0x1000 DFFF 8K ARM ROM ARM ROM
0x1000 E000 0x1000 FFFF 8K
0x1001 0000 0x110F FFFF 17344K
0x1110 0000 0x111F FFFF 1M VICP VICP VICP
0x1120 0000 0x117F FFFF 6M Reserved Reserved Reserved
0x1180 0000 0x1180 FFFF 64K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache
0x1181 0000 0x11E0 7FFF 6112K Reserved Reserved Reserved
0x11E0 8000 0x11E0 FFFF 32K L1P Cache L1P Cache L1P Cache
0x11E1 0000 0x11F0 3FFF 976K Reserved Reserved Reserved
0x11F0 4000 0x11F0 FFFF 48K L1D RAM L1D RAM L1D RAM
0x11F1 0000 0x11F1 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache
0x11F1 8000 0x1FFF FFFF 241M-32K Reserved Reserved Reserved
0x2000 0000 0x2000 7FFF 32K DDR2 Control Regs DDR2 Control Regs DDR2 Control Regs DDR2 Control Regs
0x2000 8000 0x41FF FFFF 544M-32k Reserved Reserved Reserved Reserved
0x4200 0000
0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved
0x8000 0000 0x8FFF FFFF 256M DDR2 DDR2 DDR2 DDR2
0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved

(1)

0x4FFF FFFF 224M Reserved EMIFA/VLYNQ Shadow EMIFA/VLYNQ Shadow

Reserved

Reserved

ARM C64x+ HPI VPSS

Reserved Reserved

Reserved

Reserved Reserved

(1) EMIFA shadow memory started a 0x4200 0000 is physically the same memory as location 0x0200 0000. Memory range 0x200 0000

through 0x09FF FFFF should only be used by C64x+ for data accesses. Memory range 0x4200 0000 through 0x4FFF FFFF can be
used by C64x+ for both code execution and data accesses.

Reserved

Submit Documentation Feedback Device Overview 17

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-4. Configuration Memory Map Summary

START END SIZE ARM/EDMA C64x+
ADDRESS ADDRESS (Bytes)

0x0180 0000 0x0180 FFFF 64K C64x+ interrupt controller
0x0181 0000 0x0181 0FFF 4K C64x+ powerdown controller
0x0181 1000 0x0181 1FFF 4K C64x+ security ID
0x0181 2000 0x0181 2FFF 4K C64x+ revision ID
0x0182 0000 0x0182 FFFF 64K Reserved C64x+ EMC
0x0183 0000 0x0183 FFFF 64K Reserved
0x0184 0000 0x0184 FFFF 64K C64x+ memory system
0x0185 0000 0x0187 FFFF 192K Reserved
0x0188 0000 0x01BB FFFF 3328K Reserved
0x01BC 0000 0x01BC 00FF 256 AET registers
0x01BC 0100 0x01BC 01FF 256 ARM ETB Memory Pin manager and trace
0x01BC 0200 0x01BC 0FFF 3.5K
0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers
0x01BC 1800 0x01BC 18FF 256 ARM Ice Crusher
0x01BC 1900 0x01BF FFFF 255744 Reserved
0x01C0 0000 0x01C0 FFFF 64K EDMA CC EDMA CC
0x01C1 0000 0x01C1 03FF 1K EDMA TC0 EDMA TC0
0x01C1 0400 0x01C1 07FF 1K EDMA TC1 EDMA TC1
0x01C1 8800 0x01C1 9FFF 6K
0x01C1 A000 0x01C1 FFFF 24K
0x01C2 0000 0x01C2 03FF 1K UART0
0x01C2 0400 0x01C2 07FF 1K UART1 Reserved
0x01C2 0800 0x01C2 0BFF 1K UART2
0x01C2 0C00 0x01C2 0FFF 1K Reserved
0x01C2 1000 0x01C2 13FF 1K I2C
0x01C2 1400 0x01C2 17FF 1K Timer0 Timer0
0x01C2 1800 0x01C2 1BFF 1K Timer1 Timer1
0x01C2 1C00 0x01C2 1FFF 1K Timer2 (WatchDog)
0x01C2 2000 0x01C2 23FF 1K PWM0
0x01C2 2400 0x01C2 27FF 1K PWM1 Reserved
0x01C2 2800 0x01C2 2BFF 1K PWM2
0x01C2 2C00 0x01C3 FFFF 117K Reserved
0x01C4 0000 0x01C4 07FF 2K System Module System module
0x01C4 0800 0x01C4 0BFF 1K PLL Controller 1
0x01C4 0C00 0x01C4 0FFF 1K PLL Controller 2
0x01C4 1000 0x01C4 1FFF 4K Power and Sleep Controller Power and sleep controller
0x01C4 2000 0x01C4 202F 48 Reserved Reserved
0x01C4 2030 0x01C4 2033 4 DDR2 VTP Reg DDR2 VTP reg

Reserved

Reserved

Reserved

Device Overview18 Submit Documentation Feedback

www.ti.com

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-4. Configuration Memory Map Summary (continued)

START END SIZE ARM/EDMA C64x+
ADDRESS ADDRESS (Bytes)

0x01C4 2034 0x01C4 23FF 1K - 52
0x01C4 2400 0x01C4 7FFF 23K
0x01C4 8000 0x01C4 83FF 1K ARM interrupt controller
0x01C4 8400 0x01C5 FFFF 95K
0x01C6 0000 0x01C6 3FFF 16K Reserved
0x01C6 4000 0x01C6 5FFF 8K USB2.0 Regs / RAM
0x01C6 6000 0x01C6 67FF 2K ATA/CF
0x01C6 6800 0x01C6 6FFF 2K SPI
0x01C6 7000 0x01C6 77FF 2K GPIO
0x01C6 7800 0x01C6 7FFF 2K HPI HPI
0x01C6 8000 0x01C6 FFFF 32K Reserved
0x01C7 0000 0x01C7 3FFF 16K VPSS Regs
0x01C7 4000 0x01C7 FFFF 48K Reserved
0x01C8 0000 0x01C8 0FFF 4K EMAC Control Regs
0x01C8 1000 0x01C8 1FFF 4K EMAC Control Module Regs Reserved
0x01C8 2000 0x01C8 3FFF 8K EMAC Control Module RAM
0x01C8 4000 0x01C8 47FF 2K MDIO Control Regs
0x01C8 4800 0x01C8 4FFF 2K
0x01C8 5000 0x01CB FFFF 236K
0x01CC 0000 0x01CD FFFF 128K VICP VICP
0x01CE 0000 0x01CF FFFF 128K
0x01D0 0000 0x01DF FFFF 1M
0x01E0 0000 0x01E0 0FFF 4K EMIFA Control
0x01E0 1000 0x01E0 1FFF 4K VLYNQ Control Regs
0x01E0 2000 0x01E0 3FFF 8K ASP ASP
0x01E0 4000 0x01E0 FFFF 48K Reserved
0x01E1 0000 0x01E1 FFFF 64K MMC/SD/SDIO
0x01E2 0000 0x01E3 FFFF 128K Memory Stick/Memory Stick Pro
0x01E4 0000 0x01FF FFFF 1792K Reserved
0x0200 0000 0x03FF FFFF 32M EMIFA Data/Code (CS2) EMIFA data (CS2)
0x0400 0000 0x05FF FFFF 32M EMIFA Data/Code (CS3) EMIFA data (CS3)
0x0600 0000 0x07FF FFFF 32M EMIFA Data/Code (CS4) EMIFA data (CS4)
0x0800 0000 0x09FF FFFF 32M EMIFA Data/Code (CS5) EMIFA data (CS5)
0x0A00 0000 0x0BFF FFFF 32M Reserved
0x0C00 0000 0x0FFF FFFF 64M VLYNQ (Remote)

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

TMS320DM6441

Digital Media System-on-Chip

Submit Documentation Feedback Device Overview 19

www.ti.com

W

V

U

T

R

P

N

M

L

K

10987654321

10987654321

DDR_D[1]

DV

DDR2

EM_A[4]/

GPIO27

CLK_OUT0/

GPIO48

MXI/CLKIN

EM_A[5]/

GPIO26

MXV

SS

PLLV

DD18

RSV24

EM_A[6]/

GPIO25

EM_A[8]/

GPIO23

EM_A[7]/

GPIO24

EM_A[13]/

GPIO18

EM_A[10]/

GPIO21

EM_A[15]/

GPIO16/

VLYNQ_TXD3

EM_A[11]/

GPIO20

EM_A[17]/

GPIO14/

VLYNQ_TXD2

EM_A[19]/

GPIO12/

VLYNQ_TXD1

EM_A[20]/

GPIO11/

VLYNQ_RXD0

EM_CS4/

GPIO9/

VLYNQ_

SCRUN

DDR_

DQM[0]

DDR_D[0]

EM_A[21]/

GPIO10/

VLYNQ_TXD0

EM_A[14]/

GPIO17/

VLYNQ_RXD3

EM_A[9]/

GPIO22

MXV

DD

RESET

V

SS

RSV3

V

SS

CV

DD

DV

DDR2

DV

DDR2

V

SS

V

SS

DDR_A[11]DDR_A[12]DDR_CLK0DDR_CLK0DDR_D[14]

DV

DDR2

V

SS

V

SS

DDR_D[5]

DDR_D[6]

DDR_D[9]

DV

DD18

EM_A[16]/

GPIO15/

VLYNQ_RXD2

DV

DDR2

DDR_BS[2]

CV

DD

DDR_D[11] DDR_D[15] DDR_CKE DDR_A[8]

V

SS

DV

DDR2

V

SS

V

SS

DV

DDR2

DDR_

DQM[1]

DDR_CAS DDR_WE DDR_VDDDLL

CV

DDDSP

CV

DD

DDR_DQS[1] DDR_RAS DDR_A[10]

CV

DD

CV

DD

DDR_D[2] DDR_D[3] DDR_D[8] DDR_D[13] DDR_BS[1]

DDR_D[4] DDR_D[12]

V

SS

EM_A[3]/

GPIO28

DV

DD18

CV

DD

DV

DD18

RSV7

MXO V

SS

DV

DD18

V

SS

EM_A[18]/

GPIO13/

VLYNQ_RXD1

V

SS

EM_A[12]/

GPIO19

V

SS

DDR_CS

CV

DDDSP

DDR_DQS[0] DDR_D[10] DDR_BS[0]

EM_CS5/

GPIO8/

VLYNQ_

CLOCK

RSV6

DDR_D[7]

W

V

U

T

R

P

N

M

L

K

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

2.6 Pin Assignments

Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings. For more information on pin
muxing, see Section 3.5.2 , Multiplexed Pin Configurations, of this document.

2.6.1 Pin Map (Bottom View)

Figure 2-2 through Figure 2-5 show the bottom view of the package pin assignments in four quadrants (A,

B, C, and D).

Device Overview20 Submit Documentation Feedback

Figure 2-2. Pin Map [Quadrant A]

www.ti.com

W

V

U

T

R

P

N

M

L

K

191817161514131211

191817161514131211

DDR_A[9]

V

SS

V

SS

CV

DD

CV

DD

V

SS

CV

DD

V

SS

DV

DDR2

DV

DDR2

DV

DDR2

V

SS

DV

DDR2

DV

DDR2

V

SS

DDR_

VSSDLL

DDR_ZPDDR_ZN

V

SS

V

SS

V

SS

DV

DD18

DV

DD18

HD PCLK

V

DDA_1P8V

CI6/CCD14/

UART_TXD2

CI7/CCD15/

UART_RXD2

DAC_IOUT_B

RSV4DDR_D[29]DDR_D[27]DDR_D[21]DDR_D[18]

DAC_IOUT_A

YI4/CCD4

DAC_RBIAS

DDR_A[3]

DDR_A[4]

DDR_A[0]

V

SS

V

SS

DDR_DQM[2]

DDR_D[26]

YI7/CCD7

DDR_D[17] DDR_D[22] DDR_D[24] DDR_D[30]

YI0/CCD0

V

SSA_1P8V

CI5/CCD13/

UART_CTS2

CI1/CCD9

CI4/CCD12/

UART_RTS2

DDR_VREF DDR_DQM[3] DDR_D[23] DAC_IOUT_D

YI1/CCD1 YI3/CCD3

DDR_D[20] DDR_DQS[3] DDR_D[31]

YI6/CCD6 VD

DDR_A[7] DDR_A[2] DDR_D[19] DDR_D[28]

DDR_A[6] DDR_D[16]

DAC_IOUT_C

CV

DDDSP

V

SS

CI2/CCD10

YI5/CCD5

DAC_V

REF

DV

DD18

CI0/CCD8

CI3/CCD11

DV

DDR2

V

DDA_1P1V

DV

DDR2

V

SSA_1P1V

YI2/CCD2

DDR_A[1] DDR_DQS[2] DDR_D[25]

V

SS

DDR_A[5]

W

V

U

T

R

P

N

M

L

K

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Figure 2-3. Pin Map [Quadrant B]

Submit Documentation Feedback Device Overview 21

www.ti.com

H

G

F

E

D

C

B

A

191817161514131211

191817161514131211

CV

DDDSP

YOUT4/R4/

AEAW4

GPIOV33_1/

TXCLK

GPIOV33_2/

COL

GPIOV33_9/

RXD2

GPIOV33_8/

RXD1

GPIOV33_6/

TXD3

GPIOV33_4/

TXD1

GPIOV33_12/

RXDV

GPIO2/G0

GPIOV33_7/

RXD0

GPIOV33_10/

RXD3

DV

DD33

DV

DD33

DV

DD33

V

SS

V

SS

V

SS

GPIO1/

C_WE

GPIO0/

LCD_OE

GPIO4/R0/

C_FIELD

GPIOV33_0/

TXEN

GPIO6/B1

VSYNC VPBECLK

M24XI

YOUT3/R3/

AEAW3

VCLK

YOUT7/R7

CLK_OUT1/

TIM_IN/
GPIO49

PWM1/R2/

GPIO46

M24V

DD

CV

DDDSP

GPIO38/R1

DV

DD18

V

SS

USB_R1

COUT5/G2

COUT0/B3/

BTSEL0

YOUT6/R6

YOUT2/G7/

AEAW2

COUT7/G4

YOUT1/G6/

AEAW1

DV

DD18

USB_

V

SSREF

USB_

V

SSA1P2LD0

USB_DP

COUT2/B5/

EM_WIDTH

RSV2

V

SS

USB_V

SS1P8

USB_DM

COUT3/B6/

DSP_BT

COUT6/G3

M24XO

GPIOV33_5/

TXD2

PWM2/

B2/GPIO47

HSYNC

COUT1/B4/

BTSEL1

M24V

SS

GPIO3/B0/

LCD_FIELD

PWM0/

GPIO45

YOUT0/G5/

AEAW0

GPIO5/G1 YOUT5/R5

CV

DD

USB_

V

DDA1P2LD0

COUT4/B7

V

SS

DV

DD18

USB_V

DD1P8

GPIOV33_3/

TXD0

H

G

F

E

D

C

B

A

J

CV

DDDSP

V

SS

USB_

V

SSA3P3

DV

DD18

USB_ID

USB_

V

DDA3P3

CV

DDDSP

V

SS

USB_VBUS

J

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Figure 2-4. Pin Map [Quadrant C]

Device Overview22 Submit Documentation Feedback

www.ti.com

J

H

G

F

E

D

C

B

A

10987654321

10987654321

EM_BA[1]/

DA1/

GPIO52

TMS

SPI_EN0/

GPIO37

RSV1

EM_CS3

SPI_CLK/

GPIO39

SPI_EN1/

HDDIR/
GPIO42

EM_CS2/

HCS

GPIO7

EM_D12/

DD12/

HD12

EM_D1/

DD1/

HD1

EM_D5/

DD5/

HD5

RSV5

EM_D15/

DD15/

HD15

EM_D3/

DD3/

HD3

EM_D9/

DD9/

HD9

EM_D13/

DD13/

HD13

EM_D6/

DD6/

HD6

EM_D8/

DD8/

HD8

EM_WE/(WE)/
(IOWR)/DIOW/

HDS2

EM_D11/

DD11/

HD11

GPIO51/

ATA_CS1

EM_R/W/

INTRQ/

HR/W

EM_D4/

DD4/

HD4

SCL/

GPIO43

TDOSDA/GPIO44

TDI

SD_DATA3

GPIOV33_14/

CRS

V

SS

SD_DATA2

GPIOV33_13/

RXER

SD_DATA1

GPIOV33_15/

MDIO

RTCK

V

SS

DMACK/

UART_TXD1

EM_BA[0]/

DA0/

HINT

UART_RXD0/

GPIO35

EM_D2/

DD2/

HD2

EM_D10/

DD10/

HD10

V

SS

SD_CMD

GPIO50/

ATA_CS0

DV

DD18

V

SS

CV

DDDSP

DR/

GPIO34

V

SS

SD_DATA0

FSR/

GPIO32

TRST

V

SS

DV

DD18

V

SS

V

SS

CLKR/

GPIO30

GPIOV33_11/

RXCLK

DV

DD18

V

SS

CV

DDDSP

CLKX/

GPIO29

GPIOV33_16/

MDCLK

EM_A[2]/

(CLE)/

HCNTL0

EM_A[1]/

(ALE)/

HHWIL

EM_A[0]/

DA2/

HCNTL1/

GPIO53

V

SS

CV

DDDSP

DV

DD33

SPI_DO/

GPIO41

TCK

FSX/

GPIO31

DX/

GPIO33

DV

DD18

EM_D7/

DD7/

HD7

UART_TXD0/

GPIO36

EMU1

EMU0

EM_D0/

DD0/

HD0

DV

DD18

EM_WAIT/

(RDY/BSY)/

IORDY/

HRDY

DV

DD18

DV

DD18

SD_CLK

EM_OE/(RE)/
(IORD)/DIOR/

HDS1

EM_D14/

DD14/

HD14

CV

DDDSP

DMARQ/

UART_RXD1

SPI_DI/
GPIO40

J

H

G

F

E

D

C

B

A

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Figure 2-5. Pin Map [Quadrant D]

Submit Documentation Feedback Device Overview 23

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

2.7 Terminal Functions

The terminal functions tables (Table 2-5 through Table 2-31 ) identify the external signal names, the
associated pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin
has any internal pullup or pulldown resistors, and a functional pin description. For more detailed
information on device configuration, peripheral selection, multiplexed/shared pin, and debugging
considerations, see Section 3 , Device Configurations, of this data manual.

Table 2-5. BOOT Terminal Functions

SIGNAL

NAME NO.

COUT0/

B3/ A16 I/O/Z

BTSEL0

COUT1/

B4/ B16 I/O/Z 0 1 ARM EMIFA boot (NOR)

BTSEL1

COUT2/

B5/ A17 I/O/Z

EM_WIDTH

COUT3/

B6/ B17 I/O/Z

DSP_BT

YOUT0/

G5/ D15 I/O/Z

AEAW0
YOUT1/

G6/ D16 I/O/Z

AEAW1
YOUT2/ input states of AEAW[4:0] are sampled to set the EMIFA address bus

G7/ D17 I/O/Z width. See Section 3.4.2 , Peripheral Selection at Device Reset, for details.

AEAW2 After reset, these are video encoder outputs YOUT[0:4] or RGB666/888
YOUT3/

R3/ D18 I/O/Z

AEAW3
YOUT4/

R4/ E15 I/O/Z

AEAW4

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal

(1)

TYPE

(2) (3)

OTHER

BOOT

These pins are multiplexed between ARM boot mode and the VPBE. At

IPD determine the ARM boot configuration. See below for the boot modes set

DV

DD18

IPD

DV

DD18

IPD 8-bit wide EMIFA data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data

DV

DD18

IPD booted by the ARM when DSP_BT=0. The DSP boots from EMIFA when

DV

DD18

IPD

DV

DD18

IPD

DV

DD18

IPD

DV

DD18

IPD

DV

DD18

IPD

DV

DD18

reset, the boot mode inputs BTSEL0 and BTSEL1 are sampled to
by these inputs. See Section 3.3 , Bootmode for more details.

After reset, these are video encoder outputs COUT0 and COUT1, or
RGB666/888 Blue output data bits 3 and 4 B3/B4.

BTSEL1 BTSEL0 ARM Boot Mode

0 0 ARM ROM boot (NAND) [default]

1 0 ARM ROM boot (HPI)
1 1 ARM ROM boot (UART0)

This pin is multiplexed between EMIFA and the VPBE. At reset, the input
state is sampled to set the EMIFA data bus width (EM_WIDTH). For an

bus, EM_WIDTH = 1.
After reset, it is video encoder output COUT2 or RGB666/888 Blue output
data bit 5 B5.

This pin is multiplexed between DSP boot and the VPBE. At reset, the
input state is sampled to set the DSP boot source DSP_BT. The DSP is

DSP_BT=1.
After reset, it is video encoder output COUT3 or RGB666/888 Blue data
bit 6 output B6.

These pins are multiplexed between EMIFA and the VPBE. At reset, the

Red and Green data bit outputs G5, G6, G7, R3, and R4.

DESCRIPTION

24 Device Overview Submit Documentation Feedback

www.ti.com

Table 2-6. Oscillator/PLL Terminal Functions

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

SIGNAL

NAME NO.

(1)

TYPE

(2)

OTHER

DESCRIPTION

OSCILLATOR, PLL

MXI/ Crystal input MXI for MX oscillator (system oscillator, typically 27 MHz).

CLKIN If the internal oscillator is bypassed, this is the external oscillator clock input.

MXO M1 O DV

MXV

DD

MXV

SS

M24XI F18 I DV
M24XO F19 O DV
M24V

DD

M24V

SS

PLLV

DD18

APLLREFV M3 S

L1 I DV

L5 S
L2 GND

F16 S
F17 GND

M2 S

DD18

DD18
(3)

(3)

DD18
DD18

(3)
(3)
(3)
(3)

Crystal output for MX oscillator

1.8V power supply for MX oscillator
Ground for MX oscillator
Crystal input for M24 oscillator (24 MHz for USB)
Crystal output for M24 oscillator

1.8V power supply for M24 oscillator
Ground for M24 oscillator

1.8 Volt power supply for PLLs (system and USB)
Core voltage reference for PLL logic

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table

Table 2-7. Clock Generator Terminal Functions

SIGNAL

NAME NO.

CLK_OUT0/

GPIO48

K1 I/O/Z DV

CLK_OUT1/ This pin is multiplexed between the USB clock generator, timer, and GPIO.

TIM_IN/ E19 I/O/Z DV
GPIO49 12 MHz or 24 MHz clock outputs.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal

(1)

TYPE

(2)

OTHER

DESCRIPTION

CLOCK GENERATOR

This pin is multiplexed between the PLL1 clock generator and GPIO.

DD18

DD18

For the PLL1 clock generator, it is clock output CLK_OUT0. This is configurable for

13.5 MHz or 27 MHz clock outputs.

For the USB clock generator, it is clock output CLK_OUT1. This is configurable for

Table 2-8. RESET and JTAG Terminal Functions

SIGNAL

NAME NO.

RESET L4 I This is the active low global reset input.

TMS E6 I JTAG test-port mode select input

TDO B5 O/Z JTAG test-port data output

TDI A5 I JTAG test-port data input

TCK A6 I JTAG test-port clock input

RTCK B6 O/Z JTAG test-port return clock output

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = internal pulldown, IPU = internal pullup. (To pull up a signal to the opposite supply rail, a 1-k Ω resistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal

Submit Documentation Feedback Device Overview 25

(1)

TYPE

(2) (3)

OTHER

DESCRIPTION

RESET

IPU

DV

DD18

JTAG

IPU

DV

DD18

–

DV

DD18

IPU

DV

DD18

IPU

DV

DD18

–

DV

DD18

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-8. RESET and JTAG Terminal Functions (continued)

SIGNAL

NAME NO.

TRST D7 I

EMU1 C6 I/O/Z Emulation pin 1

EMU0 D6 I/O/Z Emulation pin 0

(1)

TYPE

(2) (3)

OTHER

IPD JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

DV

DD18

IPU

DV

DD18

IPU

DV

DD18

Table 2-9. EMIFA Terminal Functions

DESCRIPTION

JTAG compatibility statement portion of this data manual .

SIGNAL

NAME NO.

(1)

TYPE

(2)

OTHER

DESCRIPTION

EMIFA BOOT CONFIGURATION

This pin is multiplexed between EMIFA and the VPBE. At reset, the input state is

COUT2/ sampled to set the EMIFA data bus width (EM_WIDTH). For an 8-bit wide EMIFA

B5/ A17 I/O/Z DV

EM_WIDTH After reset, it is video encoder output COUT2 or RGB666/888 Blue output data bit 5

DD18

data bus, EM_WIDTH = 0. For a 16-bit wide EMIFA data bus, EM_WIDTH = 1.
B5.

This pin is multiplexed between DSP boot and the VPBE. At reset, the input state is

COUT3/ sampled to set the DSP boot source DSP_BT. The DSP is booted by the ARM when

B6/ B17 I/O/Z DV

DSP_BT After reset, it is video encoder output COUT3 or RGB666/888 Blue data bit 6 output

DD18

DSP_BT=0. The DSP boots from EMIFA when DSP_BT=1.
B6.

YOUT0/

G5/ D15 I/O/Z DV

AEAW0

DD18

YOUT1/

G6/ D16 I/O/Z DV

AEAW1

DD18

These pins are multiplexed between EMIFA and the VPBE. At reset, the input states

YOUT2/ of AEAW[4:0] are sampled to set the EMIFA address bus width. See Section 3.4.2 ,

G7/ D17 I/O/Z DV

AEAW2 After reset, these are video encoder outputs YOUT[0:4] or RGB666/888 Red and

DD18

YOUT3/

R3/ D18 I/O/Z DV

AEAW3

DD18

Peripheral Selection at Device Reset for details.
Green data bit outputs G5, G6, G7, R3, and R4.

YOUT4/

R4/ E15 I/O/Z DV

AEAW4

DD18

EMIFA FUNCTIONAL PINS: ASYNC / NOR

For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous

EM_CS2 C2 I/O/Z DV

DD18

memories (i.e., NOR flash) or NAND flash. This is the chip select for the default boot
and ROM boot modes.

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous

EM_CS3 B1 I/O/Z DV

DD18

memories (i.e., NOR flash) or NAND flash. In HPI mode, this pin must be pulled high
via an external 10-k Ω resistor.

EM_CS4/ This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO9/ T2 I/O/Z DV

VLYNQ_SCRUN (i.e., NOR flash) or NAND flash.

DD18

For EMIFA, it is Chip Select 4 output EM_CS4 for use with asynchronous memories

EM_CS5/ This pin is multiplexed between EMIFA, GPIO, and VLYNQ.

GPIO8/ T1 I/O/Z DV

VLYNQ_CLOCK (i.e., NOR flash) or NAND flash.

DD18

EM_R/ W/

INTRQ G3 I/O/Z DV

HR/ W

DD18

For EMIFA, it is Chip Select 5 output EM_CS5 for use with asynchronous memories

This pin is multiplexed between EMIFA and ATA/CF.
For EMIFA, it is read/write output EM_R/ W.

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal

Device Overview26 Submit Documentation Feedback

www.ti.com

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_WAIT/

(RDY/ BSY)/ F1 I/O/Z DV

IORDY

EM_OE/

( RE)/ This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.

( IORD)/ For EMIFA, it is output enable output EM_OE.

H4 I/O/Z DV

DIOR

EM_WE

( WE) This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF. For

( IOWR)/ NAND/SmartMedia/xD or EMIFA, it is write enable output EM_WE.

G2 I/O/Z DV

DIOW

EM_BA[0]/ When connected to an 8-bit asynchronous memory, this pin is the lowest order bit of

DA0/ J3 I/O/Z DV
HINT When connected to a 16-bit asynchronous memory, this pin has the same function

EM_BA[1]/

DA1/ H2 I/O/Z DV

GPIO52

EM_A[21]/

GPIO10/ T3 I/O/Z DV

VLYNQ_TXD0

EM_A[20]/

GPIO11/ R3 I/O/Z DV

VLYNQ_RXD0

EM_A[19]/

GPIO12/ R4 I/O/Z DV

VLYNQ_TXD1

EM_A[18]/

GPIO13/ P5 I/O/Z DV

VLYNQ_RXD1

EM_A[17]/

GPIO14/ R2 I/O/Z DV

VLYNQ_TXD2

EM_A[16]/

GPIO15/ R5 I/O/Z DV

VLYNQ_RXD2

EM_A[15]/

GPIO16/ P3 I/O/Z DV

VLYNQ_TXD3

EM_A[14]/

GPIO17/ P4 I/O/Z DV

VLYNQ_RXD3

EM_A[13]/ This pin is multiplexed between EMIFA and GPIO.

GPIO18 For EMIFA, it is address bit 13 output EM_A[13].

EM_A[12]/ This pin is multiplexed between EMIFA and GPIO.

GPIO19 For EMIFA, it is address bit 12 output EM_A[12].

EM_A[11]/ This pin is multiplexed between EMIFA and GPIO.

GPIO20 For EMIFA, it is address bit 11 output EM_A[11].

EM_A[10]/ This pin is multiplexed between EMIFA and GPIO.

GPIO21 For EMIFA, it is address bit 10 output EM_A[10].

EM_A[9]/ This pin is multiplexed between EMIFA and GPIO.

GPIO22 For EMIFA, it is address bit 9 output EM_A[9].

N4 I/O/Z DV

R1 I/O/Z DV

P2 I/O/Z DV

P1 I/O/Z DV

M4 I/O/Z DV

(1)

TYPE

(2)

OTHER

DD18

DD18

DD18

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.
For EMIFA, it is wait state extension input EM_WAIT.

DESCRIPTION

This pin is multiplexed between EMIFA, ATA/CF, and HPI.
For EMIFA, this is the Bank Address 0 output (EM_BA[0]).

DD18

the byte address.
as EMIF address pin 22 (EM_A[22]).

In HPI mode, it is the host interrupt output HINT.
This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.

For EMIFA, this is the Bank Address 1 output EM_BA[1].

DD18

When connected to a 16 bit asynchronous memory this pin is the lowest order bit of
the 16-bit word address.
When connected to an 8-bit asynchronous memory, this pin is the 2nd bit of the
address.

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 21 output EM_A[21].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 20 output EM_A[20].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 19 output EM_A[19].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 18 output EM_A[18].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 17 output EM_A[17].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 16 output EM_A[16].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 15 output EM_A[15].

This pin is multiplexed between EMIFA, GPIO, and VLYNQ.
For EMIFA, it is address bit 14 output EM_A[14].

Submit Documentation Feedback Device Overview 27

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_A[8]/ This pin is multiplexed between EMIFA and GPIO.

GPIO23 For EMIFA, it is address bit 8 output EM_A[8].

EM_A[7]/ This pin is multiplexed between EMIFA and GPIO.

GPIO24 For EMIFA, it is address bit 7 output EM_A[7].

EM_A[6]/ This pin is multiplexed between EMIFA and GPIO.

GPIO25 For EMIFA, it is address bit 6 output EM_A[6].

EM_A[5]/ This pin is multiplexed between EMIFA and GPIO.

GPIO26 For EMIFA, it is address bit 5 output EM_A[5].

EM_A[4]/ This pin is multiplexed between EMIFA and GPIO.

GPIO27 For EMIFA, it is address bit 4 output EM_A[4].

EM_A[3]/ This pin is multiplexed between EMIFA and GPIO.

GPIO28 For EMIFA, it is address bit 3 output EM_A[3].

N3 I/O/Z DV

N2 I/O/Z DV

N1 I/O/Z DV

K3 I/O/Z DV

K4 I/O/Z DV

K2 I/O/Z DV

EM_A[2]/

(CLE)/ J1 I/O/Z DV

HCNTL0

EM_A[1]/

(ALE) J2 I/O/Z DV

HHWIL

EM_A[0]/

DA2/

HCNTL1/

J4 I/O/Z DV

GPIO53

(1)

TYPE

(2)

OTHER

DD18

DD18

DD18

DD18

DD18

DD18

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI.

DD18

In HPI mode, it is control input HCNTL0. The state of HCNTL1 and HCNTL0
determine if address, data, or control information is being transmitted between an
external host and DM6441.

DD18

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD), and HPI.
In HPI mode, it is half-word identification input HHWIL.

This pin is multiplexed between EMIFA, ATA/CF, HPI, and GPIO.
For EMIFA, this is address output EM_A[0], which is the least significant bit on a
32-bit word address.
When connected to a 16-bit asynchronous memory, this pin is the 2nd bit of the

DD18

address.
For an 8-bit asynchronous memory, this pin is the 3rd bit of the address.
For HPI, it is control input HCNTL1. The state of HCNTL1 and HCNTL0 determine if
address, data, or control information is being transmitted between an external host
and DM6441.

DESCRIPTION

Device Overview28 Submit Documentation Feedback

www.ti.com

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_D0/

DD0

EM_D1/

DD1

EM_D2/

DD2

EM_D3/

DD3

EM_D4/

DD4

EM_D5/

DD5

EM_D6/

DD6

EM_D7/

DD7

EM_D8/

DD8

EM_D9/

DD9

EM_D10/

DD10

EM_D11/

DD11

EM_D12/

DD12

EM_D13/

DD13

EM_D14/

DD14

EM_D15/

DD15

EM_A[1]/

(ALE)

EM_A[2]/

(CLE)

E5 I/O/Z DV

D3 I/O/Z DV

F5 I/O/Z DV

E3 I/O/Z DV

E4 I/O/Z DV

D2 I/O/Z DV

F4 I/O/Z DV

C1 I/O/Z DV

F3 I/O/Z DV

E2 I/O/Z DV

G5 I/O/Z DV

G4 I/O/Z DV

D1 I/O/Z DV

F2 I/O/Z DV

H5 I/O/Z DV

E1 I/O/Z DV

J2 I/O/Z DV

J1 I/O/Z DV

EM_WAIT/

(RDY/ BSY)/ F1 I/O/Z DV

IORDY

EM_OE/

( RE)/ This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.

( IORD)/ For NAND/SmartMedia/xD, it is read enable output ( RE).

H4 I/O/Z DV

DIOR

EM_WE

( WE) This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.

( IOWR)/ For NAND/SmartMedia/xD, it is write enable output ( WE).

G2 I/O/Z DV

DIOW

EM_CS2 C2 I/O/Z DV

EM_CS3 B1 I/O/Z DV

EM_CS4/ This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

GPIO9/ T2 I/O/Z DV

VLYNQ_SCRUN NAND flash.

(1)

TYPE

(2)

OTHER

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

These pins are multiplexed between EMIFA (NAND) and ATA/CF. In all cases they

DESCRIPTION

are used as a 16 bit bidirectional data bus.

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

For EMIFA (NAND), these are EM_D[15:0].

EMIFA FUNCTIONAL PINS: NAND / SMARTMEDIA / xD

DD18

DD18

DD18

DD18

DD18

For NAND/SmartMedia/xD, it is Address Latch Enable output (ALE).

For NAND/SmartMedia/xD, this pin is the Command Latch Enable output (CLE).

This pin is multiplexed between EMIFA (NAND/SmartMedia/xD) and ATA/CF.
For NAND/SmartMedia/xD, it is ready/busy input (RDY/ BSY).

For EMIFA, this pin is Chip Select 2 output EM_CS2 for use with asynchronous

DD18

DD18

DD18

memories (i.e. NOR flash) or NAND flash. This is the chip select for the default boot
and ROM boot modes.

For EMIFA, this pin is Chip Select 3 output EM_CS3 for use with asynchronous
memories (i.e. NOR flash) or NAND flash.

Select 4 output EM_CS4 for use with asynchronous memories (i.e., NOR flash) or

TMS320DM6441

Submit Documentation Feedback Device Overview 29

www.ti.com

TMS320DM6441
Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

Table 2-9. EMIFA Terminal Functions (continued)

SIGNAL

NAME NO.

EM_CS5/ This pin is multiplexed between EMIFA, GPIO, and VLYNQ. For EMIFA, it is Chip

GPIO8/ T1 I/O/Z DV

VLYNQ_CLOCK NAND flash.

EM_D0/

DD0

EM_D1/

DD1

EM_D2/

DD2

EM_D3/

DD3

EM_D4/

DD4

EM_D5/

DD5

EM_D6/

DD6

EM_D7/

DD7

EM_D8/

DD8

EM_D9/

DD9

EM_D10/

DD10

EM_D11/

DD11

EM_D12/

DD12

EM_D13/

DD13

EM_D14/

DD14

EM_D15/

DD15

E5 I/O/Z DV

D3 I/O/Z DV

F5 I/O/Z DV

E3 I/O/Z DV

E4 I/O/Z DV

D2 I/O/Z DV

F4 I/O/Z DV

C1 I/O/Z DV

F3 I/O/Z DV

E2 I/O/Z DV

G5 I/O/Z DV

G4 I/O/Z DV

D1 I/O/Z DV

F2 I/O/Z DV

H5 I/O/Z DV

E1 I/O/Z DV

(1)

TYPE

(2)

OTHER

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

Select 5 output EM_CS5 for use with asynchronous memories (i.e., NOR flash) or

These pins are multiplexed between EMIFA (NAND) and ATA/CF. In all cases they

DESCRIPTION

are used as a 16 bit bidirectional data bus.

DD18

DD18

DD18

DD18

DD18

DD18

DD18

DD18

For EMIFA (NAND), these are EM_D[15:0].

Device Overview30 Submit Documentation Feedback