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TMS320DM643X DMP
User Manual
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User Manual 2
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Texas Instruments TMS320DM643X DMP User Manual

TMS320DM643x DMP Universal Asynchronous Receiver/Transmitter (UART)
User's Guide
Literature Number: SPRU997C
December 2009
2
SPRU997C–December 2009
Copyright © 2009, Texas Instruments Incorporated
Preface ....................................................................................................................................... 6
1 Introduction ........................................................................................................................ 7
1.1 Purpose of the Peripheral .............................................................................................. 7
1.2 Features .................................................................................................................. 7
1.3 Functional Block Diagram .............................................................................................. 8
1.4 Industry Standard(s) Compliance Statement ........................................................................ 8
2 Peripheral Architecture ...................................................................................................... 10
2.1 Clock Generation and Control ........................................................................................ 10
2.2 Signal Descriptions .................................................................................................... 12
2.3 Pin Multiplexing ........................................................................................................ 12
2.4 Protocol Description ................................................................................................... 12
2.5 Endianness Considerations .......................................................................................... 13
2.6 Operation ................................................................................................................ 14
2.7 Reset Considerations .................................................................................................. 18
2.8 Initialization ............................................................................................................. 18
2.9 Interrupt Support ....................................................................................................... 18
2.10 DMA Event Support ................................................................................................... 20
2.11 Power Management ................................................................................................... 20
2.12 Emulation Considerations ............................................................................................. 20
2.13 Exception Processing ................................................................................................. 21
3 Registers .......................................................................................................................... 21
3.1 Receiver Buffer Register (RBR) ...................................................................................... 22
3.2 Transmitter Holding Register (THR) ................................................................................. 23
3.3 Interrupt Enable Register (IER) ...................................................................................... 24
3.4 Interrupt Identification Register (IIR) ................................................................................ 25
3.5 FIFO Control Register (FCR) ......................................................................................... 26
3.6 Line Control Register (LCR) .......................................................................................... 28
3.7 Modem Control Register (MCR) ..................................................................................... 30
3.8 Line Status Register (LSR) ........................................................................................... 31
3.9 Divisor Latches (DLL and DLH) ...................................................................................... 33
3.10 Peripheral Identification Registers (PID1 and PID2) .............................................................. 35
3.11 Power and Emulation Management Register (PWREMU_MGMT) .............................................. 36
Appendix A Revision History ...................................................................................................... 37

SPRU997C–December 2009 Table of Contents

Copyright © 2009, Texas Instruments Incorporated
3
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List of Figures
1 UART Block Diagram....................................................................................................... 9
2 UART Clock Generation Diagram....................................................................................... 10
3 Relationships Between Data Bit, BCLK, and UART Input Clock.................................................... 11
4 UART Protocol Formats .................................................................................................. 13
5 UART Interface Using Autoflow Diagram .............................................................................. 16
6 Autoflow Functional Timing Waveforms for RTS...................................................................... 17
7 Autoflow Functional Timing Waveforms for CTS...................................................................... 17
8 UART Interrupt Request Enable Paths ................................................................................. 19
9 Receiver Buffer Register (RBR) ......................................................................................... 22
10 Transmitter Holding Register (THR) .................................................................................... 23
11 Interrupt Enable Register (IER).......................................................................................... 24
12 Interrupt Identification Register (IIR).................................................................................... 25
13 FIFO Control Register (FCR) ............................................................................................ 27
14 Line Control Register (LCR) ............................................................................................. 28
15 Modem Control Register (MCR)......................................................................................... 30
16 Line Status Register (LSR)............................................................................................... 31
17 Divisor LSB Latch (DLL).................................................................................................. 34
18 Divisor MSB Latch (DLH)................................................................................................. 34
19 Peripheral Identification Register 1 (PID1)............................................................................. 35
20 Peripheral Identification Register 2 (PID2)............................................................................. 35
21 Power and Emulation Management Register (PWREMU_MGMT) ................................................. 36
4
List of Figures SPRU997C–December 2009
Copyright © 2009, Texas Instruments Incorporated
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1 UART Supported Features/Characteristics by Instance ............................................................... 8
2 Baud Rate Examples for 27 MHz UART Input Clock................................................................. 11
3 UART Signal Descriptions................................................................................................ 12
4 Character Time for Word Lengths....................................................................................... 15
5 UART Interrupt Requests Descriptions................................................................................. 19
6 UART Registers ........................................................................................................... 21
7 Receiver Buffer Register (RBR) Field Descriptions................................................................... 22
8 Transmitter Holding Register (THR) Field Descriptions.............................................................. 23
9 Interrupt Enable Register (IER) Field Descriptions ................................................................... 24
10 Interrupt Identification Register (IIR) Field Descriptions.............................................................. 25
11 Interrupt Identification and Interrupt Clearing Information............................................................ 26
12 FIFO Control Register (FCR) Field Descriptions ...................................................................... 27
13 Line Control Register (LCR) Field Descriptions ....................................................................... 28
14 Relationship Between ST, EPS, and PEN Bits in LCR............................................................... 29
15 Number of STOP Bits Generated ....................................................................................... 29
16 Modem Control Register (MCR) Field Descriptions................................................................... 30
17 Line Status Register (LSR) Field Descriptions ........................................................................ 31
18 Divisor LSB Latch (DLL) Field Descriptions............................................................................ 34
19 Divisor MSB Latch (DLH) Field Descriptions .......................................................................... 34
20 Peripheral Identification Register 1 (PID1) Field Descriptions....................................................... 35
21 Peripheral Identification Register 2 (PID2) Field Descriptions....................................................... 35
22 Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions........................... 36
23 Document Revision History .............................................................................................. 37
List of Tables
SPRU997C–December 2009 List of Tables
Copyright © 2009, Texas Instruments Incorporated
5
About This Manual
This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM643x Digital Media Processor (DMP) .
Notational Conventions
This document uses the following conventions.
• Hexadecimal numbers are shown with the suffix h. For example, the following number is 40 hexadecimal (decimal 64): 40h.
• Registers in this document are shown in figures and described in tables. – Each register figure shows a rectangle divided into fields that represent the fields of the register.
Each field is labeled with its bit name, its beginning and ending bit numbers above, and its read/write properties below. A legend explains the notation used for the properties.
– Reserved bits in a register figure designate a bit that is used for future device expansion.
Related Documentation From Texas Instruments
The following documents describe the TMS320DM643x Digital Media Processor (DMP). Copies of these documents are available on the Internet at www.ti.com. Tip: Enter the literature number in the search box provided at www.ti.com.
The current documentation that describes the DM643x DMP, related peripherals, and other technical collateral, is available in the C6000 DSP product folder at: www.ti.com/c6000.
SPRU978 — TMS320DM643x DMP DSP Subsystem Reference Guide. Describes the digital signal
processor (DSP) subsystem in the TMS320DM643x Digital Media Processor (DMP).

Preface

SPRU997C–December 2009
Read This First
SPRU983 — TMS320DM643x DMP Peripherals Overview Reference Guide. Provides an overview and
briefly describes the peripherals available on the TMS320DM643x Digital Media Processor (DMP).
SPRAA84 — TMS320C64x to TMS320C64x+ CPU Migration Guide. Describes migrating from the
Texas Instruments TMS320C64x digital signal processor (DSP) to the TMS320C64x+ DSP. The objective of this document is to indicate differences between the two cores. Functionality in the devices that is identical is not included.
SPRU732 — TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide. Describes the CPU
architecture, pipeline, instruction set, and interrupts for the TMS320C64x and TMS320C64x+ digital signal processors (DSPs) of the TMS320C6000 DSP family. The C64x/C64x+ DSP generation comprises fixed-point devices in the C6000 DSP platform. The C64x+ DSP is an enhancement of the C64x DSP with added functionality and an expanded instruction set.
SPRU871 — TMS320C64x+ DSP Megamodule Reference Guide. Describes the TMS320C64x+ digital
signal processor (DSP) megamodule. Included is a discussion on the internal direct memory access (IDMA) controller, the interrupt controller, the power-down controller, memory protection, bandwidth management, and the memory and cache.
6
Preface SPRU997C–December 2009
Copyright © 2009, Texas Instruments Incorporated
Universal Asynchronous Receiver/Transmitter (UART)

1 Introduction

This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM643x Digital Media Processor (DMP) .

1.1 Purpose of the Peripheral

The UART peripheral is based on the industry standard TL16C550 asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.
The UART includes a programmable baud generator capable of dividing the UART input clock by divisors from 1 to 65 535 and producing a 16 × reference clock for the internal transmitter and receiver logic. For detailed timing and electrical specifications for the UART, see the device specific data manual.
User's Guide
SPRU997C–December 2009

1.2 Features

The UART peripheral has the following features:
• Programmable baud rates up to 128 kbps (frequency pre-scale values from 1 to 65535)
• Fully programmable serial interface characteristics: – 5, 6, 7, or 8-bit characters
– Even, odd, or no PARITY bit generation and detection – 1, 1.5, or 2 STOP bit generation
• 16-byte depth transmitter and receiver FIFOs: – The UART can be operated with or without the FIFOs
– 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• DMA signaling capability for both received and transmitted data
• CPU interrupt capability for both received and transmitted data
• Operates in little-endian mode
• False START bit detection
• Line break generation and detection
• Internal diagnostic capabilities: – Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
• Programmable autoflow control using CTS and RTS signals (not supported on all UARTs. See the device-specific data manual for supported features.)
• Modem control functions using CTS and RTS signals (not supported on all UARTs. See the device-specific data manual for supported features.)
SPRU997C–December 2009 Universal Asynchronous Receiver/Transmitter (UART)
Copyright © 2009, Texas Instruments Incorporated
7
Introduction
Table 1 summarizes the capabilities supported on the UART. Note that the number of UARTs and their
supported features vary on each device, see the device-specific data manual for more details.
Feature Support
5, 6, 7 or 8-bit characters Supported Even, odd, or no PARITY bit Supported 1, 1.5, or 2 STOP bit generation Supported Line break generation and detection Supported Internal loop back Supported DMA sync events for both received and transmitted data Supported 1, 4, 8, or 14 byte selectable receiver FIFO trigger level Supported Polling/Interrupt Supported Max speed 128 kbps Supported Modem control functions using CTS and RTS Supported Autoflow control using CTS and RTS Supported DTR and DSR Not supported Ring indication Not supported Carrier detection Not supported Single-character transfer mode (mode 0) in DMA mode Not supported
(1)
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Table 1. UART Supported Features/Characteristics by Instance
(1)
(1)
Not supported on all UARTs. See the device-specific data manual for supported features.

1.3 Functional Block Diagram

A functional block diagram of the UART is shown in Figure 1.

1.4 Industry Standard(s) Compliance Statement

The UART peripheral is based on the industry standard TL16C550 asynchronous communications element, which is a functional upgrade of the TL16C450. Any deviations in supported functions are indicated in Table 1.
The information in this document assumes the reader is familiar with these standards.
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Universal Asynchronous Receiver/Transmitter (UART) SPRU997C–December 2009
Copyright © 2009, Texas Instruments Incorporated
8
Receiver
Buffer
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Baud
Generator
Receiver
FIFO
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Line
Control
Register
Transmitter
FIFO
Interrupt
Enable
Register
Interrupt
Identification
Register
FIFO
Control
Register
Interrupt/
Event
Control
Logic
S e
l e c
t
Data
Bus
Buffer
RX
TX
Peripheral Bus
S e
l e c
t
Receiver
Shift
Register
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
Shift
Register
Control
Logic
16
8
8
8
8
8
Interrupt to CPU
16
8
pin
pin
8
88
8
Power and
Emulation
Control
Register
Event to DMA controller
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Introduction
Figure 1. UART Block Diagram
SPRU997C–December 2009 Universal Asynchronous Receiver/Transmitter (UART)
Copyright © 2009, Texas Instruments Incorporated
9
Divisor +
UART input clock frequency
Desired baud rate 16
Processor
generator
Clock
DLH:DLL
UART input clock
DSP input clock
UART
Receiver
timing and
control
Transmitter
timing and
control
Baud
generator
BCLK
Other logic
Peripheral Architecture

2 Peripheral Architecture

2.1 Clock Generation and Control

The UART bit clock is sourced from the PLLC1 AUXCLK. It supports up to 128 kbps maximum data rate.
Figure 2 is a conceptual clock generation diagram for the UART. The processor clock generator receives
a signal from an external clock source and produces a UART input clock with a programmed frequency. The UART contains a programmable baud generator that takes an input clock and divides it by a divisor in the range between 1 and (216- 1) to produce a baud clock (BCLK). The frequency of BCLK is sixteen times (16 ×) the baud rate; each received or transmitted bit lasts 16 BCLK cycles. When the UART is receiving, the bit is sampled in the 8th BCLK cycle. The formula to calculate the divisor is:
Two 8-bit register fields (DLH and DLL), called divisor latches, hold this 16-bit divisor. DLH holds the most significant bits of the divisor, and DLL holds the least significant bits of the divisor. For information about these register fields, see Section 3. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value.
Figure 3 summarizes the relationship between the transferred data bit, BCLK, and the UART input clock.
Example baud rates and divisor values relative to a 27-MHz UART input clock are shown in Table 2.
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(1)
Figure 2. UART Clock Generation Diagram
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Universal Asynchronous Receiver/Transmitter (UART) SPRU997C–December 2009
Copyright © 2009, Texas Instruments Incorporated
BCLK
Each bit lasts 16 BCLK cycles.
When receiving, the UART samples the bit in the 8th cycle.
D0
TX,
RX
D1 D2
PARITY
D7D6D5
STOP2STOP1
D1 D4D2 D3
START
D0
TX,
RX
UART input clock
n UART input clock cycles, where n = divisor in DLH:DLL
n
BCLK
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Peripheral Architecture
Figure 3. Relationships Between Data Bit, BCLK, and UART Input Clock
Table 2. Baud Rate Examples for 27 MHz UART Input Clock
Baud Rate Divisor Value Actual Baud Rate Error (%)
2400 703 2400.427 0.018 4800 352 4794.034 -0.124 9600 176 9588.068 -0.124 19200 88 19176.14 -0.124 38400 44 38352.27 -0.124 56000 30 56250 0.446 128000 13 129807.7 1.412
SPRU997C–December 2009 Universal Asynchronous Receiver/Transmitter (UART)
Copyright © 2009, Texas Instruments Incorporated
11
Peripheral Architecture

2.2 Signal Descriptions

The UARTs utilize a minimal number of signal connections to interface with external devices. The UART signal descriptions are included in Table 3. Note that the number of UARTs and their supported features vary on each device, see the device-specific data manual for more details.
Signal Name
UTXDn Output Serial data transmit URXDn Input Serial data receive UCTSn Input Clear-to-Send handshaking signal URTSn Output Request-to-Send handshaking signal
(1)
The value n indicates the applicable UART; that is, UART0, UART1, etc.
(1)
Signal Type Function

2.3 Pin Multiplexing

On the DM643x DMP extensive pin multiplexing is used to accommodate the largest number of peripheral functions in the smallest possible package. Pin multiplexing is controlled using a combination of hardware configuration at device reset and software programmable register settings. Refer to the device-specific data manual to determine how pin multiplexing affects the UART.

2.4 Protocol Description

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Table 3. UART Signal Descriptions

2.4.1 Transmission

The UART transmitter section includes a transmitter hold register (THR) and a transmitter shift register (TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART transmitter sends the following to the receiving device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1, 1.5, or 2 STOP bits

2.4.2 Reception

The UART receiver section includes a receiver shift register (RSR) and a receiver buffer register (RBR). When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Receiver section control is a function of the UART line control register (LCR). Based on the settings chosen in LCR, the UART receiver accepts the following from the transmitting device:
• 1 START bit
• 5, 6, 7, or 8 data bits
• 1 PARITY bit (optional)
• 1 STOP bit (any other STOP bits transferred with the above data are not detected)
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Universal Asynchronous Receiver/Transmitter (UART) SPRU997C–December 2009
Copyright © 2009, Texas Instruments Incorporated
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