Texas Instruments TMS320DM642, TMS320DM642ZNZ600 Datasheet

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Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor

1.1 Features

• High-Performance Digital Media Processor

– 2-, 1.67-, 1.39-ns Instruction Cycle Time
– 500-, 600-, 720-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 4000, 4800, 5760 MIPS
– Fully Software-Compatible With C64x™

• VelociTI.2™ Extensions to VelociTI™

Advanced Very-Long-Instruction-Word (VLIW)
TMS320C64x™ DSP Core
– Eight Highly Independent Functional Units • Management Data Input/Output (MDIO)

With VelociTI.2™ Extensions:

• Six ALUs (32-/40-Bit), Each Supports

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle

• Two Multipliers Support Four 16 x 16-Bit

Multiplies (32-Bit Results) per Clock
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
Results) per Clock Cycle

– Load-Store Architecture With Non-Aligned

Support
– 64 32-Bit General-Purpose Registers
– Instruction Packing Reduces Code Size
– All Instructions Conditional

• Instruction Set Features

– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
– Normalization, Saturation, Bit-Counting
– VelociTI.2™ Increased Orthogonality

• L1/L2 Memory Architecture

– 128K-Bit (16K-Byte) L1P Program Cache

(Direct Mapped)
– 128K-Bit (16K-Byte) L1D Data Cache (2-Way

Set-Associative)
– 2M-Bit (256K-Byte) L2 Unified Mapped

RAM/Cache (Flexible RAM/Cache

Allocation)

• Endianess: Little Endian, Big Endian

• 64-Bit External Memory Interface (EMIF)

– Glueless Interface to Asynchronous

Memories (SRAM and EPROM) and

Synchronous Memories (SDRAM, SBSRAM,

ZBT SRAM, and FIFO)

– 1024M-Byte Total Addressable External

Memory Space

• Enhanced Direct-Memory-Access (EDMA)

Controller (64 Independent Channels)

• 10/100 Mb/s Ethernet MAC (EMAC)

– IEEE 802.3 Compliant
– Media Independent Interface (MII)
– 8 Independent Transmit (TX) Channels and

1 Receive (RX) Channel

• Three Configurable Video Ports

– Providing a Glueless I/F to Common Video

Decoder and Encoder Devices

– Supports Multiple Resolutions/Video Stds

• VCXO Interpolated Control Port (VIC)

– Supports Audio/Video Synchronization

• Host-Port Interface (HPI) [32-/16-Bit]

• 32-Bit/66-MHz, 3.3-V Peripheral Component

Interconnect (PCI) Master/Slave Interface
Conforms to PCI Specification 2.2

• Multichannel Audio Serial Port (McASP)

– Eight Serial Data Pins
– Wide Variety of I2S and Similar Bit Stream

Format

– Integrated Digital Audio I/F Transmitter

Supports S/PDIF, IEC60958-1, AES-3,
CP-430 Formats

• Inter-Integrated Circuit ( I2C Bus™)

• Two Multichannel Buffered Serial Ports

• Three 32-Bit General-Purpose Timers

• Sixteen General-Purpose I/O (GPIO) Pins

• Flexible PLL Clock Generator

• IEEE-1149.1 (JTAG) Boundary-

Scan-Compatible

• 548-Pin Ball Grid Array (BGA) Package

(GDK and ZDK Suffixes), 0.8-mm Ball Pitch

• 548-Pin Ball Grid Array (BGA) Package

(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch

• 0.13-µm/6-Level Cu Metal Process (CMOS)

• 3.3-V I/O, 1.2-V Internal (-500)

• 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600,

-720)

TMS320DM642

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.

Windows is a registered trademark of Microsoft Corporation.
I2C Bus is a trademark of Philips Electronics N.V..

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2002–2007, Texas Instruments Incorporated

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

1.2 Description

The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point

DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on

the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)

architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice

for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the

DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The

DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of

array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length

and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic

units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units

include new instructions to accelerate the performance in video and imaging applications and extend the

parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates

(MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for

a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory,

and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals.

The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is

a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory

space that is shared between program and data space. L2 memory can be configured as mapped

memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a

10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO

interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated

circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose

timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component

interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event

generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of

interfacing to synchronous and asynchronous memories and peripherals.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port

peripherals provide a glueless interface to common video decoder and encoder devices. The DM642

video port peripherals support multiple resolutions and video standards (e.g., CCIR601, ITU-BT.656,

BT.1120, SMPTE 125M, 260M, 274M, and 296M).

These three video port peripherals are configurable and can support either video capture and/or video

display modes. Each video port consists of two channels — A and B with a 5120-byte capture/display

buffer that is splittable between the two channels.

For more details on the Video Port peripherals, see the TMS320C64x DSP Video Port/VCXO Interpolated

Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can

be individually allocated to any of the two zones. The serial port supports time-division multiplexing on

each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins

transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on

multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC

Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3,

CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of

user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection

circuit for each high-frequency master clock which verifies that the master clock is within a programmed

frequency range .

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The VCXO interpolated control (VIC) port provides digital-to-analog conversion with resolution from 9-bits

to up to 16-bits. The output of the VIC is a single bit interpolated D/A output.For more details on the VIC

port, see the TMS320C64x DSP Video Port/VCXO Interpolated Control (VIC) Port Reference Guide

(literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP

core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10

Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of

service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows

efficient data transmission and reception.For more details on the EMAC, see the TMS320C6000 DSP

Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference

Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to

enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the

MDIO module transparently monitors its link state by reading the PHY status register. Link change events

are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link

status of the device without continuously performing costly MDIO accesses. For more details on the

MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data

Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices and

communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP)

may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The DM642 has a complete set of development tools which includes: a new C compiler, an assembly

optimizer to simplify programming and scheduling, and a Windows

®

debugger interface for visibility into

source code execution.

1.2.1 Device Compatibility

The DM642 device is a code-compatible member of the C6000™ DSP platform.

The C64x™ DSP generation of devices has a diverse and powerful set of peripherals.

For more detailed information on the device compatibility and similarities/differences among the DM642

and other C64x™ devices, see the TMS320DM642 Technical Overview (literature number SPRU615).

Submit Documentation Feedback TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor 3

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HPI32

OR

HPI16

PCI-66

Test

C64x DSP Core

Data Path B

B Register File

B31−B16

B15−B0

Instruction Fetch

Instruction Dispatch

Advanced Instruction Packet

Instruction Decode

Data Path A

A Register File

A31−A16

A15−A0

Power-Down

Logic

.L1 .S1 .M1 .D1 .D2 .M2 .S2 .L2

64

SDRAM

FIFO

SBSRAM

SRAM

L1P Cache

Direct-Mapped

16K Bytes Total

Control

Registers

Control

Logic

L1D Cache 2-Way Set-Associative

16K Bytes Total

Advanced

In-Circuit

Emulation

Interrupt

Control

TMS320DM642

Enhanced

DMA

Controller

(EDMA)

L2

Cache

Memory

256kBytes

PLL

(x1, x6, x12)

Timer 2

EMIF A

ZBT SRAM

Timer 1

Boot Configuration

ROM/FLASH

I/O Devices

Video Port 2

(VP2)

VCXO
Interpolated
Control Port

(VIC)

8/10-bit VP1

McBSP1

(A)

Video Port 1

(VP1)

AND

McASP0

Data

OR

OR

AND/OR

EMAC

MDIO

OR

GP0

I2C0

16

2

(B)

8/10-bit VP0

McBSP0

(A)

Video Port 0

(VP0)

AND

McASP0

Control

OR

OR

Timer 0

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

1.3 Functional Block Diagram

Figure 1-1 shows the functional block diagram of the DM642 device.

A. McBSPs: Framing Chips – H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
B. The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins. The Video

Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins. The PCI peripheral is
muxed with the HPI(32/16), EMAC, and MDIO peripherals. For more details on the multiplexed pins of these
peripherals, see the Device Configurations section of this data sheet.

Figure 1-1. Functional Block Diagram

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TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Contents

1 TMS320DM642 Video/Imaging Fixed-Point Digital 5 DM642 Peripheral Information and Electrical

Signal Processor ......................................... 1 Specifications ........................................... 73

1.1 Features .............................................. 1 5.1 Parameter Information .............................. 73

1.2 Description ............................................ 2

1.2.1 Device Compatibility ................................. 3

1.3 Functional Block Diagram ............................ 4

2 Device Overview ......................................... 6

2.1 Device Characteristics ................................ 6

2.2 CPU (DSP Core) Description ......................... 7

2.3 Memory Map Summary ............................. 13

2.4 Bootmode ........................................... 16

2.5 Pin Assignments .................................... 16

2.6 Development ........................................ 50

3 Device Configurations ................................. 54

3.1 Configurations at Reset ............................. 54

3.2 Configurations After Reset .......................... 56

3.3 Peripheral Configuration Lock ....................... 59

3.4 Device Status Register Description ................. 61

3.5 Multiplexed Pin Configurations ...................... 63

3.6 Debugging Considerations .......................... 65

3.7 Configuration Examples ............................. 66

4 Device Operating Conditions ........................ 70

4.1 Absolute Maximum Ratings Over Operating Case
Temperature Range

(Unless Otherwise Noted) .......................... 70

4.2 Recommended Operating Conditions ............... 70

4.3 Electrical Characteristics Over Recommended
Ranges of Supply Voltage and Operating Case

Temperature (Unless Otherwise Noted) ............ 71

5.2 Recommended Clock and Control Signal Transition

Behavior ............................................. 75

5.3 Power Supplies ...................................... 75

5.4 Enhanced Direct Memory Access (EDMA)

Controller ............................................ 79

5.5 Interrupts ............................................ 83

5.6 Reset ................................................ 85

5.7 Clock PLL ........................................... 88

5.8 External Memory Interface (EMIF) .................. 94

5.9 Multichannel Audio Serial Port (McASP0)

Peripheral .......................................... 110

5.10 Inter-Integrated Circuit (I2C) ....................... 118

5.11 Host-Port Interface (HPI) ........................... 123

5.12 Peripheral Component Interconnect (PCI) ......... 129

5.13 Multichannel Buffered Serial Port (McBSP) ........ 133

5.14 Video Port .......................................... 142

5.15 VCXO Interpolated Control (VIC) .................. 150

5.16 Ethernet Media Access Controller (EMAC) ........ 152

5.17 Management Data Input/Output (MDIO) ........... 158

5.18 Timer ............................................... 160

5.19 General-Purpose Input/Output (GPIO) ............. 162

5.20 JTAG ............................................... 165

Revision History ............................................ 167

6 Mechanical Data ....................................... 168

6.1 Thermal Data ...................................... 168

6.2 Packaging Information ............................. 169

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

2 Device Overview

2.1 Device Characteristics

Table 2-1 provides an overview of the DM642 DSP. The table shows significant features of the DM642

device, including the capacity of on-chip RAM, the peripherals, the CPU frequency, and the package type
with pin count.

Table 2-1. Characteristics of the DM642 Processor

HARDWARE FEATURES DM642

EMIFA (64-bit bus width)
(clock source = AECLKIN)

EDMA (64 independent channels) 1
McASP0 (uses Peripheral Clock [AUXCLK]) 1
I2C0 (uses Peripheral Clock) 1

Peripherals
Not all peripherals pins are

available at the same time
(For more detail, see the
Device Configuration
section).

On-Chip Memory

CPU ID + CPU Rev ID Control Status Register (CSR.[31:16]) 0x0C01
JTAG BSDL_ID JTAGID register (address location: 0x01B3F008) 0x0007902F
Frequency MHz 500, 600, 720

Cycle Time ns

Voltage

PLL Options CLKIN frequency multiplier Bypass (x1), x6, x12

BGA Package

Process Technology µm 0.13 µm
Product Status

(1) On this DM64x™ device, the rated EMIF speed affects only the SDRAM interface on the EMIF. For more detailed information, see the

EMIF device speed portion of this data sheet.

(2) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

(2)

HPI (32- or 16-bit user selectable) 1 (HPI16 or HPI32)
PCI (32-bit), 66-MHz/33-MHz

[DeviceID Register value 0x9065]
McBSPs

(internal clock source = CPU/4 clock frequency)
Configurable Video Ports (VP0, VP1, VP2) 3
10/100 Ethernet MAC (EMAC) 1
Management Data Input/Output (MDIO) 1
VCXO Interpolated Control Port (VIC) 1
32-Bit Timers

(internal clock source = CPU/8 clock frequency)
General-Purpose Input/Output Port (GP0) 16
Size (Bytes) 288K

Organization 16KB L1 Data (L1D) Cache

Core (V)
I/O (V) 3.3 V

23 x 23 mm 548-Pin BGA (GDK and ZDK)
27 x 27 mm 548-Pin BGA (GNZ and ZNZ)

Product Preview (PP), Advance Information (AI),
or Production Data (PD)

16K-Byte (16KB) L1 Program (L1P) Cache
256KB Unified Mapped RAM/Cache (L2)

2 ns (DM642-500) and (DM642 A-500)

[500 MHz CPU, 100 MHz EMIF

1.67 ns (DM642-600) and (DM642 A-600)

[600 MHz CPU, 133 MHz EMIF

1.39 ns (DM642-720)

[720 MHz CPU, 133 MHz EMIF

1.4 V ( A-500, A-600, -600, -720)

1.2 V (–500)

1

1

2

3

(1)

, 33 MHz PCI port]

(1)

, 66 MHz PCI port]

(1)

, 66 MHz PCI port]

PD

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2.2 CPU (DSP Core) Description

The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW
architecture features controls by which all eight units do not have to be supplied with instructions if they
are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs
to the same execute packet as the previous instruction, or whether it should be executed in the following
clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute
packets can vary in size. The variable-length execute packets are a key memory-saving feature,
distinguishing the C64x CPUs from other VLIW architectures. The C64x™ VelociTI.2™ extensions add
enhancements to the TMS320C62x™ DSP VelociTI™ architecture. These enhancements include:

• Register file enhancements

• Data path extensions

• Quad 8-bit and dual 16-bit extensions with data flow enhancements

• Additional functional unit hardware

• Increased orthogonality of the instruction set

• Additional instructions that reduce code size and increase register flexibility

The CPU features two sets of functional units. Each set contains four units and a register file. One set
contains functional units .L1, .S1, .M1, and .D1; the other set contains units .D2, .M2, .S2, and .L2. The
two register files each contain 32 32-bit registers for a total of 64 general-purpose registers. In addition to
supporting the packed 16-bit and 32-/40-bit fixed-point data types found in the C62x™ VelociTI™ VLIW
architecture, the C64x™ register files also support packed 8-bit data and 64-bit fixed-point data types. The
two sets of functional units, along with two register files, compose sides A and B of the CPU [see the
functional block and CPU (DSP core) diagram, and Figure 2-1 ]. The four functional units on each side of
the CPU can freely share the 32 registers belonging to that side. Additionally, each side features a "data
cross path"—a single data bus connected to all the registers on the other side, by which the two sets of
functional units can access data from the register files on the opposite side. The C64x CPU pipelines
data-cross-path accesses over multiple clock cycles. This allows the same register to be used as a
data-cross-path operand by multiple functional units in the same execute packet. All functional units in the
C64x CPU can access operands via the data cross path. Register access by functional units on the same
side of the CPU as the register file can service all the units in a single clock cycle. On the C64x CPU, a
delay clock is introduced whenever an instruction attempts to read a register via a data cross path if that
register was updated in the previous clock cycle.

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

In addition to the C62x™ DSP fixed-point instructions, the C64x™ DSP includes a comprehensive
collection of quad 8-bit and dual 16-bit instruction set extensions. These VelociTI.2™ extensions allow the
C64x CPU to operate directly on packed data to streamline data flow and increase instruction set
efficiency. This is a key factor for video and imaging applications.

Another key feature of the C64x CPU is the load/store architecture, where all instructions operate on
registers (as opposed to data in memory). Two sets of data-addressing units (.D1 and .D2) are
responsible for all data transfers between the register files and the memory. The data address driven by
the .D units allows data addresses generated from one register file to be used to load or store data to or
from the other register file. The C64x .D units can load and store bytes (8 bits), half-words (16 bits), and
words (32 bits) with a single instruction. And with the new data path extensions, the C64x .D unit can load
and store doublewords (64 bits) with a single instruction. Furthermore, the non-aligned load and store
instructions allow the .D units to access words and doublewords on any byte boundary. The C64x CPU
supports a variety of indirect addressing modes using either linear- or circular-addressing with 5- or 15-bit
offsets. All instructions are conditional, and most can access any one of the 64 registers. Some registers,
however, are singled out to support specific addressing modes or to hold the condition for conditional
instructions (if the condition is not automatically "true").

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The two .M functional units perform all multiplication operations. Each of the C64x .M units can perform
two 16 × 16-bit multiplies or four 8 × 8-bit multiplies per clock cycle. The .M unit can also perform 16 ×
32-bit multiply operations, dual 16 × 16-bit multiplies with add/subtract operations, and quad 8 × 8-bit
multiplies with add operations. In addition to standard multiplies, the C64x .M units include bit-count,
rotate, Galois field multiplies, and bidirectional variable shift hardware.

The two .S and .L functional units perform a general set of arithmetic, logical, and branch functions with
results available every clock cycle. The arithmetic and logical functions on the C64x CPU include single
32-bit, dual 16-bit, and quad 8-bit operations.

The processing flow begins when a 256-bit-wide instruction fetch packet is fetched from a program
memory. The 32-bit instructions destined for the individual functional units are "linked" together by "1" bits
in the least significant bit (LSB) position of the instructions. The instructions that are "chained" together for
simultaneous execution (up to eight in total) compose an execute packet. A "0" in the LSB of an
instruction breaks the chain, effectively placing the instructions that follow it in the next execute packet. A
C64x™ DSP device enhancement now allows execute packets to cross fetch-packet boundaries. In the
TMS320C62x™/TMS320C67x™ DSP devices, if an execute packet crosses the fetch-packet boundary
(256 bits wide), the assembler places it in the next fetch packet, while the remainder of the current fetch
packet is padded with NOP instructions. In the C64x™ DSP device, the execute boundary restrictions
have been removed, thereby, eliminating all of the NOPs added to pad the fetch packet, and thus,
decreasing the overall code size. The number of execute packets within a fetch packet can vary from one
to eight. Execute packets are dispatched to their respective functional units at the rate of one per clock
cycle and the next 256-bit fetch packet is not fetched until all the execute packets from the current fetch
packet have been dispatched. After decoding, the instructions simultaneously drive all active functional
units for a maximum execution rate of eight instructions every clock cycle. While most results are stored in
32-bit registers, they can be subsequently moved to memory as bytes, half-words, or doublewords. All
load and store instructions are byte-, half-word-, word-, or doubleword-addressable.

For more details on the C64x CPU functional units enhancements, see the following documents:

• TMS320C6000 CPU and Instruction Set Reference Guide (literature number SPRU189)

• TMS320C64x Technical Overview (literature number SPRU395)

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.L1

.S1

.M1

.D1

.D2

.M2

.S2

.L2

src1

long dst

8

8

src2

DA1 (Address)

ST1b (Store Data)

ST2a (Store Data)

Register

File A

(A0−A31)

8

8

8

8

dst

Data Path A

DA2 (Address)

Register

File B

(B0− B31)

LD2a (Load Data)

Data Path B

Control Register

File

ST2b (Store Data)

LD1b (Load Data)

8

8

2X

1X

ST1a (Store Data)

(A)

LD1a (Load Data)

LD2b (Load Data)

32 MSBs
32 LSBs

32 MSBs

32 LSBs

32 MSBs
32 LSBs

32 MSBs

32 LSBs

src2

src1

dst

long dst
long src

long src
long dst

dst

src1
src2

src1
src2

src2
src1

dst

src2

src1

dst

src2

long dst

src2
src1

dst

long dst

long dst
long src

long src
long dst

dst

dst

src2

src1

dst

(A)

(A)

(A)

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

A. For the .M functional units, the long dst is 32 MSBs and the dst is 32 LSBs.

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Figure 2-1. TMS320C64x™ CPU (DSP Core) Data Paths

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

2.2.1 CPU Core Registers

Table 2-2. L2 Cache Registers (C64x)

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

0184 0000 CCFG Cache configuration register

0184 0004 – 0184 0FFC – Reserved

0184 1000 EDMAWEIGHT L2 EDMA access control register

0184 1004 – 0184 1FFC – Reserved

0184 2000 L2ALLOC0 L2 allocation register 0
0184 2004 L2ALLOC1 L2 allocation register 1
0184 2008 L2ALLOC2 L2 allocation register 2

0184 200C L2ALLOC3 L2 allocation register 3

0184 2010 – 0184 3FFC – Reserved

0184 4000 L2WBAR L2 writeback base address register
0184 4004 L2WWC L2 writeback word count register
0184 4010 L2WIBAR L2 writeback invalidate base address register
0184 4014 L2WIWC L2 writeback invalidate word count register
0184 4018 L2IBAR L2 invalidate base address register

0184 401C L2IWC L2 invalidate word count register

0184 4020 L1PIBAR L1P invalidate base address register
0184 4024 L1PIWC L1P invalidate word count register
0184 4030 L1DWIBAR L1D writeback invalidate base address register
0184 4034 L1DWIWC L1D writeback invalidate word count register

0184 4038 – 0184 4044 – Reserved

0184 4048 L1DIBAR L1D invalidate base address register

0184 404C L1DIWC L1D invalidate word count register

0184 4050 – 0184 4FFC – Reserved

0184 5000 L2WB L2 writeback all register
0184 5004 L2WBINV L2 writeback invalidate all register

0184 5008 – 0184 7FFC – Reserved
0184 8000 – 0184 81FC Reserved

0184 8200 MAR128 Controls EMIFA CE0 range 8000 0000 – 80FF FFFF
0184 8204 MAR129 Controls EMIFA CE0 range 8100 0000 – 81FF FFFF
0184 8208 MAR130 Controls EMIFA CE0 range 8200 0000 – 82FF FFFF

0184 820C MAR131 Controls EMIFA CE0 range 8300 0000 – 83FF FFFF

0184 8210 MAR132 Controls EMIFA CE0 range 8400 0000 – 84FF FFFF
0184 8214 MAR133 Controls EMIFA CE0 range 8500 0000 – 85FF FFFF
0184 8218 MAR134 Controls EMIFA CE0 range 8600 0000 – 86FF FFFF

0184 821C MAR135 Controls EMIFA CE0 range 8700 0000 – 87FF FFFF

0184 8220 MAR136 Controls EMIFA CE0 range 8800 0000 – 88FF FFFF
0184 8224 MAR137 Controls EMIFA CE0 range 8900 0000 – 89FF FFFF
0184 8228 MAR138 Controls EMIFA CE0 range 8A00 0000 – 8AFF FFFF

0184 822C MAR139 Controls EMIFA CE0 range 8B00 0000 – 8BFF FFFF

0184 8230 MAR140 Controls EMIFA CE0 range 8C00 0000 – 8CFF FFFF
0184 8234 MAR141 Controls EMIFA CE0 range 8D00 0000 – 8DFF FFFF
0184 8238 MAR142 Controls EMIFA CE0 range 8E00 0000 – 8EFF FFFF

0184 823C MAR143 Controls EMIFA CE0 range 8F00 0000 – 8FFF FFFF

0184 8240 MAR144 Controls EMIFA CE1 range 9000 0000 – 90FF FFFF

MAR0 to
MAR127

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Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Table 2-2. L2 Cache Registers (C64x) (continued)

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

0184 8244 MAR145 Controls EMIFA CE1 range 9100 0000 – 91FF FFFF
0184 8248 MAR146 Controls EMIFA CE1 range 9200 0000 – 92FF FFFF

0184 824C MAR147 Controls EMIFA CE1 range 9300 0000 – 93FF FFFF

0184 8250 MAR148 Controls EMIFA CE1 range 9400 0000 – 94FF FFFF
0184 8254 MAR149 Controls EMIFA CE1 range 9500 0000 – 95FF FFFF
0184 8258 MAR150 Controls EMIFA CE1 range 9600 0000 – 96FF FFFF

0184 825C MAR151 Controls EMIFA CE1 range 9700 0000 – 97FF FFFF

0184 8260 MAR152 Controls EMIFA CE1 range 9800 0000 – 98FF FFFF
0184 8264 MAR153 Controls EMIFA CE1 range 9900 0000 – 99FF FFFF
0184 8268 MAR154 Controls EMIFA CE1 range 9A00 0000 – 9AFF FFFF

0184 826C MAR155 Controls EMIFA CE1 range 9B00 0000 – 9BFF FFFF

0184 8270 MAR156 Controls EMIFA CE1 range 9C00 0000 – 9CFF FFFF
0184 8274 MAR157 Controls EMIFA CE1 range 9D00 0000 – 9DFF FFFF
0184 8278 MAR158 Controls EMIFA CE1 range 9E00 0000 – 9EFF FFFF

0184 827C MAR159 Controls EMIFA CE1 range 9F00 0000 – 9FFF FFFF

0184 8280 MAR160 Controls EMIFA CE2 range A000 0000 – A0FF FFFF
0184 8284 MAR161 Controls EMIFA CE2 range A100 0000 – A1FF FFFF
0184 8288 MAR162 Controls EMIFA CE2 range A200 0000 – A2FF FFFF

0184 828C MAR163 Controls EMIFA CE2 range A300 0000 – A3FF FFFF

0184 8290 MAR164 Controls EMIFA CE2 range A400 0000 – A4FF FFFF
0184 8294 MAR165 Controls EMIFA CE2 range A500 0000 – A5FF FFFF

0184 8298 MAR166 Controls EMIFA CE2 range A600 0000 – A6FF FFFF
0184 829C MAR167 Controls EMIFA CE2 range A700 0000 – A7FF FFFF
0184 82A0 MAR168 Controls EMIFA CE2 range A800 0000 – A8FF FFFF
0184 82A4 MAR169 Controls EMIFA CE2 range A900 0000 – A9FF FFFF
0184 82A8 MAR170 Controls EMIFA CE2 range AA00 0000 – AAFF FFFF
0184 82AC MAR171 Controls EMIFA CE2 range AB00 0000 – ABFF FFFF
0184 82B0 MAR172 Controls EMIFA CE2 range AC00 0000 – ACFF FFFF
0184 82B4 MAR173 Controls EMIFA CE2 range AD00 0000 – ADFF FFFF
0184 82B8 MAR174 Controls EMIFA CE2 range AE00 0000 – AEFF FFFF
0184 82BC MAR175 Controls EMIFA CE2 range AF00 0000 – AFFF FFFF
0184 82C0 MAR176 Controls EMIFA CE3 range B000 0000 – B0FF FFFF
0184 82C4 MAR177 Controls EMIFA CE3 range B100 0000 – B1FF FFFF
0184 82C8 MAR178 Controls EMIFA CE3 range B200 0000 – B2FF FFFF
0184 82CC MAR179 Controls EMIFA CE3 range B300 0000 – B3FF FFFF
0184 82D0 MAR180 Controls EMIFA CE3 range B400 0000 – B4FF FFFF
0184 82D4 MAR181 Controls EMIFA CE3 range B500 0000 – B5FF FFFF
0184 82D8 MAR182 Controls EMIFA CE3 range B600 0000 – B6FF FFFF
0184 82DC MAR183 Controls EMIFA CE3 range B700 0000 – B7FF FFFF
0184 82E0 MAR184 Controls EMIFA CE3 range B800 0000 – B8FF FFFF
0184 82E4 MAR185 Controls EMIFA CE3 range B900 0000 – B9FF FFFF
0184 82E8 MAR186 Controls EMIFA CE3 range BA00 0000 – BAFF FFFF
0184 82EC MAR187 Controls EMIFA CE3 range BB00 0000 – BBFF FFFF
0184 82F0 MAR188 Controls EMIFA CE3 range BC00 0000 – BCFF FFFF
0184 82F4 MAR189 Controls EMIFA CE3 range BD00 0000 – BDFF FFFF
0184 82F8 MAR190 Controls EMIFA CE3 range BE00 0000 – BEFF FFFF
0184 82FC MAR191 Controls EMIFA CE3 range BF00 0000 – BFFF FFFF

TMS320DM642

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Table 2-2. L2 Cache Registers (C64x) (continued)

HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS

0184 8300 – 0184 83FC Reserved
0184 8400 – 0187 FFFF – Reserved

MAR192 to

MAR255

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2.3 Memory Map Summary

Table 2-3 shows the memory map address ranges of the DM642 device. Internal memory is always

located at address 0 and can be used as both program and data memory. The external memory address
ranges in the DM642 device begin at the hex address location 0x8000 0000 for EMIFA.

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Table 2-3. TMS320DM642 Memory Map Summary

MEMORY BLOCK DESCRIPTION HEX ADDRESS RANGE

Internal RAM (L2) 256K 0000 0000 – 0003 FFFF
Reserved 768K 0004 0000 – 000F FFFF
Reserved 23M 0010 0000 – 017F FFFF
External Memory Interface A (EMIFA) Registers 256K 0180 0000 – 0183 FFFF
L2 Registers 256K 0184 0000 – 0187 FFFF
HPI Registers 256K 0188 0000 – 018B FFFF
McBSP 0 Registers 256K 018C 0000 – 018F FFFF
McBSP 1 Registers 256K 0190 0000 – 0193 FFFF
Timer 0 Registers 256K 0194 0000 – 0197 FFFF
Timer 1 Registers 256K 0198 0000 – 019B FFFF
Interrupt Selector Registers 256K 019C 0000 – 019F FFFF
EDMA RAM and EDMA Registers 256K 01A0 0000 – 01A3 FFFF
Reserved 512K 01A4 0000 – 01AB FFFF
Timer 2 Registers 256K 01AC 0000 – 01AF FFFF
GP0 Registers 256K – 4K 01B0 0000 – 01B3 EFFF
Device Configuration Registers 4K 01B3 F000 – 01B3 FFFF
I2C0 Data and Control Registers 16K 01B4 0000 – 01B4 3FFF
Reserved 32K 01B4 4000 – 01B4 BFFF
McASP0 Control Registers 16K 01B4 C000 – 01B4 FFFF
Reserved 192K 01B5 0000 – 01B7 FFFF
Reserved 256K 01B8 0000 – 01BB FFFF
Emulation 256K 01BC 0000 – 01BF FFFF
PCI Registers 256K 01C0 0000 – 01C3 FFFF
VP0 Control 16K 01C4 0000 – 01C4 3FFF
VP1 Control 16K 01C4 4000 – 01C4 7FFF
VP2 Control 16K 01C4 8000 – 01C4 BFFF
VIC Control 16K 01C4 C000 – 01C4 FFFF
Reserved 192K 01C5 0000 – 01C7 FFFF
EMAC Control 4K 01C8 0000 – 01C8 0FFF
EMAC Wrapper 8K 01C8 1000 – 01C8 2FFF
EWRAP Registers 2K 01C8 3000 – 01C8 37FF
MDIO Control Registers 2K 01C8 3800 – 01C8 3FFF
Reserved 3.5M 01C8 4000 – 01FF FFFF
QDMA Registers 52 0200 0000 – 0200 0033
Reserved 736M – 52 0200 0034 – 2FFF FFFF
McBSP 0 Data 64M 3000 0000 – 33FF FFFF
McBSP 1 Data 64M 3400 0000 – 37FF FFFF
Reserved 64M 3800 0000 – 3BFF FFFF
McASP0 Data 1M 3C00 0000 – 3C0F FFFF
Reserved 64M – 1M 3C10 0000 – 3FFF FFFF
Reserved 832M 4000 0000 – 73FF FFFF

BLOCK SIZE

(BYTES)

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Table 2-3. TMS320DM642 Memory Map Summary (continued)

MEMORY BLOCK DESCRIPTION HEX ADDRESS RANGE

VP0 Channel A Data 32M 7400 0000 – 75FF FFFF
VP0 Channel B Data 32M 7600 0000 – 77FF FFFF
VP1 Channel A Data 32M 7800 0000 – 79FF FFFF
VP1 Channel B Data 32M 7A00 0000 – 7BFF FFFF
VP2 Channel A Data 32M 7C00 0000 – 7DFF FFFF
VP2 Channel B Data 32M 7E00 0000 – 7FFF FFFF
EMIFA CE0 256M 8000 0000 – 8FFF FFFF
EMIFA CE1 256M 9000 0000 – 9FFF FFFF
EMIFA CE2 256M A000 0000 – AFFF FFFF
EMIFA CE3 256M B000 0000 – BFFF FFFF
Reserved 1G C000 0000 – FFFF FFFF

BLOCK SIZE

(BYTES)

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2.3.1 L2 Architecture Expanded

0x0000 0000

011010001 111

0x0002 0000

000

L2MODE L2 Memory Block Base Address

0x0003 8000

0x0003 0000

0x0004 0000

32K Cache

(4 Way)

64K Cache (4 Way)

128K Cache (4 Way)

256K Cache (4 Way) [All]

256K SRAM (All)

224K SRAM

192K SRAM

128K SRAM

128K-Byte SRAM

64K-Byte RAM

32K-Byte RAM

0x0003 FFFF

32K-Byte RAM

Figure 2-2 shows the detail of the L2 architecture on the TMS320DM642 device. For more information on

the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x
Two-Level Internal Memory Reference Guide (literature number SPRU610).

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Figure 2-2. TMS320DM642 L2 Architecture Memory Configuration

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

2.4 Bootmode

The DM642 device resets using the active-low signal RESET. While RESET is low, the device is held in
reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics
and states of device pins during reset. The release of RESET starts the processor running with the
prescribed device configuration and boot mode.

The DM642 has three types of boot modes:

• Host boot
If host boot is selected, upon release of RESET, the CPU is internally "stalled" while the remainder of

the device is released. During this period, an external host can initialize the CPU's memory space as
necessary through the host interface, including internal configuration registers, such as those that
control the EMIF or other peripherals. For the DM642 device, the HPI peripheral is used for host boot if
PCI_EN = 0, and the PCI peripheral is used if PCI_EN = 1. Once the host is finished with all necessary
initialization, it must set the DSPINT bit in the HPIC register to complete the boot process. This
transition causes the boot configuration logic to bring the CPU out of the "stalled" state. The CPU then
begins execution from address 0. The DSPINT condition is not latched by the CPU, because it occurs
while the CPU is still internally "stalled". Also, DSPINT brings the CPU out of the "stalled" state only if
the host boot process is selected. All memory may be written to and read by the host. This allows for
the host to verify what it sends to the DSP if required. After the CPU is out of the "stalled" state, the
CPU needs to clear the DSPINT, otherwise, no more DSPINTs can be received.

• EMIF boot (using default ROM timings)
Upon the release of RESET, the 1K-Byte ROM code located in the beginning of CE1 is copied to

address 0 by the EDMA using the default ROM timings, while the CPU is internally "stalled". The data
should be stored in the endian format that the system is using. In this case, the EMIF automatically
assembles consecutive 8-bit bytes to form the 32-bit instruction words to be copied. The transfer is
automatically done by the EDMA as a single-frame block transfer from the ROM to address 0. After
completion of the block transfer, the CPU is released from the "stalled" state and starts running from
address 0.

• No boot
With no boot, the CPU begins direct execution from the memory located at address 0. Note: operation

is undefined if invalid code is located at address 0.

2.5 Pin Assignments

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2.5.1 Pin Map

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

13121110987654321

13121110987654321

CLKMODE1

CLKMODE0

PLLV

RESET

VDAC/

GP0[8]/

PCI66

HCNTL1/

PDEVSEL

HCS/

PPERR

HAS/

PPAR

HDS1/

PSERR

HDS2/

PCBE1

HD15/
AD15

HD14/

AD14

HD13/
AD13

HD12/

AD12

HD11/

AD11

HD10/

AD10

HD9/

AD9

HD8/

AD8

HD7/

AD7

HD6/

AD6

HD4/

AD4

HD3/

AD3

HD2/

AD2

HD1/

AD1

HD0/

AD0

PCBE0

XSP_CS

XSP_CLK/

MDCLK

XSP_DI

XSP_DO/

MDIO

STCLK

VP1D[18]/

AXR0[6]

VP1D[19]/

AXR0[7]

VP1D[15]/

AXR0[3]

VP1D[17]/

AXR0[5]

VP0D[19]/
AHCLKX0

VP1D[16]/

AXR0[4]

VP1D[14]/

AXR0[2]

VP1D[13]/

AXR0[1]

VP1D[12]/

AXR0[0]

VP1D[11]

VP1D[10]

VP1D[9]

VP1D[8]/

CLKR1

VP1D[7]/

FSR1

VP1D[6]/

DR1

VP1D[5]/

CLKS1

VP1D[4]/

DX1

VP1D[3]/

FSX1

VP1D[2]/

CLKX1

VP1D[1]

VP1D[0] VP1CLK1VP1CLK0

VP1CTL2

VP1CTL1

VP1CTL0

VP0D[17]/

ACLKX0

VP0D[16]/

AMUTE0

VP0D[15]/

AMUTEIN0

VP0CLK1

VP0D[18]/

AFSX0

RSV

RSV

RSV

RSV

RSV

RSV

RSV

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

CLKIN V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

VSSV

SS

V

SS

V

SS

HD5/

AD5

HCNTL0/

PSTOP

V

SS

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Figure 2-3 through Figure 2-6 show the DM642 pin assignments in four quadrants (A, B, C, and D).

Figure 2-3. DM642 Pin Map [Quadrant A]

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14 15 16 17 18 19 20 21 22 23 24 25 26

AF

AE

AD

AC

AB

AA

Y

W

V

U

T

R

P

ABE7 ABE6

ABE5 ABE4

ABUSREQ

ASOE3

AEA22

AEA21 AEA20 AEA19AEA18

AEA17 AEA16 AEA15

AEA14 AEA13

AEA12 AEA11

AEA10 AEA9 AEA8

AED63AED62

AED61

AED60AED59

AED58AED58

AED57

AED56

AED55

AED54

AED53

AED52

AED51

AED50

AED49

AED48

AED47

AED46AED45 AED44AED43

AED42AED41 AED40AED39

AED38 AED37AED36

AED35AED34

AED33 AED32

VP0D[14]/
AHCLKR0

VP0D[13]/

AFSR0

VP0D[12]/

ACLKR0

VP0D[11]

VP0D[10]

VP0D[9]

VP0D[8]/

CLKR0

VP0D[7]/

FSR0

VP0D[6]/

DR0

VP0D[5]/

CLKS0

VP0D[4]/

DX0

VP0D[3]/

FSX0

VP0D[2]/

CLKX0

VP0D[1]

VP0D[0]VP0D[0]VP0CLK0

VP0CTL2

VP0CTL1

VP0CTL0

DV

DD

DV

DD

DV

DD

DVDDDV

DD

AHOLDDV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DVDDDV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

VSSV

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

CV

DD

14 15 16 17 18 19 20 21 22 23 24 25 26

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Figure 2-4. DM642 Pin Map [Quadrant B]

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N

M

L

K

J

H

G

F

E

D

C

B

A

CLKOUT6/

GP0[2]

NMI

GP0[7]/

EXT_INT7

GP0[6]/

EXT_INT6

GP0[5]/

EXT_INT5

GP0[4]/

EXT_INT4

GP0[15]/

PRST

GP0[14]/

PCLK

GP0[13]/

PINTA

GP0[12]/

PGNT

GP0[11]/

PREQ

GP0[10]/

PCBE3

GP0[9]/
PIDSEL

GP0[3]/

PCIEEAI

GP0[0]

PCI_EN

HINT/

PFRAME

HHWIL/
PTRDY

HR/W/

PCBE2

HRDY/
PIRDY

HD31/

AD31/

MRCLK

HD30/
AD30/
MCRS

HD29/
AD29/

MRXER

HD28/
AD28/

MRXDV

HD27/
AD27/

MRXD3

HD26/
AD26/

MRXD2

HD25/

AD25/

MRXD1

HD24/
AD24/

MRXD0

HD23/

AD23

13121110987654321

HD22/
AD22/

MTCLK

HD21/
AD21/
MCOL

HD20/
AD20/

MTXEN

HD19/
AD19/

MTXD3

HD18/
AD18/

MTXD2

HD17/
AD17/

MTXD1

HD16/
AD16/

MTXD0

VP2D[19]VP2D[18]

VP2D[16]

VP2D[15]

VP2D[14]

VP2D[12]

VP2D[10]

VP2D[8]

VP2D[6]

VP2D[4]VP2D[4]

VP2D[2]

VP2D[0]

VP2CLK0 VP2CLK1

VP2CTL2

TOUT1/

LENDIAN

TINP1

TOUT0/

MAC_EN

TINP0

SCL0

RSV

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DVDDDV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

VSSV

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

SDA0 DV

DD

CLKOUT4/

GP0[1]

VP2CTL1 VP2D[1] VP2D[5] VP2D[9] VP2D[13] VP2D[17]

VP2CTL0 VP2D[3] VP2D[7] VP2D[11]

13121110987654321

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

TMS320DM642

Figure 2-5. DM642 Pin Map [Quadrant C]

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N

M

L

K

J

H

G

F

E

D

C

B

A

14 15 16 17 18 19 20 21 22 23 24 25 26

14 15 16 17 18 19 20 21 22 23 24 25 26

TMS

TDO

TDITCK

TRST EMU11

EMU10

EMU9

EMU8

EMU7

EMU6

EMU5

EMU4

EMU3

EMU2

EMU1

EMU0

ACE3

ACE2 ACE1 ACE0

ABE3 ABE2

ABE1 ABE0

APDT

AHOLDA

AECLKIN

AAOE/

ASDRAS/

ASOE

AARDY

AECLKOUT1

AARE/

ASDCAS/

ASADS/

ASRE

AAWE/

ASDWE/

ASWE

ASDCKE

AEA7 AEA6 AEA5

AEA4AEA4 AEA3

AED31AED30

AED29AED28

AED27 AED26

AED25 AED24AED23 AED22

AED21 AED20AED19 AED18

AED17 AED16

AED15

AED14

AED13

AED12

AED11

AED10

AED9

AED8

AED7

AED6 AED4

AED3

AED5

AED2

AED1

AED0

RSV

DV

DD

V

SS

V

SS

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

V

SS

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DV

DD

DVDDDV

DD

DV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

CV

DD

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

V

SS

AECLKOUT2

CV

DD

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Figure 2-6. DM642 Pin Map [Quadrant D]

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2.5.2 Signal Groups Description

TRST

GP0[7]/EXT_INT7

(B)

IEEE Standard

1149.1

(JTAG)

Emulation

Reserved

Reset and
Interrupts

Control/Status

TDI

TDO

TMS

TCK

EMU0
EMU1

NMI

GP0[6]/EXT_INT6

(B)

GP0[5]/EXT_INT5

(B)

GP0[4]/EXT_INT4

(B)

RESET

RSV07
RSV06

Clock/PLL

CLKIN

CLKMODE1
CLKMODE0

PLLV

EMU2
EMU3
EMU4
EMU5

GP0

General-Purpose Input/Output 0 (GP0) Port

GP0[7]/EXT_INT7

(B)

GP0[6]/EXT_INT6

(B)

GP0[5]/EXT_INT5

(B)

GP0[4]/EXT_INT4

(B)

GP0[3]/PCIEEAI
CLKOUT6/GP0[2]

(A)

CLKOUT4/GP0[1]

(A)

GP0[0]

CLKOUT6/GP0[2]

(A)

CLKOUT4/GP0[1]

(A)

EMU6
EMU7
EMU8
EMU9

EMU10

GP0[15]/PRST

(C)

GP0[14]/PCLK

(C)

GP0[13]/PINTA

(C)

GP0[12]/PGNT

(C)

GP0[11]/PREQ

(C)

GP0[10]/PCBE3

(C)

GP0[9]/PIDSEL

(C)

VDAC/GP0[8]/PCI66

(C)

RSV08

EMU11

RSV04
RSV03

RSV05

Peripheral

Control/Status

PCI_EN
TOUT0/MAC_EN

RSV01
RSV00

RSV02

TMS320DM642

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Submit Documentation Feedback Device Overview 21

A. These pins are muxed with the GP0 pins and by default these signals function as clocks (CLKOUT4 or CLKOUT6).

To use these muxed pins as GPIO signals, the appropriate GPIO register bits (GPxEN and GPxDIR) must be properly
enabled and configured. For more details, see the Device Configurations section of this data sheet.

B. These pins are GP0 pins that can also function as external interrupt sources (EXT_INT[7:4]). Default after reset is

EXT_INTx or GPIO as input-only.

C. These GP0 pins are muxed with the PCI peripheral pins and by default these signals are set up to no function with

both the GPIO and PCI pin functions disabled. For more details on these muxed pins, see the Device Configurations
section of this data sheet.

Figure 2-7. CPU and Peripheral Signals

www.ti.com

ACE3

AECLKOUT1

AED[63:0]

ACE2

ACE1
ACE0

AEA[22:3]

ABE7
ABE6

ABE5

ABE4

AARDY

Data

Memory Map

Space Select

Address

Byte Enables

64

20

External

Memory I/F

Control

EMIFA (64-bit)

AECLKIN

AHOLD
AHOLDA
ABUSREQ

Bus

Arbitration

AARE/ASDCAS/ASADS/ASRE

ASDCKE

AECLKOUT2

ASOE3

ABE3
ABE2
ABE1
ABE0

AAOE/ASDRAS/ASOE
AAWE/ASDWE/ASWE

APDT

VDAC/GP0[8]/PCI66

VCXO Interpolated

Control Port (VIC)

Data

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Figure 2-8. EMIFA/VIC Peripheral Signals

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HHWIL/PTRDY

HCNTL0/PSTOP

HCNTL1/PDEVSEL

Data

Register Select

Half-Word

Select

Control

HPI

(A)

(Host-Port Interface)

32

HD[15:0]/AD[15:0]

HAS/PPAR
HR/W/PCBE2

HCS/PPERR
HDS1/PSERR
HDS2/PCBE1
HRDY/PIRDY
HINT/PFRAME

(HPI16 ONL Y)

HD[15:0]/AD[15:0]

HR/W/PCBE2
HDS2/PCBE1

PCBE0

GP0[12]/PGNT
GP0[11]/PREQ

GP0[14]/PCLK

HINT/PFRAME
GP0[13]/PINTA

Data/Address

Arbitration

32

Clock

Control

PCI Interface

(B)

HAS/PPAR
GP0[15]/PRST
HRDY/PIRDY
HCNTL0/PSTOP
HHWIL/PTRDY

GP0[10]/PCBE3

GP0[9]/PIDSEL

HCNTL1/PDEVSEL

HDS1/PSERR

Error

Command

Byte Enable

Serial

EEPROM

XSP_DO/MDIO
XSP_CS
XSP_CLK/MDCLK
XSP_DI

HCS/PPERR

HD[31:16]/AD[31:16]

(C)

HD[31:16]/AD[31:16]

(C)

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

TMS320DM642

A. These HPI pins are muxed with the PCI peripheral. By default, these signals function as HPI. For more details on

these muxed pins, see the Device Configurations section of this data sheet.

B. These PCI pins (excluding PCBE0 and XSP_CS) are muxed with the HPI or MDIO or GP0 peripherals. By default,

these signals function as HPI and no function, respectively. For more details on these muxed pins, see the Device
Configurations section of this data sheet.

C. These HPI/PCI data pins (HD[31:16/AD[31:16]) are muxed with the EMAC peripheral. By default, these pins function

as HPI. For more details on the EMAC pin functions, see the Ethernet MAC (EMAC) peripheral signals section and
the terminal functions table portions of this data sheet.

Figure 2-9. HPI/PCI Peripheral Signals

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McBSPs

(Multichannel Buffered

Serial Ports)

VP0D[2]/CLKX0

(A)

VP0D[3]/FSX0

(A)

VP0D[4]/DX0

(A)

VP0D[8]/CLKR0

(A)

VP0D[7]/FSR0

(A)

VP0D[6]/DR0

(A)

VP0D[5]/CLKS0

(A)

McBSP0

VP1D[2]/CLKX1

(A)

VP1D[3]/FSX1

(A)

VP1D[4]/DX1

(A)

VP1D[8]/CLKR1

(A)

VP1D[7]/FSR1

(A)

VP1D[6]/DR1

(A)

VP1D[5]/CLKS1

(A)

McBSP1

TOUT0/MACEN

Timers

TINP0

TOUT1/LENDIAN

Timer 1

TINP1

Timer 2

Timer 0

SCL0

I2C0

I2C0

SDA0

Transmit

Receive

Clock

Transmit

Receive

Clock

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

A. These McBSP1 and McBSP0 pins are muxed with the Video Port 1 (VP1) and Video Port 0 (VP0) peripherals,

respectively. By default, these signals function as VP1 and VP0, respectively. For more details on these muxed pins,
see the Device Configurations section of this data sheet.

Figure 2-10. McBSP/Timer/I2C0 Peripheral Signals

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HD21/AD21/MCOL

(A)

HD28/AD28/MRXDV

(A)

HD29/AD29/MRXER

(A)

HD20/AD20/MTXEN

(A)

Ethernet MAC (EMAC)

and MDIO

XSP_DO/MDIO

(B)

XSP_CLK/MDCLK

(B)

MDIO

Clock

HD16/AD16/MTXD0

(A)

HD17/AD17/MTXD1

(A)

HD18/AD18/MTXD2

(A)

HD25/AD25/MRXD1

(A)

HD26/AD26/MRXD2

(A)

HD27/AD27/MRXD3

(A)

EMAC

Transmit

HD24/AD24/MRXD0

(A)

HD19/AD19/MTXD3

(A)

Clocks

HD31/AD31/MRCLK

(A)

HD22/AD22/MTCLK

(A)

HD30/AD30/MCRS

(A)

Error Detect

and Control

Input/Output

Receive

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

TMS320DM642

A. These EMAC pins are muxed with the upper data pins of the HPI or PCI peripherals. By default, these signals

function as HPI. For more details on these muxed pins, see the Device Configurations section of this data sheet.

B. These MDIO pins are muxed with the PCI peripherals. By default, these signals function as PCI. For more details on

these muxed pins, see the Device Configurations section of this data sheet.

Figure 2-11. EMAC/MDIO Peripheral Signals

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VP0D[10]
VP0D[11]
VP0D[12]/ACLKR0
VP0D[13]/AFSR0
VP0D[14]/AHCLKR0
VP0D[15]/AMUTEIN0
VP0D[16]/AMUTE0
VP0D[17]/ACLKX0

VP0D[0]

VP0D[1]

VP0D[2]/CLKX0

VP0D[3]/FSX0

VP0D[4]/DX0

VP0D[5]/CLKS0

VP0D[6]/DR0

VP0D[7]/FSR0

VP0D[8]/CLKR0

VP0D[9]

VP0D[18]/AFSX0
VP0D[19]/AHCLKX0

Capture/Display

Buffer

(2560 Bytes)

VP0CLK0

VP0CLK1

VP0CTL0
VP0CTL1

VP0CTL2

Timing and

Control Logic

Video Port 0 (VP0)

Channel B

(B)

Channel A

(A)

Capture/Display

Buffer

(2560 Bytes)

Channel B uses only
the VP0D[19:10]
bidirectional pins

STCLK

(C)

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

A. Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656

(8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit), and TSI (8-bit) capture modes.

B. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW

Video data with Channel A.

C. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).

Figure 2-12. Video Port 0 Peripheral Signals

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VP1D[10]
VP1D[11]
VP1D[12]/AXR0[0]
VP1D[13]/AXR0[1]
VP1D[14]/AXR0[2]
VP1D[15]/AXR0[3]
VP1D[16]/AXR0[4]
VP1D[17]/AXR0[5]

VP1D[0]
VP1D[1]

VP1D[2]/CLKX1

VP1D[3]/FSX1

VP1D[4]/DX1

VP1D[5]/CLKS1

VP1D[6]/DR1

VP1D[7]/FSR1

VP1D[8]/CLKR1

VP1D[9]

VP1D[18]/AXR0[6]
VP1D[19]/AXR0[7]

Capture/Display

Buffer

(2560 Bytes)

VP1CLK0

VP1CLK1

VP1CTL0
VP1CTL1

VP1CTL2

Timing and

Control Logic

Video Port 1 (VP1)

Channel B

(B)

Channel A

(A)

Capture/Display

Buffer

(2560 Bytes)

Channel B uses only
the VP1D[19:10]
bidirectional pins

STCLK

(C)

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

TMS320DM642

A. Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656

(8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit), and TSI (8-bit) capture modes.

B. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW

Video data with Channel A.

C. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).

Figure 2-13. Video Port 1 Peripheral Signals

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VP2D[10]
VP2D[11]
VP2D[12]
VP2D[13]
VP2D[14]
VP2D[15]
VP2D[16]
VP2D[17]

VP2D[0]
VP2D[1]
VP2D[2]
VP2D[3]
VP2D[4]
VP2D[5]
VP2D[6]
VP2D[7]
VP2D[8]
VP2D[9]

VP2D[18]
VP2D[19]

Capture/Display

Buffer

(2560 Bytes)

VP2CLK0
VP2CLK1

VP2CTL0
VP2CTL1
VP2CTL2

Timing and

Control Logic

Video Port 2 (VP2)

Channel B

(B)

Channel A

(A)

Capture/Display

Buffer

(2560 Bytes)

Channel B uses only
the VP2D[19:10]
bidirectional pins

STCLK

(C)

TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

A. Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656

(8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) and TSI (8-bit) capture modes.

B. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW

Video data with Channel A.

C. The same STCLK signal is used for all three video ports (VP0, VP1, and VP2).

Figure 2-14. Video Port 2 Peripheral Signals

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VP1D[19]/AXR0[7]

McASP0

(Multichannel Audio Serial Port 0)

VP1D[18]/AXR0[6]

VP0D[17]/ACLKX0
VP0D[19]/AHCLKX0

Transmit

Clock

Generator

VP0D[15]/AMUTEIN0

Auto Mute

Logic

VP0D[16]/AMUTE0

VP0D[18]/AFSX0

Transmit

Frame Sync

VP0D[13]/AFSR0

Receive Frame

Sync

VP1D[17]/AXR0[5]

VP1D[16]/AXR0[4]

VP0D[12]/ACLKR0

VP0D[14]/AHCLKR0

Receive Clock

Generator

VP1D[15]/AXR0[3]

VP1D[14]/AXR0[2]

VP1D[13]/AXR0[1]

VP1D[12]/AXR0[0]

8-Serial Ports

Flexible

Partitioning

Tx, Rx, OFF

Transmit

Clock Check

Circuit

Receive Clock

Check Circuit

Error Detect

(A)

(Transmit/Receive Data Pins)(Transmit/Receive Data Pins)

(Receive Bit Clock)

(Transmit Bit Clock)

(Receive Master Clock) (Transmit Master Clock)

(Receive Frame Sync or

Left/Right Clock)

(Transmit Frame Sync or
Left/Right Clock)

NOTES: On multiplexed pins, bolded text denotes the active function of the pin for that particular peripheral module.

Bolded and Italicized text within parentheses denotes the function of the pins in an audio system.

Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

TMS320DM642

A. The McASPs' Error Detect function detects underruns, overruns, early/late frame syncs, DMA errors, and external

mute input.

Figure 2-15. McASP0 Peripheral Signals

2.5.3 Terminal Functions

Table 2-4 , the terminal functions table, identifies the external signal names, the associated pin (ball)

numbers along with the mechanical package designator, the pin type (I, O/Z, or I/O/Z), whether the pin
has any internal pullup/pulldown resistors and a functional pin description. For more detailed information
on device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see
the Device Configurations section of this data sheet.

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TMS320DM642
Video/Imaging Fixed-Point Digital Signal Processor

SPRS200L – JULY 2002 – REVISED JANUARY 2007

Table 2-4. Terminal Functions

SIGNAL

NAME NO.

TYPE

IPD/

(1)

(2)

IPU

DESCRIPTION

CLOCK/PLL CONFIGURATION

CLKIN AC2 I Clock Input. This clock is the input to the on-chip PLL.
CLKOUT4/GP0[1]

CLKOUT6/GP0[2]

(3)

(3)

D6 I/O/Z IPU

C6 I/O/Z IPU

Clock output at 1/4 of the device speed ( O/Z) [default] or this pin can be
programmed as a GP0 1 pin ( I/O/Z).

Clock output at 1/6 of the device speed ( O/Z) [default] or this pin can be
programmed as a GP0 2 pin ( I/O/Z).

CLKMODE1 AE4 I IPD Clock mode select

• Selects whether the CPU clock frequency = input clock frequency x1

CLKMODE0 AA2 I IPD

(Bypass), x6, or x12.
For more details on the CLKMODE pins and the PLL multiply factors, see

the Clock PLL section of this data sheet.

(4)

PLLV

V6 A

(1)

PLL voltage supply

JTAG EMULATION

TMS E15 I IPU JTAG test-port mode select
TDO B18 O/Z IPU JTAG test-port data out
TDI A18 I IPU JTAG test-port data in
TCK A16 I IPU JTAG test-port clock

TRST D14 I IPD

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

JTAG compatibility statement portion of this data sheet.
EMU11 D17 I/O/Z IPU Emulation pin 11. Reserved for future use, leave unconnected.
EMU10 C17 I/O/Z IPU Emulation pin 10. Reserved for future use, leave unconnected.
EMU9 B17 I/O/Z IPU Emulation pin 9. Reserved for future use, leave unconnected.
EMU8 D16 I/O/Z IPU Emulation pin 8. Reserved for future use, leave unconnected.
EMU7 A17 I/O/Z IPU Emulation pin 7. Reserved for future use, leave unconnected.
EMU6 C16 I/O/Z IPU Emulation pin 6. Reserved for future use, leave unconnected.
EMU5 B16 I/O/Z IPU Emulation pin 5. Reserved for future use, leave unconnected.
EMU4 D15 I/O/Z IPU Emulation pin 4. Reserved for future use, leave unconnected.
EMU3 C15 I/O/Z IPU Emulation pin 3. Reserved for future use, leave unconnected.
EMU2 B15 I/O/Z IPU Emulation pin 2. Reserved for future use, leave unconnected.
EMU1 C14 I/O/Z IPU Emulation pin 1
EMU0 A15 I/O/Z IPU Emulation pin 0

(5)
(5)

RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS

RESET P4 I Device reset

Nonmaskable interrupt, edge-driven (rising edge)
NMI B4 I IPD

Note: Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the

NMI pin is not used, it is recommended that the NMI pin be grounded versus

relying on the IPD.
GP0[7]/EXT_INT7 E1 I/O/Z IPU General-purpose input/output (GPIO) pins ( I/O/Z) or external interrupts ( input
GP0[6]/EXT_INT6 F2 I/O/Z IPU
GP0[5]/EXT_INT5 F3 I/O/Z IPU

GP0[4]/EXT_INT4 F4 I/O/Z IPU

only). The default after reset setting is GPIO enabled as input-only.

• When these pins function as External Interrupts [by selecting the
corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven
and the polarity can be independently selected via the External Interrupt
Polarity Register bits (EXTPOL.[3:0]).

(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k Ω IPD or IPU resistor. To pull up a signal to the

opposite supply rail, a 1-k Ω resistor should be used.)
(3) These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.
(4) PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.
(5) The EMU0 and EMU1 pins are internally pulled up with 30-k Ω resistors; therefore, for emulation and normal operation, no external

pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated

1-k Ω resistor.

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