Texas Instruments LV70036DSER, TLV70012DCKR, TLV70012DDCR, TLV70012DSER, TLV70013DDCR Schematic [ru]

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TLV700xx

GND

IN OUT

OUT

Off

OUT

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SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

TLV700 200-mA, Low-IQ, Low-Dropout Regulator for Portable Devices

1 Features 3 Description

• Very Low Dropout: – 43 mV at I – 85 mV at I – 175 mV at I

= 50 mA, V

OUT

= 100 mA, V

OUT

= 200 mA, V

OUT

= 2.8 V

= 2.35 V

OUT

• 2% Accuracy

• Low IQ: 31 μA

• Available in Fixed-Output Voltages from 1.2 V to

4.8 V

• High PSRR: 68 dB at 1 kHz

• Stable With Effective Capacitance of 0.1 μF

(1)

• Thermal Shutdown and Overcurrent Protection

• Available in 1.5-mm × 1.5-mm SON-6, SOT23-5, and SC-70 Packages

(1)

See the Input and Output Capacitor Requirements.

2 Applications

• Wireless Handsets

• Smart Phones, PDAs

• ZigBee®Networks

• Bluetooth®Devices

• Li-Ion Operated Handheld Products

• WLAN and Other PC Add-on Cards

The TLV700 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision bandgap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. All device versions have thermal shutdown and current limit for safety.

Furthermore, these devices are stable with an effective output capacitance of only 0.1 μF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices regulate to specified accuracy with no output load.

The TLV700 series of LDOs are available in 1.5-mm × 1.5-mm SON-6, SOT-5, and SC70 packages.

Device Information

PART NUMBER PACKAGE BODY SIZE (NOM)

TL700xx SOT (5) 2.90 mm × 1.60 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

TLV700

(1)

SC70 (5) 2.00 mm × 1.25 mm

WSON (6) 1.50 mm × 1.50 mm

Typical Application Circuit

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

www.ti.com

1 Features.................................................................. 1 8 Application and Implementation........................ 13

2 Applications ........................................................... 1

3 Description ............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 4

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Typical Characteristics.............................................. 7

7 Detailed Description ............................................ 11

7.1 Overview................................................................. 11

7.2 Functional Block Diagram....................................... 11

7.3 Feature Description................................................. 11

7.4 Device Functional Modes........................................ 12

8.1 Application Information............................................ 13

8.2 Typical Application .................................................. 13

9 Power Supply Recommendations...................... 14

10 Layout................................................................... 15

10.1 Layout Guidelines ................................................. 15

10.2 Layout Examples................................................... 15

10.3 Thermal Protection................................................ 15

10.4 Power Dissipation ................................................. 16

11 Device and Documentation Support................. 17

11.1 Device Support .................................................... 17

11.2 Documentation Support ........................................ 17

11.3 Trademarks........................................................... 17

11.4 Electrostatic Discharge Caution............................ 17

11.5 Glossary................................................................ 17

12 Mechanical, Packaging, and Orderable

Information........................................................... 18

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (October 2012) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section ................................................................................................. 1

• Deleted Applications bullet for MP3 Players .......................................................................................................................... 1

• Changed front-page graphic .................................................................................................................................................. 1

• Changed Pin Configuration and Functions section; updated table format ............................................................................ 4

• Changed "free-air temperature" to "junction temperature" in Absolute Maximum Ratings condition statement.................... 5

• Deleted Dissipation Ratings table .......................................................................................................................................... 5

• Changed Thermal Information table; updated thermal resistance values for all packages ................................................... 5

Changes from Revision C (July 2011) to Revision D Page

• Updated Figure 5.................................................................................................................................................................... 7

Changes from Revision B (December, 2010) to Revision C Page

• Added footnote 2 to Absolute Maximum Ratings table .......................................................................................................... 5

• Changed output current limit typical and maximum specifications......................................................................................... 6

• Deleted previous Figure 12, Current Limit vs Input Voltage typical characteristic................................................................. 7

Changes from Revision A (April, 2010) to Revision B Page

• Removed TLV701xx device references throughout document .............................................................................................. 1

• Changed minimum output voltage available from 0.7 V to 1.2 V........................................................................................... 1

• Added footnote (1).................................................................................................................................................................. 1

• Deleted V

< 1 V specification............................................................................................................................................ 6

OUT

• Deleted Active pulldown resistance parameter...................................................................................................................... 6

Product Folder Links: TLV700

TLV700

www.ti.com

• Changed Figure 4 title ............................................................................................................................................................ 7

• Changed Figure 5 title ............................................................................................................................................................ 7

• Removed TLV701xx block diagram...................................................................................................................................... 11

• Revised Shutdown section................................................................................................................................................... 11

• Updated Application Information section to reflect minimum output voltage availability of 1.2 V ........................................ 13

• Deleted references to TLV701xx throughout Application Information.................................................................................. 13

• Changed footnote 2 for Ordering Information table to reflect minimum output voltage of 1.2 V ......................................... 17

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

Product Folder Links: TLV700

OUT

N/C

(1)

GND

OUT

N/C

(1)

GND

3 4

N/C

(1)

N/C

(1)

GND

OUT

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

5 Pin Configuration and Functions

www.ti.com

DSE Package

6-Pin WSON

Top View

DCK Package

5-Pin SC70

Top View

DDC Package

5-Pin SOT

Top View

(1) No connection.

Pin Functions

NAME WSON SC70 SOT

IN 1 1 1 I to assure stability and good transient performance. See Input and Output

GND 2 2 2 — Ground pin

EN 6 3 3 I puts the regulator into shutdown mode and reduces operating current to 1 μA,

NC 4, 5 4 4 — No connection. This pin can be tied to ground to improve thermal dissipation.

OUT 3 5 5 O pin to ground to assure stability. See Input and Output Capacitor Requirements for

I/O DESCRIPTION

Input pin. A small, 1-μF ceramic capacitor is recommended from this pin to ground

Capacitor Requirements for more details.

Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V nominal.

Regulated output voltage pin. A small, 1-μF ceramic capacitor is needed from this more details.

Product Folder Links: TLV700

TLV700

www.ti.com

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

6 Specifications

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)

Voltage V

Maximum output current I

EN OUT

OUT

Output short-circuit duration Indefinite

Temperature °C

Operating junction, T Storage, T

stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) VENabsolute maximum rating is VIN+ 0.3 V or 6 V, whichever is less.

6.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(ESD)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Electrostatic discharge V

Charged device model (CDM), per JEDEC specification JESD22-C101,

(2)

all pins

(1)

MIN MAX UNIT

–0.3 6 –0.3 6

(2)

–0.3 6

Internally limited

–55 150 –55 150

VALUE UNIT

(1)

±2000

±500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

V V I

OUT

IN OUT

2 5.5 V

1.2 4.8 V 0 200 mA

6.4 Thermal Information

TLV700

THERMAL METRIC

θJA

θJC(top)

θJB

θJC(bot)

Junction-to-ambient thermal resistance 307.6 235.9 321.3 Junction-to-case (top) thermal resistance 79.1 61.9 207.9 Junction-to-board thermal resistance 93.7 54 281.5 Junction-to-top characterization parameter 1.3 0.8 42.4 Junction-to-board characterization parameter 92.8 53.4 284.8 Junction-to-case (bottom) thermal resistance n/a n/a 142.3

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

(1)

DCK [SC70] DDC [SOT] DSE [WSON] UNIT

5 PINS 5 PINS 6 PINS

°C/W

Product Folder Links: TLV700

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

www.ti.com

6.5 Electrical Characteristics

At VIN= V

OUT(nom)

unless otherwise noted. Typical values are at TJ= 25°C.

OUT

ΔV

OUT(ΔVIN)

ΔV

OUT(ΔIOUT)

GND

SHDN

PSRR Power-supply rejection ratio 68 dB

STR

EN(high)

EN(low)

UVLO Undervoltage lockout VINrising 1.9 V

(1) VDOis measured for devices with V (2) Start-up time = time from EN assertion to 0.98 × V

+ 0.3 V or 2 V (whichever is greater); I

= 10 mA, VEN= 0.9 V, C

OUT

= 1 μF, and TJ= –40°C to +125°C,

OUT

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Input voltage range 2 5.5 V DC output accuracy –40°C ≤ TJ≤ +125°C –2% 2%

Line regulation 1 5 mV

OUT(nom)

OUT

Load regulation 0 mA ≤ I

VIN= 0.98 × V V

OUT

Dropout voltage

(1)

VIN= 0.98 × V V

OUT

VIN= 0.98 × V V

OUT

Output current limit V

Ground pin current μA

Ground pin current (shutdown)

OUT

VEN≤ 0.4 V, VIN= 2 V 400 nA VEN≤ 0.4 V, 2 V ≤ VIN≤ 4.5 V 1 2 μA VIN= 2.3 V, V

OUT

Output noise voltage 48 μV Start-up time

(2)

BW = 100 Hz to 100 kHz, VIN= 2.3 V, V

OUT

Enable pin high (enabled) 0.9 V

+ 0.3 V ≤ VIN≤ 5.5 V,

= 10 mA

≤ 200 mA 1 15 mV

OUT

, I

OUT

= 50 mA,

= 100 mA,

= 200 mA,

85 mV

175 250

220 860 mA

= 2.8 V

= 2.35 V = 0.9 × V

OUT(nom)

= 0 mA 31 55 = 200 mA, VIN= V

= 1.8 V,

= 1 μF, I

OUT

= 1.8 V, I

OUT

= 200 mA 100 μs

OUT

= 10 mA, f = 1 kHz

+ 0.5 V 270

OUT

= 10 mA

OUT

Enable pin low (disabled) 0 0.4 V Enable pin current VIN= VEN= 5.5 V 0.04 0.5 μA

Thermal shutdown temperature °C

Shutdown, temperature increasing 160 Reset, temperature decreasing 140

Operating junction temperature –40 125 °C

OUT(nom)

≥ 2.35 V.

OUT(nom)

RMS

Product Folder Links: TLV700

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

OutputVoltage(V)

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature( C)

I =200mA

I =10mA

I =150mA

OUT

0 30 60 90 120 150 180 210

Output Current (mA)

180

160

140

120

100

Dropout Voltage (mV)

+125 C

+85 C +25 C

40 C-

° ° ° °

0 40 60 100 120 140 180 200

OutputCurrent(mA)

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

OutputVoltage(V)

+125 C

+85 C +25 C

40 C-

° ° ° °

20 80 160

250

200

150

100

DropoutVoltage(mV)

2.25 2.75 3.25 3.75 4.25

4.75

InputVoltage(V)

+125 C

+85 C +25 C

40 C-

° ° ° °

I =200mA

OUT

2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6

InputVoltage(V)

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

OutputVoltage(V)

+125 C

+85 C +25 C

40 C-

° ° ° °

I =10mA

OUT

2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6

InputVoltage(V)

1.90

1.88

1.86

1.84

1.82

1.80

1.78

1.76

1.74

1.72

1.70

OutputVoltage(V)

+125 C

+85 C +25 C

40 C-

° ° ° °

I =200mA

OUT

www.ti.com

6.6 Typical Characteristics

Over operating temperature range (TJ= –40°C to +125°C), VIN= V VEN= VIN, C

= 1 μF, unless otherwise noted. Typical values are at TJ= 25°C.

OUT

Figure 1. TLV70018 Line Regulation Figure 2. TLV70018 Line Regulation

OUT(nom)

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

+ 0.5 V or 2 V, whichever is greater; I

OUT

TLV700

= 10 mA,

Figure 3. TLV70018 Load Regulation Figure 4. Dropout Voltage vs Input Voltage

Figure 5. Dropout Voltage vs Output Current, V

OUT

= 4.8 V

Figure 6. TLV70018 Output Voltage vs Temperature

Product Folder Links: TLV700

2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8

InputVoltage(V)

PSRR(dB)

10kHz

100kHz

1kHz

100

PSRR(dB)

10 100

1k 10k 100k 1M 10M

Frequency(Hz)

I =150mA

OUT

I =10mA

OUT

V V =0.5V

IN OUT

2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6

InputVoltage(V)

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

ShutdownCurrent( A)m

+125 C

+85 C +25 C

° ° °

GroundPinCurrent( A)m

-40 -25 -10

20 35 50 65 80 95 110 125

Temperature( C)

I =0mA

OUT

2.1 2.6 3.1 3.6 4.1 4.6 5.1 5.6

InputVoltage(V)

GroundPinCurrent( A)m

+125 C

+85 C +25 C

40 C-

° ° ° °

I =0mA

OUT

+125 C

+85 C +25 C

40 C-

° ° ° °

300

250

200

150

100

GroundPinCurrent( A)m

0 20 40 60 80 100 120 140 160 180 200

OutputCurrent(mA)

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

Typical Characteristics (continued)

www.ti.com

Over operating temperature range (TJ= –40°C to +125°C), VIN= V VEN= VIN, C

Figure 7. TLV70018 Ground Pin Current vs Input Voltage

= 1 μF, unless otherwise noted. Typical values are at TJ= 25°C.

OUT

OUT(nom)

+ 0.5 V or 2 V, whichever is greater; I

Figure 8. TLV70018 Ground Pin Current vs Load

OUT

= 10 mA,

Figure 9. TLV70018 Ground Pin Current vs Temperature

Figure 11. TLV70018 Power-Supply Ripple Rejection vs

Frequency

Figure 10. TLV70018 Shutdown Current vs Input Voltage

Figure 12. TLV70018 Power-Supply Ripple Rejection vs

Input Voltage

Product Folder Links: TLV700

1V/div

5mV/div

1ms/div

OUT

SlewRate=1V/ sm

2.9V

2.3V

I 200mA

OUT

1V/div

5mV/div

1ms/div

OUT

2.7V

2.3V

I 1mA

OUT

SlewRate=1V/ sm

20mA/div

5mV/div

10 s/divm

OUT

VIN=2.3V

OUT

10mA

0mA

t =t =1 s

R F

50mA/div

20mV/div

10 s/divm

OUT

VIN=2.3V

OUT

50mA

0mA

t =t =1 s

R F

0.1

0.01

OutputSpectralNoiseDensity( V/ )m Hz

10 100

1k 10k 100k 1M 10M

Frequency(Hz)

I =10mA C =C =1 F

OUT

IN OUT

100mA/div

50mV/div

10 s/divm

OUT

VIN=2.1V

OUT

200mA

0mA

t =t =1 s

R F

www.ti.com

Typical Characteristics (continued)

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

Over operating temperature range (TJ= –40°C to +125°C), VIN= V VEN= VIN, C

Figure 13. TLV70018 Output Spectral Noise Density vs

= 1 μF, unless otherwise noted. Typical values are at TJ= 25°C.

OUT

Output Voltage

OUT(nom)

+ 0.5 V or 2 V, whichever is greater; I

OUT

= 10 mA,

Figure 14. TLV70018 Load Transient Response

Figure 15. TLV70018 Load Transient Response Figure 16. TLV70018 Load Transient Response

Figure 17. TLV70018 Line Transient Response Figure 18. TLV70018 Line Transient Response

Product Folder Links: TLV700

1V/div

10mV/div

1ms/div

OUT

5.5V

2.1V

I 200mA

OUT

SlewRate=1V/ sm

1V/div

200ms/div

OUT

I 1mA

OUT

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

Typical Characteristics (continued)

www.ti.com

Over operating temperature range (TJ= –40°C to +125°C), VIN= V VEN= VIN, C

= 1 μF, unless otherwise noted. Typical values are at TJ= 25°C.

OUT

Figure 19. TLV70018 Line Transient Response Figure 20. TLV70018 VINRamp-Up, Ramp-Down Response

OUT(nom)

+ 0.5 V or 2 V, whichever is greater; I

OUT

= 10 mA,

Product Folder Links: TLV700

Thermal

Shutdown

Current

Limit

UVLO

Bandgap

OUT

LOGIC

GND

TLV700xxSeries

TLV700

www.ti.com

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

7 Detailed Description

7.1 Overview

The TLV700 series of LDO linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision bandgap and error amplifier provides overall 2% accuracy. Low output noise, very high PSRR, and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. All device versions have integrated thermal shutdown, current limit, and undervoltage lockout (UVLO).

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Internal Current Limit

The TLV700 internal current limit helps to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is V ICLuntil thermal shutdown is triggered and the device turns off. As the device cools down, it is turned on by the

OUT

= ICL× R

. The PMOS pass transistor dissipates (VIN– V

LOAD

OUT

internal thermal shutdown circuit. If the fault condition continues, the device cycles between current limit and thermal shutdown. See Thermal Protection for more details.

The PMOS pass element in the TLV700 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended.

7.3.2 Shutdown

The enable pin (EN) is active high. The device is enabled when voltage at EN pin goes above 0.9 V. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the IN pin.

Product Folder Links: TLV700

) ×

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

www.ti.com

Feature Description (continued)

7.3.3 Dropout Voltage

The TLV700 uses a PMOS pass transistor to achieve low dropout. When (VIN– V

) is less than the dropout

OUT

voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the R

of the PMOS pass element. VDOscales approximately with output current because the PMOS device

DS(on)

behaves as a resistor in dropout. As with any linear regulator, PSRR and transient response are degraded as (VIN– V

) approaches dropout.

OUT

This effect is shown in Figure 12 in Typical Characteristics.

7.3.4 Undervoltage Lockout (UVLO)

The TLV700 uses a UVLO circuit to keep the output shut off until internal circuitry is operating properly.

7.4 Device Functional Modes

7.4.1 Normal Operation

The device regulates to the nominal output voltage under the following conditions:

• The input voltage is greater than the nominal output voltage added to the dropout voltage.

• The output current is less than the current limit.

• The input voltage is greater than the UVLO voltage.

7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of the LDO. Line or load transients in dropout may result in large output voltage deviations.

Table 1 lists the conditions that lead to the different modes of operation.

Table 1. Device Functional Mode Comparison

OPERATING MODE

Normal mode VIN> V

Dropout mode VIN< V

Current limit VIN> UVLO I

OUT(nom) OUT(nom)

PARAMETER

+ V

OUT

OUT OUT

OUT

< I < I > I

CL CL CL

Product Folder Links: TLV700

TLV700xx

GND

IN OUT

OUT

Off

OUT

1 F Ceramic

TLV700

www.ti.com

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLV700 belongs to a new family of next-generation value LDO regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise, very good PSRR with little (VIN– V applications. This family of regulators offers current limit and thermal protection, and is specified from –40°C to +125°C.

8.2 Typical Application

Figure 21 shows a typical application circuit.

) headroom, make this family of devices ideal for RF portable

OUT

Figure 21. Typical Application Circuit

8.2.1 Design Requirements

Table 2 lists the design parameters.

Table 2. Design Parameters

PARAMETER DESIGN REQUIREMENT

Input voltage 2.5 V to 3.3 V Output voltage 1.8 V Output current 100 mA

8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor Requirements

TI recommends using 1-μF X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature.

However, the TLV700 is designed to be stable with an effective capacitance of 0.1 μF or larger at the output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 μF. This effective capacitance refers to the capacitance that the LDO sees under operating bias voltage and temperature conditions; that is, the capacitance after taking both bias voltage and temperature derating into consideration. In addition to allowing the use of cheaper dielectrics, this capability of being stable with 0.1-μF effective capacitance also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications.

Using a 0.1-μF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions must not be less than 0.1 μF. Maximum ESR should be less than 200 mΩ.

Product Folder Links: TLV700

50mA/div

20mV/div

10 s/divm

OUT

VIN=2.3V

OUT

50mA

0mA

t =t =1 s

R F

1V/div

5mV/div

1ms/div

OUT

SlewRate=1V/ sm

2.9V

2.3V

I 200mA

OUT

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

www.ti.com

Although an input capacitor is not required for stability, it is good analog design practice to connect a 0.1-μF to 1- μF, low ESR capacitor across the IN pin and GND in of the regulator. This capacitor counteracts reactive input

sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability.

8.2.2.2 Transient Response

As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases the duration of the transient response.

8.2.3 Application Curves

Figure 22. TLV70018 Load Transient Response

Figure 23. TLV70018 Line Transient Response

9 Power Supply Recommendations

Connect a low output impedance power supply directly to the INPUT pin of the TLV700. Inductive impedances between the input supply and the INPUT pin can create significant voltage excursions at the INPUT pin during start-up or load transient events.

Product Folder Links: TLV700

OUT

GND PLANE

Represents via used for

application specific connections

GND

OUT

GND PLANE

Represents via used for

application specific connections

GND

OUT

TLV700

www.ti.com

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

10 Layout

10.1 Layout Guidelines

Input and output capacitors should be placed as close to the device pins as possible. To improve AC performance such as PSRR, output noise, and transient response, TI recommends designing the printed-circuitboards with separate ground planes for VINand V the device. In addition, the ground connection for the output capacitor should be connected directly to the GND pin of the device. High ESR capacitors may degrade PSRR performance.

10.2 Layout Examples

, with the ground plane connected only at the GND pin of

OUT

Figure 24. Layout Example for the DCK and DDC Package

Figure 25. Layout Example for the DSE Package

10.3 Thermal Protection

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating.

Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heatsink. For reliable operation, junction temperature should be limited to 125°C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions.

For good reliability, thermal protection should trigger at least 35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

Product Folder Links: TLV700

P =(V V ) I- ´

D IN OUT OUT

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

www.ti.com

Thermal Protection (continued)

The internal protection circuitry of the TLV700 has been designed to protect against overload conditions. The protection circuitry was not intended to replace proper heatsinking. Continuously running the TLV700 into thermal shutdown degrades device reliability.

10.4 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the PCB layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness.

Power dissipation depends on input voltage and load conditions. Power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 1.

(1)

Product Folder Links: TLV700

TLV700

www.ti.com

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Evaluation Modules

Three evaluation modules (EVMs) are available to assist in the initial circuit performance evaluation using the TLV700:

• TLV70033EVM-503

• TLV70018EVM-503

• TLV70028EVM-463 These EVMs can be requested at the Texas Instruments website through the product folders or purchased

directly from the TI eStore.

11.1.1.2 Spice Models

Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TLV700 is available through the product folders under Tools & Software.

11.1.2 Device Nomenclature

Table 3. Ordering Information

PRODUCT V

TLV700xx yyyz XX is nominal output voltage (for example, 28 = 2.8 V).

YYY is the package designator. Z is tape and reel quantity (R = 3000, T = 250).

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the

device product folder at www.ti.com.

(2) Output voltages from 1.2 V to 4.8 V in 50-mV increments are available. Contact factory for details and availability.

(1)

OUT

(2)

11.2 Documentation Support

11.2.1 Related Documentation

• Using the TLV700xxEVM-463 Evaluation Module, SLUU390

• Using the TLV700xxEVM-503 Evaluation Module, SLUU391

11.3 Trademarks

Bluetooth is a registered trademark of Bluetooth SIG. ZigBee is a registered trademark of the ZigBee Alliance. All other trademarks are the property of their respective owners.

11.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

Product Folder Links: TLV700

TLV700

SLVSA00E –SEPTEMBER 2009–REVISED APRIL 2015

www.ti.com

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: TLV700

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

(1)

TLV70012DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS

TLV70012DCKT ACTIVE SC70 DCK 5 250 Green (RoHS

TLV70012DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70012DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70012DSER ACTIVE WSON DSE 6 3000 Green (RoHS

TLV70012DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70013DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70013DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70015DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS

TLV70015DCKT ACTIVE SC70 DCK 5 250 Green (RoHS

TLV70015DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70015DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70015DSER ACTIVE WSON DSE 6 3000 Green (RoHS

TLV70015DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70018DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS

TLV70018DCKT ACTIVE SC70 DCK 5 250 Green (RoHS

TLV70018DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODT

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODO

CU NIPDAU Level-1-260C-UNLIM -40 to 125 NH

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SAH

CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODU

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODP

CU NIPDAU Level-1-260C-UNLIM -40 to 125 NJ

CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODV

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODK

14-Jan-2016

Samples

(4/5)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TLV70018DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70018DSER ACTIVE WSON DSE 6 3000 Green (RoHS

TLV70018DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70019DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70019DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70022DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70022DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70025DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS

TLV70025DCKT ACTIVE SC70 DCK 5 250 Green (RoHS

TLV70025DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70025DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70025DSER ACTIVE WSON DSE 6 3000 Green (RoHS

TLV70025DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70028DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS

TLV70028DCKT ACTIVE SC70 DCK 5 250 Green (RoHS

TLV70028DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70028DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70028DSER ACTIVE WSON DSE 6 3000 Green (RoHS

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODK

CU NIPDAU Level-1-260C-UNLIM -40 to 125 NK

CU NIPDAU Level-1-260C-UNLIM -40 to 85 NK

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCJ

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCI

CU NIPDAU Level-1-260C-UNLIM -40 to 125 QTP

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 DAU

CU NIPDAU Level-1-260C-UNLIM -40 to 125 QY

CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODW

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODL

CU NIPDAU Level-1-260C-UNLIM -40 to 125 NL

14-Jan-2016

Samples

(4/5)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TLV70028DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70029DSER ACTIVE WSON DSE 6 3000 Green (RoHS

TLV70029DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70030DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS

TLV70030DCKT ACTIVE SC70 DCK 5 250 Green (RoHS

TLV70030DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70030DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70030DSER ACTIVE WSON DSE 6 3000 Green (RoHS

TLV70030DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70031DSER ACTIVE WSON DSE 6 3000 Green (RoHS

TLV70031DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70032DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70032DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70033DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS

TLV70033DCKT ACTIVE SC70 DCK 5 250 Green (RoHS

TLV70033DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70033DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70033DSER ACTIVE WSON DSE 6 3000 Green (RoHS

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

CU NIPDAU Level-1-260C-UNLIM -40 to 125 NL

CU NIPDAU Level-1-260C-UNLIM -40 to 125 QJ

CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODR

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODM

CU NIPDAU Level-1-260C-UNLIM -40 to 125 NP

CU NIPDAU Level-1-260C-UNLIM -40 to 125 C4

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCH

CU NIPDAU Level-1-260C-UNLIM -40 to 125 ODS

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 ODN

CU NIPDAU Level-1-260C-UNLIM -40 to 125 NR

14-Jan-2016

Samples

(4/5)

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

TLV70033DSET ACTIVE WSON DSE 6 250 Green (RoHS

TLV70036DDCR ACTIVE SOT DDC 5 3000 Green (RoHS

TLV70036DDCT ACTIVE SOT DDC 5 250 Green (RoHS

TLV70036DSER ACTIVE WSON DSE 6 3000 Green (RoHS

TLV70036DSET ACTIVE WSON DSE 6 250 Green (RoHS

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

Package Type Package

(1)

Drawing

Pins Package

Qty

Eco Plan

(2)

& no Sb/Br)

Lead/Ball Finish

(6)

CU NIPDAU Level-1-260C-UNLIM -40 to 125 NR

CU NIPDAU Level-2-260C-1 YEAR -40 to 125 SCG

CU NIPDAU Level-1-260C-UNLIM -40 to 125 UG

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

14-Jan-2016

(4/5)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Samples

Addendum-Page 4

PACKAGE OPTION ADDENDUM

www.ti.com

14-Jan-2016

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 5

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jan-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

TLV70012DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70012DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70012DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70012DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70012DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70012DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70012DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70012DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70012DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70012DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70013DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70013DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70015DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70015DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70015DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70015DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70015DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70015DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jan-2016

Device Package

Type

TLV70015DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70015DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70015DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70015DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70018DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70018DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70018DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70018DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70018DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70018DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70018DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70018DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70018DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70018DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70018DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70018DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70018DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70019DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70019DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70022DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70022DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70025DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70025DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70025DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70025DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70025DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70025DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70025DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70025DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70025DSER WSON DSE 6 3000 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70025DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70025DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70025DSET WSON DSE 6 250 179.0 8.4 1.8 1.8 1.0 4.0 8.0 Q2 TLV70028DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70028DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70028DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70028DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70028DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70028DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70028DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70028DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70028DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70028DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jan-2016

Device Package

Type

TLV70029DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70029DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70030DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70030DCKR SC70 DCK 5 3000 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70030DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70030DCKT SC70 DCK 5 250 179.0 8.4 2.2 2.5 1.2 4.0 8.0 Q3 TLV70030DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70030DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70030DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70030DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70030DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70030DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70030DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70030DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70031DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70031DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70032DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70032DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70033DCKR SC70 DCK 5 3000 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70033DCKR SC70 DCK 5 3000 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70033DCKT SC70 DCK 5 250 180.0 8.4 2.47 2.3 1.25 4.0 8.0 Q3 TLV70033DCKT SC70 DCK 5 250 178.0 9.0 2.4 2.5 1.2 4.0 8.0 Q3 TLV70033DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70033DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70033DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70033DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 TLV70033DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70033DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70036DDCR SOT DDC 5 3000 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70036DDCT SOT DDC 5 250 180.0 8.4 3.1 3.05 1.1 4.0 8.0 Q3 TLV70036DSER WSON DSE 6 3000 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2 TLV70036DSET WSON DSE 6 250 180.0 8.4 1.83 1.83 0.89 4.0 8.0 Q2

Package Drawing

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Pin1

Quadrant

Pack Materials-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jan-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV70012DCKR SC70 DCK 5 3000 180.0 180.0 18.0 TLV70012DCKR SC70 DCK 5 3000 202.0 201.0 28.0 TLV70012DCKT SC70 DCK 5 250 202.0 201.0 28.0

TLV70012DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70012DDCR SOT DDC 5 3000 406.0 348.0 63.0 TLV70012DDCR SOT DDC 5 3000 195.0 200.0 45.0

TLV70012DDCT SOT DDC 5 250 195.0 200.0 45.0

TLV70012DDCT SOT DDC 5 250 202.0 201.0 28.0

TLV70012DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70012DSET WSON DSE 6 250 202.0 201.0 28.0 TLV70013DDCR SOT DDC 5 3000 202.0 201.0 28.0

TLV70013DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70015DCKR SC70 DCK 5 3000 180.0 180.0 18.0

TLV70015DCKR SC70 DCK 5 3000 202.0 201.0 28.0

TLV70015DCKT SC70 DCK 5 250 202.0 201.0 28.0

TLV70015DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70015DDCR SOT DDC 5 3000 195.0 200.0 45.0 TLV70015DDCR SOT DDC 5 3000 223.0 270.0 35.0

TLV70015DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70015DDCT SOT DDC 5 250 195.0 200.0 45.0

Pack Materials-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jan-2016

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV70015DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70015DSET WSON DSE 6 250 202.0 201.0 28.0

TLV70018DCKR SC70 DCK 5 3000 202.0 201.0 28.0

TLV70018DCKR SC70 DCK 5 3000 180.0 180.0 18.0

TLV70018DCKR SC70 DCK 5 3000 203.0 203.0 35.0

TLV70018DCKT SC70 DCK 5 250 203.0 203.0 35.0

TLV70018DCKT SC70 DCK 5 250 202.0 201.0 28.0

TLV70018DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70018DDCR SOT DDC 5 3000 223.0 270.0 35.0 TLV70018DDCR SOT DDC 5 3000 195.0 200.0 45.0

TLV70018DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70018DDCT SOT DDC 5 250 195.0 200.0 45.0

TLV70018DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70018DSER WSON DSE 6 3000 203.0 203.0 35.0

TLV70018DSET WSON DSE 6 250 202.0 201.0 28.0 TLV70019DDCR SOT DDC 5 3000 195.0 200.0 45.0

TLV70019DDCT SOT DDC 5 250 195.0 200.0 45.0 TLV70022DDCR SOT DDC 5 3000 195.0 200.0 45.0

TLV70022DDCT SOT DDC 5 250 195.0 200.0 45.0

TLV70025DCKR SC70 DCK 5 3000 180.0 180.0 18.0

TLV70025DCKR SC70 DCK 5 3000 203.0 203.0 35.0

TLV70025DCKT SC70 DCK 5 250 203.0 203.0 35.0

TLV70025DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70025DDCR SOT DDC 5 3000 223.0 270.0 35.0 TLV70025DDCR SOT DDC 5 3000 195.0 200.0 45.0

TLV70025DDCT SOT DDC 5 250 195.0 200.0 45.0

TLV70025DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70025DSER WSON DSE 6 3000 203.0 203.0 35.0

TLV70025DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70025DSET WSON DSE 6 250 202.0 201.0 28.0

TLV70025DSET WSON DSE 6 250 203.0 203.0 35.0

TLV70028DCKR SC70 DCK 5 3000 180.0 180.0 18.0

TLV70028DCKR SC70 DCK 5 3000 202.0 201.0 28.0

TLV70028DCKT SC70 DCK 5 250 180.0 180.0 18.0

TLV70028DCKT SC70 DCK 5 250 202.0 201.0 28.0 TLV70028DDCR SOT DDC 5 3000 195.0 200.0 45.0 TLV70028DDCR SOT DDC 5 3000 223.0 270.0 35.0

TLV70028DDCT SOT DDC 5 250 195.0 200.0 45.0

TLV70028DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70028DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70028DSET WSON DSE 6 250 202.0 201.0 28.0

TLV70029DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70029DSET WSON DSE 6 250 202.0 201.0 28.0

TLV70030DCKR SC70 DCK 5 3000 202.0 201.0 28.0

Pack Materials-Page 5

PACKAGE MATERIALS INFORMATION

www.ti.com 15-Jan-2016

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TLV70030DCKR SC70 DCK 5 3000 203.0 203.0 35.0

TLV70030DCKR SC70 DCK 5 3000 180.0 180.0 18.0

TLV70030DCKT SC70 DCK 5 250 203.0 203.0 35.0

TLV70030DCKT SC70 DCK 5 250 180.0 180.0 18.0

TLV70030DCKT SC70 DCK 5 250 202.0 201.0 28.0 TLV70030DDCR SOT DDC 5 3000 223.0 270.0 35.0 TLV70030DDCR SOT DDC 5 3000 195.0 200.0 45.0

TLV70030DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70030DDCT SOT DDC 5 250 195.0 200.0 45.0

TLV70030DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70030DSET WSON DSE 6 250 202.0 201.0 28.0

TLV70031DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70031DSET WSON DSE 6 250 202.0 201.0 28.0 TLV70032DDCR SOT DDC 5 3000 202.0 201.0 28.0

TLV70032DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70033DCKR SC70 DCK 5 3000 202.0 201.0 28.0

TLV70033DCKR SC70 DCK 5 3000 180.0 180.0 18.0

TLV70033DCKT SC70 DCK 5 250 202.0 201.0 28.0

TLV70033DCKT SC70 DCK 5 250 180.0 180.0 18.0 TLV70033DDCR SOT DDC 5 3000 195.0 200.0 45.0 TLV70033DDCR SOT DDC 5 3000 223.0 270.0 35.0

TLV70033DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70033DDCT SOT DDC 5 250 195.0 200.0 45.0

TLV70033DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70033DSET WSON DSE 6 250 202.0 201.0 28.0 TLV70036DDCR SOT DDC 5 3000 202.0 201.0 28.0

TLV70036DDCT SOT DDC 5 250 223.0 270.0 35.0

TLV70036DSER WSON DSE 6 3000 202.0 201.0 28.0

TLV70036DSET WSON DSE 6 250 202.0 201.0 28.0

Pack Materials-Page 6

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Texas Instruments LV70036DSER, TLV70012DCKR, TLV70012DDCR, TLV70012DSER, TLV70013DDCR Schematic [ru]

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Features 3 Description

2 Applications

Table of Contents

4 Revision History

5 Pin Configuration and Functions

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 Typical Characteristics

7 Detailed Description

7.1 Overview

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Internal Current Limit

7.3.2 Shutdown

7.3.3 Dropout Voltage

7.3.4 Undervoltage Lockout (UVLO)

7.4 Device Functional Modes

7.4.1 Normal Operation

7.4.2 Dropout Operation

8 Application and Implementation

8.1 Application Information

8.2 Typical Application

8.2.1 Design Requirements

8.2.2 Detailed Design Procedure

8.2.2.1 Input and Output Capacitor Requirements

8.2.2.2 Transient Response

8.2.3 Application Curves

9 Power Supply Recommendations

10 Layout

10.1 Layout Guidelines

10.2 Layout Examples

10.3 Thermal Protection

10.4 Power Dissipation

11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Evaluation Modules

11.1.1.2 Spice Models

11.1.2 Device Nomenclature

11.2 Documentation Support

11.2.1 Related Documentation

11.3 Trademarks

11.4 Electrostatic Discharge Caution

11.5 Glossary

12 Mechanical, Packaging, and Orderable Information