Texas Instruments TLV5618AQDR, TLV5618AQD, TLV5618AMJG, TLV5618AMJGB, TLV5618AMFKB Datasheet

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230D – JULY 1999 – REVISED MARCH 2000

features

D

Dual 12-Bit Voltage Output DAC

D

Programmable Settling Time
– 2.5 µs in Fast Mode
– 12 µs in Slow Mode

D

Compatible With TMS320 and SPI Serial
Ports

D

Differential Nonlinearity <0.5 LSB Typ

D

Monotonic Over Temperature

D

Available in Q-Temp Automotive

HighRel Automotive Applications
Configuration Control / Print Support
Qualification to Automotive Standards

description

The TL V5618A is a dual 12-bit voltage output DAC
with a flexible 3-wire serial interface. The serial
interface is compatible with TMS320, SPI,
QSPI, and Microwire serial ports. It is
programmed with a 16-bit serial string containing
4 control and 12 data bits.

The resistor string output voltage is buffered by an
x2 gain rail-to-rail output buffer. The buffer
features a Class-AB output stage to improve
stability and reduce settling time. The program­mable settling time of the DAC allows the designer
to optimize speed versus power dissipation.

applications

D

Digital Servo Control Loops

D

Digital Offset and Gain Adjustment

D

Industrial Process Control

D

Machine and Motion Control Devices

D

Mass Storage Devices

D OR JG PACKAGE

(TOP VIEW)

DIN

NC

SCLK

NC
CS
NC

SCLK

CS

OUTA

4
5
6
7
8

1
2
3
4

FK PACKAGE

(TOP VIEW)

NC

NC

DINNCV

NC

OUTA

8
7
6
5

AGND

DD

1920132

1312119 10

V

DD

OUTB
REF
AGND

NC

18
17
16
15
14

NC

NC
OUTB
NC
REF
NC

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It
is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.

The TL V5618AC is characterized for operation from 0°C to 70°C. The TL V5618AI is characterized for operation
from –40°C to 85°C. The TLV5618AQ is characterized for operation from –40°C to 125°C. The TLV5618AM
is characterized for operation from –55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLV5618ACD — —

–40°C to 85°C TLV5618AID — —
–40°C to 125°C
–55°C to 125°C — TLV5618AMJG TLV5618AMFK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SOIC

(D)

TLV5618AQD

TLV5618AQDR

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CERAMIC DIP

(JG)

— —

20 PAD LCCC

(FK)

Copyright  2000, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

TLV5618A

I/O/P

DESCRIPTION

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230D – JULY 1999 – REVISED MARCH 2000

functional block diagram

DIN

SCLK

CS

Power-On

Reset

Speed Control

Serial

Interface

and

Control

Power and

2

12

Buffer

REF AGND V

12 12

12

12-Bit

DAC A

Latch

12-Bit

DAC B

Latch

12

DD

x2

x2

OUTA

OUTB

Terminal Functions

TERMINAL

NAME NO.

AGND 5 P Ground
CS 3 I Chip select. Digital input active low, used to enable/disable inputs.
DIN 1 I Digital serial data input
OUTA 4 O DAC A analog voltage output
OUTB 7 O DAC B analog voltage output
REF 6 I Analog reference voltage input
SCLK 2 I Digital serial clock input
V

DD

8 P Positive power supply

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE

A

A

A

A

Suppl

oltage, V

Operating free-air temperature, T

°C

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230D – JULY 1999 – REVISED MARCH 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range – 0.3 V to V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV5618AC 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5618AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5618AQ –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV5618AM –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

T

≤ 25°C DERATING FACTOR T

POWER RATING ABOVE TA = 25°C

D 635 mW 5.08 mW/°C 407 mW 330 mW 127 mW
FK 1375 mW 11.00 mW/°C 880 mW 715 mW 275 mW
JG 1050 mW 8.40 mW/°C 672 mW 546 mW 210 mW

‡

This is the inverse of the traditional junction-to-ambient thermal resistance (RΘJA). Thermal resistances are not production tested and are for
informational purposes only.

‡

= 70°C T

POWER RATING

= 85°C T

POWER RATING

= 125°C

POWER RATING

recommended operating conditions

MIN NOM MAX UNIT

pp

y v

Power on reset, POR 0.55 2 V
High-level digital input voltage, V
Low-level digital input voltage, V
Reference voltage, V
Reference voltage, V
Load resistance, R
Load capacitance, C
Clock frequency, f

p

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD–0.4 V)/2 causes clipping of the transfer function.

DD

IH

IL

to REF terminal VDD = 5 V (see Note 1) AGND 2.048 VDD–1.5 V

ref

to REF terminal VDD = 3 V (see Note 1) AGND 1.024 VDD–1.5 V

ref

L

L

CLK

p

A

VDD = 5 V 4.5 5 5.5
VDD = 3 V 2.7 3 3.3

VDD = 2.7 V to 5.5 V 2 V
VDD = 2.7 V to 5.5 V 0.8 V

2 kΩ

100 pF

TLV5618AC 0 70
TLV5618AI –40 85
TLV5618AQ –40 125
TLV5618AM –55 125

V

20 MHz

°

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLV5618A

I

P

t

All i

AGND

A

DD

y

DD

,

DAC latch = 0x800

Slow

0.8

1

PSRR

Power supply rejection ratio

dB

Reference input bandwidth

REF

V

024 V dc

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230D – JULY 1999 – REVISED MARCH 2000

electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

No load,

ower supply curren

Power down supply current 1 µA

pp

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin)/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
PSRR = 20 log [(EG(VDDmax) – EG(VDDmin)/VDDmax]

nputs =

Zero scale, See Note 2 –65
Full scale, See Note 3 –65

or V,

=

Fast 1.8 2.3
Slow 0.8 1

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 12 bits
INL Integral nonlinearity See Note 4 ±2 ±4 LSB
DNL Differential nonlinearity See Note 5 ±0.5 ±1 LSB
E

ZS

EZS TC Zero-scale-error temperature coefficient See Note 7 3 ppm/°C
E

G

EG T

NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error , is the maximum deviation of the output

Zero-scale error (offset error at zero scale) See Note 6 ±12 mV

Gain error See Note 8 ±0.6

Gain-error temperature coefficient See Note 9 1 ppm/°C

C

from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.

5. The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal
1-LSB amplitude change of any two adjacent codes.

6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (T

8. Gain error is the deviation from the ideal output (2V

9. Gain temperature coefficient is given by: EG TC = [EG (T

– 1 LSB) with an output load of 10 kΩ.

ref

max) – Eg

(T

max) – EZS

min

)]/2V

(T

× 106/(T

ref

min

)]/2V

max

× 106/(T

ref

– T

min

– T

max

).

output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Output voltage range RL = 10 kΩ VDD–0.4 V
Output load regulation accuracy VO = 4.096 V, 2.048 V RL = 2 kΩ ±0.29 % FS

min

UNIT

m

% full

scale V

).

reference input

VIInput voltage range 0 V
RIInput resistance 10 MΩ
CIInput capacitance 5 pF

Reference feedthrough REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) –80 dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

4

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DD–1.5

p

= 0.2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

pp

+ 1.

Fast 1.3 MHz
Slow 525 kHz

V

t

Output settling time, full scale

L

,

L

,

s

t

Output settling time, code to code

L

,

L

,

s

SR

Slew rate

L

,

L

,

V/µs

s

,

out

,

dB

TLV5618A

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT

DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230D – JULY 1999 – REVISED MARCH 2000

electrical characteristics over recommended operating conditions (unless otherwise noted)
(Continued)

digital inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

High-level digital input current VI = V

IH

I

Low-level digital input current VI = 0 V –1 µA

IL

C

Input capacitance 8 pF

i

DD

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R

s(FS)

s(CC)

SNR Signal-to-noise ratio 76
SINAD Signal-to-noise + distortion
THD Total harmonic distortion
SFDR Spurious free dynamic range 72

NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

p

p

Glitch energy

of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.

12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, assured by design.

13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.

= 10 kΩ,C

See Note 11
R

= 10 kΩ,C

See Note 12
R

= 10 kΩ,C

See Note 13
DIN = 0 to 1, FCLK = 100 kHz,

CS

= V

DD

f

= 102 kSPS, f

RL = 10 kΩ,CL = 100 pF

= 100 pF,

= 100 pF,

= 100 pF,

= 1 kHz,

Fast 2.5
Slow 12
Fast 1
Slow 2
Fast 3
Slow 0.5

68

–68

1 µA

µ

µ

5 nV–s

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TLV5618A

t

Setup time, data ready before SCLK falling edge

ns

2.7-V TO 5.5-V LOW-POWER DUAL 12-BIT
DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS230D – JULY 1999 – REVISED MARCH 2000

digital input timing requirements

t

su(CS–CK)

t

su(C16-CS)

t

wH

t

wL

su(D)

t

h(D)

timing requirements

Setup time, CS low before first negative SCLK edge 10 ns
Setup time, 16th negative SCLK edge before CS rising edge 10 ns
SCLK pulse width high 25 ns
SCLK pulse width low 25 ns

p

Hold time, data held valid after SCLK falling edge 5 ns

t

t

wL

wH

C and I suffixes 10
Q and M suffixes 8

MIN NOM MAX UNIT

SCLK

DIN

CS

X

t

1

t

su(D)th(D)

su(CS-CK)

2 3 4 5 15 16

D15 D14 D13 D12 D1 D0 XX

t

X

su(C16-CS)

Figure 1. Timing Diagram

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265