Texas Instruments TLV1578IDA, TLV1578IDAR, TLV1578EVM, TLV1578CDAR, TLV1571IDW Datasheet

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D

Fast Throughput Rate: 1.25 MSPS at 5 V,

625 KSPS at 3 V

D

Wide Analog Input: 0 V to AV

DD

D

Differential Nonlinearity Error: < ± 1 LSB

D

Integral Nonlinearity Error: < ± 1 LSB

D

8-to-1 Analog MUX – TLV1578

D

Internal OSC

D

Single 2.7-V to 5.5-V Supply Operation

D

Low Power: 12 mW at 3 V and 35 mW at 5 V

D

Auto Power Down of 1 mA Max

D

Software Power Down: 10 µA Max

D

Hardware Configurable

D

DSP and Microcontroller Compatible
Parallel Interface

D

Binary/Twos Complement Output

D

Hardware Controlled Extended Sampling

D

Channel Sweep Mode Operation and
Channel Select

D

Hardware or Software Start of Conversion

applications

D

Mass Storage and HDD

D

Automotive

D

Digital Servos

D

Process Control

D

General-Purpose DSP

D

Image Sensor Processing

description

The TLV1571/1578 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a
high-speed 10-bit ADC, and a parallel interface. The device contains two on-chip control registers allowing
control of channel selection, software conversion start, and power down via the bidirectional parallel port. The
control registers can be set to a default mode by applying a dummy RD

signal when WR is tied low. This allows
the TLV1571/1578 to be configured by hardware. The MUX is independently accessible. This allows the user to
insert a signal conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and
the ADC. Therefore, one signal conditioning circuit can be used for all eight channels. The TL V1571 is a single
channel analog input device with all the same functions as the TLV1578.

The TL V1571/TLV1578 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range
from 0 V to A VDD and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V . The power dissipations
are only 12 mW with a 3-V supply or 35 mW with a 5-V supply . The device features an auto power-down mode
that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the
ADC is further powered down to only 10 µA.

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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13
14
15
16

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

CH0
CH1
CH2
CH3

CS

WR

RD

CLK

DGND

DV

DD

INT

/EOC

D0
D1
D2
D3
D4

CH7
CH6
CH5
CH4
MO
AIN
AV

DD

AGND
REFM
REFP
CSTART
D9/A1
D8/A0
D7
D6
D5

TLV1578

DA PACKAGE

(TOP VIEW)

NC – No internal connection

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

CS

WR

RD

CLK

DGND

DV

DD

INT/EOC

D0
D1
D2
D3
D4

NC
AIN
AV

DD

AGND
REFM
REFP
CSTART
D9/A1
D8/A0
D7
D6
D5

TLV1571

DW OR PW PACKAGE

(TOP VIEW)

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Very high throughput rate, simple parallel interface, and low power consumption make the TLV1571/TLV1578
an ideal choice for high-speed digital signal processing requiring multiple analog inputs.

AVAILABLE OPTIONS

PACKAGE

T

A

32 TSSOP

(DA)

24 SOP

(DW)

24 TSSOP

(PW)

0°C to 70°C TLV1578CDA TLV1571CDW TLV1571CPW

–40°C to 85°C TLV1578IDA TLV1571IDW TLV1571IPW

functional block diagram – TLV1571/78

Internal

Clock

CLK

CS
RD

INT/EOC

MUX

10-BIT

SAR ADC

Input Registers

and Control Logic

WR

CSTART

REFP

Three

State

Latch

AV

DD

D0 – D7

D8/A0
D9/A1

REFM DV

DD

DGNDAGND

MUX

CH0 – CH7

MO AIN

TLV1578 Only

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NO.

I/O DESCRIPTION

NAME

TLV1571 TLV1578

AGND 21 25 Analog ground
AIN 23 27 I ADC analog input (used as single analog input channel for TLV1571)
AV

DD

22 26 Analog supply voltage, 2.7 V to 5.5 V

CH0 – CH7 – 1–4,

29–32

I Analog input channels

CLK 4 8 I External clock input
CS 1 5 I Chip select. A logic low on CS enables the TLV1571/TLV1578.
CSTAR T 18 22 I Hardware sample and conversion start input. The falling edge of CSTART starts sampling and

the rising edge of CSTART

starts conversion.
DGND 5 9 Digital ground
DV

DD

6 10 Digital supply voltage, 2.7 V to 5.5 V

D0 – D7 8–12,

13–15

12–16,

17–19

I/O Bidirectional 3-state data bus

D8/A0 16 20 I/O Bidirectional 3-state data bus. D8/A0 along with D9/A1 is used as address lines to access CR0

and CR1 for initialization.

D9/A1 17 21 I/O Bidirectional 3-state data bus. D9/A1 along with D8/A0 is used as address lines to access CR0

and CR1 for initialization.

INT/EOC

7 11 O End-of-conversion/interrupt
MO 28 O On-chip mux analog output
NC 24 Not connected
RD

3 7 I Read data. A falling edge on RD enables a read operation on the data bus when CS is low.
REFM 20 24 I Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be

grounded.

REFP 19 23 I Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by

the difference between the voltage applied to REFP and REFM.

WR

2 6 I Write data. A rising edge on the WR latches in configuration data when CS is low. When using

software conversion start, a rising edge on WR

also initiates an internal sampling start pulse.

When WR

is tied to ground, the ADC in nonprogrammable (hardware configuration mode).

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

_
+

Charge

Redistribution

DAC

SAR

Register

REFM

ADC Code

Control

Logic

Ain

Figure 1. Analog-to-Digital SAR Converter

The TLV1571/78 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a
simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.

sampling frequency, f

s

The TLV1571/ TLV1578 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling
frequency achievable with a given CLK frequency is:

f

s(max)

= (1/16) f

CLK

The TL V1571 and TLV1578 are software configurable. The first two MSB bits, D(9,8) are used to address which
register to set. The rest of the eight bits are used as control data bits. There are two control registers, CR0 and
CR1, that are user configurable. All of the register bits are written to the control register during write cycles. A
description of the control registers is shown in Figure 2.

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

control registers

Output =

Output =

Output =

0:
Binary

1:
2s
Complement

0:
Reserved
Bit,
Always
Write 0

0:
INT. OSC.
SLOW
1:
INT. OSC.
FAST

7h

6h

5h

STARTSEL

A1 A0 D6 D5 D4 D3 D2 D1 D0D7

Control Register Zero (CR0)

D6D7 D5 D4 D3 D2 D1 D0

Channels Swept

PROGEOC

CLKSEL SWPWDN MODESEL CHSEL(2–0)

†

0:
HARDWARE
START
(CSTART)

A(1:0)=00

1:
SOFTWARE
START

0:
INT

1:
EOC

0:
Internal
Clock

1:
External
Clock

0:
NORMAL

1:
Powerdown

0:
Single
Channel
1:
Sweep
Mode

D(2–0)

0h
1h

2h
3h
4h

0,1

0,1,2,3

0,1,2,3,4,5,

0,1,2,3,4,5,6,7

N/A
N/A
N/A

N/A

3h

2h

1h

RESERVED

Control Register One (CR1)

D6D7

‡

D3 D2 D1 D0

IF READREG = 0

OSCSPD 0 Reserved 0 Reserved OUTCODE READREG

0:
Reserved
Bit
Always
Write 0

A(1:0)=01

0:
Reserved
Bit
Always
Write 0

0:
Enable Self
Test

ACTION

1:
Enable
Register
Read back

0h

1h

2h

3h

CONVERSION result

SELF TEST 1 result

SELF TEST 2 result

Output Contents of

CR1
RESERVED
RESERVED

STEST1 STEST0

CR1.(1–0)

SELF TEST 3 result

IF READREG = 1

Output Contents of

CR0

0h

7

6

5

Single

Input

0
1

2
3
4

Output =

D5

‡

D4

‡

†

Don’t care for TLV1571

‡

When in read back mode, the values read from the control register reserved bits are don’t care.

Figure 2. Input Data Format

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

6

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detailed description (continued)

hardware configuration option

The TLV1571/TLV1578 can configure itself. This option is enabled when the WR pin is tied to ground and a
dummy RD signal is applied. The ADC is now fully configured. Zeros or default values are applied to both control
registers. The ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz, single
channel input mode, and hardware start of conversion using CSTART

.

ADC conversion modes

The TL V1571/TLV1578 provides two conversion modes and two start of conversion modes. In single channel
input mode, a single channel is continuously sampled and converted. In sweep mode (only available for the
TLV1578), a predetermined set of channels is continuously sampled and converted. Table 1 explains these
modes in more detail.

Table 1. Conversion Modes

MODES

START OF

CONVER-

SION

OPERATION

COMMENT–SET BITS

CR0.D(2–0) FOR INPUT

Single

Channel

Input

†

CR0.D3 = 0
CR1.D7 = 0

Hardware

Start

(CSTART)

CR0.D7 = 0

• Repeated conversions from a selected channel

• CSTART

falling edge to start sampling

• CSTART

rising edge to start conversion

• If in INT mode, one INT

pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion, and return high
at end of conversion.

CSTAR T rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.

Software

Start

CR0.D7 = 1

• Repeated conversions from a selected channel

• WR

rising edge to start sampling initially . Thereafter, sampling occurs at the rising

edge of RD

.

• Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INT
mode, one INT

pulse is generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.

With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.

Channel

Sweep
CR0.D3 = 1
CR1.D7 = 0

Hardware

Start

(CSTART)

CR0.D7 = 0

• One conversion per channel from a predetermined sequence of channels

• CSTART

falling edge to start sampling

• CSTART

rising edge to start conversion

• If in INT mode, one INT pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion, and return high

at end of conversion.

CSTAR T rising edge must
be applied a minimum of
5 ns before or after CLK
rising edge.

Software

Start

CR0.D7 = 1

• One conversion per channel from a sequence of channels

• WR

rising edge to start sampling

• ADC proceeds to sample next channel at rising edge of RD

. Conversion begins

after 6 clocks and lasts 10 clocks

• If in INT mode, one INT

pulse generated after each conversion

• If in EOC mode, EOC will go high to low at start of conversion and return high at
end of conversion.

With external clock, WR
and RD rising edge must be
a minimum 5 ns before or
after CLK rising edge.

†

Single channel input mode repeatedly samples and converts from the channel until WR is applied.

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

configure the device

The device can be configured by writing to control registers CR0 and CR1.

Table 2. TLV1571/TLV1578 Programming Examples

INDEX

REGISTER

D9 D8

D7D6D5D4D3D2D1D0COMMENT

EXAMPLE1

CR0 0 0 0 0 0 0 0 0 0 0 Single channel
CR1 0 1 0 0 0 0 0 1 0 0 Single Input

EXAMPLE2

CR0 0 0 0 1 1 0 1 0 1 1 Sweep mode
CR1 0 1 0 0 0 0 1 1 0 0 2’s complement output

register read back

Control data written to the TL V1571/78 can be read back from the control registers CR0 and CR1. See Figure 2.

NOTE:

Data read out of CR1 reserved bits is don’t care.

power down

The TL V1571/TLV1578 offers two power-down modes, auto power down and software power down. This device
will automatically proceed to auto power-down mode if RD is not present one clock after conversion. Software
power down is controlled directly by the userby pulling CS to DV

DD

.

Table 3. Power Down Modes

PARAMETERS/MODES AUTO POWER DOWN

SOFTWARE POWER DOWN

(CS

= DVDD)

Maximum power down dissipation current 1 mA 10 µA
Comparator Power down Power down
Clock buffer Power down Power down
Reference Active Power down
Control registers Saved Saved
Minimum power down time 1 CLK 2 CLK
Minimum resume time 1 CLK 2 CLK

self-test modes

The TL V1571/TLV1578 provides three self test modes. These modes can be used to check whether the ADC
itself is working properly without having to supply an external signal. There are three tests that are controlled
by writing to CR1(D1,D0) (see Table 4).

Table 4. Self Tests

CR1(D1,D0) SELF TEST VOLTAGE APPLIED DIGITAL OUTPUT

0h Normal, no self test applied N/A
1h VREFM applied to ADC input internally 000h
2h (VREFP–VREFM)/2 applied to ADC input internally 200h
3h VIN = VREFP applied to ADC input internally 3FFh

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

reference voltage input

The TL V1571/TLV1578 has two reference input pins: REFP and REFM. The voltage levels applied to these pins
establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading
respectively . The values of REFP , REFM, and the analog input should not exceed the positive supply or be less
than GND consistent with the specified absolute maximum ratings. The digital output is at full scale when the
input signal is equal to or higher than REFP and is at zero when the input signal is equal to or lower than REFM.

sampling/conversion

All sampling, conversion, and data output in the device are started by a trigger. This could be the RD, WR, or
CST ART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, and
CSTART signal are extremely important, since they are used to start the conversion. These edges need to stay
close to the rising edge of the external clock (if they are used as CLK). The minimum setup and hold time with
respect to the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this
is not an issue since these two edges will start the internal clock automatically. Therefore, the setup time is
always met. Software controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal
oscillator if enabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from

0.6 µs to 0.3 µs. The internal oscillator frequency is 9 MHz minimum (oscillator frequency is between 9 MHz
to 22 MHz), translating into a sampling time from 0.6 µs to 0.3 µs. Conversion begins immediately after sampling
and lasts 10 clock cycles. This is again done using the external clock input (1 MHz–20 MHz) or the internal
oscillator (9 MHz minimum) if enabled. Hardware controlled sampling, via CST ART

, begins on falling CST ART
lasts the length of the active CST AR T signal. This allows more control over the sampling time, which is useful
when sampling sources with large output impedances. On rising CSTART, conversion begins. Conversion in
hardware controlled mode also lasts 10 clock cycles. This is done using the external clock input (1 MHz–20 MHz)
or the internal oscillator (9 MHz minimum) as is the case in software controlled mode.

NOTE: tsu = setup time, th = hold time

ExtClk

WR

RD

CSTART

t

su(WRH_EXTCLKH)

≥5 ns

t

h(WRL_EXTCLKH)

≥5 ns

t

h(RDL_EXTCLKH)

≥5 ns

t

d(EXTCLK_CSTARTL)

≥5 ns

t

h(CSTARTL_EXTCLKH)

≥5 ns

t

su(CSTARTH_EXTCLKH)

≥5 ns

OR

OR

t

su(RDH_EXTCLKH)

≥5 ns

Figure 3. Trigger Timing – Software Start Mode Using External Clock

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

start of conversion mechanism

There are two ways to convert data: hardware and software. In the hardware conversion mode the ADC begins
sampling at the falling edge of CSTART and begins conversion at the rising edge of CSTART. Software start
mode ADC samples for 6 clocks, then conversion occurs for ten clocks. The total sampling and conversion
process lasts only 16 clocks in this case. If RD

is not detected during the next clock cycle, the ADC automatically

proceeds to a power down state. Data is valid on the rising edge of INT in both conversion modes.

hardware CST ART conversion

external clock

With CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CSTART and
conversion begins at the rising edge of CST AR T. At the end of conversion, EOC goes from low to high, telling
the host that conversion is ready to be read out. The external clock is active and is used as the reference at all
times. With this mode, it is required that CST ART is not applied at the rising edge of the clock (see Figure 4).

TLV1571, TLV1578

2.7 V to 5.5 V, 1-/8-CHANNEL, 10-BIT,

RARALLEL ANALOG-TO-DIGIT AL CONVERTERS

SLAS170C – MARCH 1999 – REVISED FEBRUARY 2000

10

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

•

start of conversion mechanism (continued)

CLK

CS

WR

CSTART

RD

D[0:9]

INT

EOC

Config

Data

t

su(CSL_WRL)

h(WRH_CSH)

t

(sample)

(Channel 0)

(see Note A)

t

su(DAV_WRH)

t

h(WRH_DAV)

t

c

(I/O CLKs)

su(CSL_RDL)

t

h(RDH_CSH)

t

en(RDL_DAV)

t

dis(RDH_DAV)

t

c

t

su(CSL_RDL)

t

en(RDL_DAV)

OR

Auto Powerdown

ADC ADC

t

(sample)

(Channel 0)

(see Note A)

d(CSH_CSTARTL)

t

t

t

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 4. Multichannel Input Mode Conversion – Hardware CSTART, External Clock

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C – MARCH 1999 – REVISED FEBRUARY 2000

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 11

internal clock

In single channel input mode, with CS low and WR low, data is written into the ADC. The sampling begins at the falling edge of CST AR T, and
conversion begins at the rising edge of CSTAR T . The internal clock turns on at the rising edge of CSTART. The internal clock is disabled after
each conversion.

OR

Auto Powerdown

CS

WR

CSTART

INTCLK

RD

D[0:9]

INT

EOC

Config

Data

ADC
Data

ADC
Data

t

su(CSL_WRL)

t

h(WRH_CSH)

t

d(CSH_CSTARTL)

t

(sample)

(Channel 0)
(see Note A)

t

su(DAV_WRH)

t

h(WRH_DAV)

t

c

t

su(CSL_RDL)

t

h(RDH_CSH)

t

en(RDL_DAV)

t

dis(RDH_DAV)

t

c

t

su(CSL_RDL)

t

en(RDL_DAV)

t

(STARTOSC)

t

(STARTOSC)

9

10

10

Auto Powerdown

t

c

(Channel 1)

(see Note A)

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 5. Multichannel Input Mode Conversion – Hardware CSTART, Internal Clock

TLV1571, TLV1578

2.7 V to 5.5 V, 1-/8-CHANNEL, 10-BIT,

RARALLEL ANALOG-TO-DIGIT AL CONVERTERS

SLAS170C – MARCH 1999 – REVISED FEBRUARY 2000

12

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•

software START conversion

external clock

With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. The conversion process begins 6 clocks
after sampling begins. At the end of conversion, INT goes low telling the host that conversion is ready to be read out. EOC is low during the
conversion and makes a high-to-low transition at the end of the conversion. The external clock is active and used as the reference at all times.
With this mode, WR and RD should not be applied at the rising edge of the clock (see Figure 3).

Auto Powerdown

CLK

CS

WR

RD

D[0:9]

INT

EOC

Config

Data

ADC Data ADC Data

t

su(CSL_WRL)

t

h(WRH_CSH)

t

su(DAV_WRH)

t

h(WRH_DAV)

t

c

t

su(CSL_RDL)

t

h(RDH_CSH)

t

en(RDL_DAV)

t

dis(RDH_DAV)

t

t

en(RDL_DAV)

015671516

OR

su(CSL_RDL)

04 5 15

t

(sample)

(Channel 0)

(see Note A)

t

c

t

(sample)

(Channel 1)

(see Note A)

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 6. Multichannel Input Mode Conversion – Software Start, External Clock

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C – MARCH 1999 – REVISED FEBRUARY 2000

POST OFFICE BOX 655303 DALLAS, TEXAS 75265

• 13

software START conversion (continued)

internal clock

With CS low and WR low, data is written into the ADC. Sampling begins at the rising edge of WR. Conversion begins 6 clocks after sampling
begins. The internal clock begins at the rising edge of WR. The internal clock is disabled after each conversion. Subsequent sampling begins
at the rising edge of RD.

OR

Auto Powerdown

ADC

CS

WR

RD

INTCLK

D[0:9]

INT

EOC

Config

Data

ADC
Data

t

su(CSL_WRL)

t

h(WRH_CSH)

t

su(DAV_WRH)

t

h(WRH_DAV)

t

c

t

su(CSL_RDL)

t

h(RDH_CSH)

t

en(RDL_DAV)

t

dis(RDH_DAV)

t

(STARTOSC)

t

(STARTOSC)

456 045015 15

Auto Powerdown

t

(sample)

(Channel 0)

(see Note A)

t

c

t

(sample)

(Channel 1)

(see Note A)

NOTE A: AIN for TLV1571; channels sweep according to register settings.

Figure 7. Multichannel Input Mode Conversion – Software Start, Internal Clock

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
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software START conversion (continued)
system clock source

The TL V1571/TL V1578 internally derives multiple clocks from the SYSCLK for different tasks. SYSCLK is used
for most conversion subtasks. The source of SYSCLK is programmable via control register zero bit 5. The
source of SYSCLK is changed at the rising edge of WR

of the cycle when CR0.D5 is programmed.

internal clock (CR0.D5 = 0, SYSCLK = internal OSC)

The TLV1571/TLV1578 has a built-in 10 MHz OSC. When the internal OSC is selected as the source of
SYSCLK, the internal clock starts with a delay (one half of the OSC period max) after the falling edge of the
conversion trigger (either WR, RD, or CST ART). The OSC speed can be set to 10 ± 1 MHz or 20 ± 2 MHz by
setting register bit CR1.6.

external clock (CR0.D5 = 1, SYSCLK = external clock)

The TL V1571/TLV1578 is designed to accept an external clock input (CMOS/TTL logic) with frequencies from
1 MHz to 20 MHz.

host processor interface

The TLV1571/TLV1578 provides a generic high-speed parallel interface that is compatible with
high-performance DSPs and general-purpose microprocessors. The interface includes D(0–9), INT/EOC, RD,
and WR.

output format

The data output format is unipolar (code 0 to 1023) when the device is operated in single-ended input mode.
The output code format can be either binary or twos complement by setting register bit CR1.D3.

power up and initialization

After power up, CS

must be low to begin an I/O cycle. INT/EOC is initially high. The TL V1571/TL V1578 requires
two write cycles to configure the two control registers. The first conversion after the device has returned from
the power down state may be invalid and should be disregarded.

definitions of specifications and terminology

integral nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.
The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level
1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to
the true straight line between these two points.

differential nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.
A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

zero offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the
deviation of the actual transition from that point.

gain error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition
should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual
difference between first and last code transitions and the ideal difference between first and last code transitions.

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

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software START conversion (continued)
signal-to-noise ratio + distortion (SINAD)

Signal-to-noise ratio + disortion is the ratio of the rms value of the measured input signal to the rms sum of all
other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.

effective number of bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective
number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its
measured SINAD.

total harmonic distortion (THD)

T otal harmonic distortion is the ratio of the rms sum of the first six harmonic components to the rms value of the
measured input signal and is expressed as a percentage or in decibels.

spurious free dynamic range (SFDR)

Spurious free dynamic range is the difference in dB between the rms amplitude of the input signal and the peak
spurious signal.

DSP interface

The TLV1571/TLV1578 is a 10-bit 1-/8-analog input channel analog-to-digital converter with throughput up to

1.25 MSPS at 5 V and up to 625 KSPS at 3 V. To achieve 1.25 MSPS throughout, the ADC must be clocked
at 20 MHz. Likewise to achieve 625 KSPS throughout, the ADC must be clocked at 10 MHz. The
TLV1571/ TLV1578 can be easily interfaced to microcontrollers, ASICs, and DSPs. Figure 8 shows the pin
connections to interface the TLV1571/TLV1578 to the TMS320C6x DSP.

Address
Decoder

EN

A0–A15

TMS320C6X

HW

HR

INTx

D0–D15

D0–D9

CS

WR
RD
EOC

TLV1571/78

REF

CH(1–8)

†

REFP

REFM

†

The TLV1571 has only one analog input (AIN).

Figure 8. TMS320C6x DSP Interface

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
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grounding and decoupling considerations

General practices should apply to the PCB design to limit high frequency transients and noise that are fed back
into the supply and reference lines. This requires that the supply and reference pins be sufficiently bypassed.
In most cases 0.1-µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency
range. Since their effectiveness depends largely on the proximity to the individual supply pin, they should be
placed as close to the supply pins as possible.

To reduce high frequency and noise coupling, it is highly recommended that digital and analog grounds be
shorted immediately outside the package. This can be accomplished by running a low impedance line between
DGND and AGND under the package.

TLV1571/78

100 nF

DGND

DV

DD

AV

DD

AGND

REFP

REFM

100 nF

100 nF

V

REFP

V

REFM

AV

DD

DV

DD

Figure 9. Placement for Decoupling Capacitors

power supply ground layout

Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the ADC AGND terminal to the system analog ground plane making sure that analog ground
currents are well managed.

R

s

R

i(MUX)

V

S

V

C

15 pF

Driving Source

†

TLV1571/78

C

i

V

I

VI= Input Voltage at AIN
VS= External Driving Source Voltage
Rs= Source Resistance
R

i(ADC)

= Input Resistance of ADC

R

i(MUX)

= Input Resistance (MUX on resistance)
Ci= Input Capacitance
VC= Capacitance Charging Voltage

†

Driving source requirements:

• Noise and distortion for the source must be equivalent to the resolution of the converter.

• Rs must be real at the input frequency.

R

i(ADC)

MO

AIN

Figure 10. Equivalent Input Circuit Including the Driving Source

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

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simplified analog input analysis

Using the equivalent circuit in Figure 9, the time required to charge the analog input capacitance from 0 to V

S

within 1/2 LSB, tch(1/2 LSB), can be derived as follows.
The capacitance charging voltage is given by:

Where:

R

t

= Rs + R

i

Ri = R

i(ADC)

+ R

i(MUX)

tch = Charge time

V

C(t)

+

V

S

ǒ

1–e

–tchń

RtC

i

Ǔ

The input impedance Ri is 718 Ω at 5 V , and is higher (~ 1.25 kΩ) at 2.7 V. The final voltage to 1/2 LSB is given
by:

VC (1/2 LSB) = VS – (VS/2048)

Equating equation 1 to equation 2 and solving for cycle time tc gives:

and time to change to 1/2 LSB (minimum sampling time) is:

t

ch

(1/2 LSB) = Rt × Ci × ln(2048)

VS*

ǒ

VSń

2048Ǔ+

V

S

ǒ

1–e

–tchń

RtC

i

Ǔ

Where:

ln(2048) = 7.625

Therefore, with the values given, the time for the analog input signal to settle is:

tch (1/2 LSB) = (Rs + 718 Ω) × 15 pF × ln(2048)

This time must be less than the converter sample time shown in the timing diagrams, which is 6x SCLK.

tch (1/2 LSB) ≤ 6x 1/f

(SCLK)

Therefore the maximum SCLK frequency is:

Max(f

(SCLK)

) = 6/tch (1/2 LSB) = 6/(ln(2048) × Rt × Ci)

(1)

(2)

(3)

(4)

(5)

(6)

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, GND to VCC –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range –0.3 V to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage range AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to DV

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: TLV1571C, TLV1578C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . .

TLV1571I, TLV1578I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supplies

MIN MAX UNIT

Analog supply voltage, A V

DD

2.7 5.5 V

Digital supply voltage, DV

DD

2.7 5.5 V

NOTE 1: Abs (A VDD – DVDD) < 0.5 V

analog inputs

MIN MAX UNIT

Analog input voltage, AIN AGND VREFP V

digital inputs

MIN NOM MAX UNIT

High-level input voltage, V

IH

DVDD = 2.7 V to 5.5 V 2.1 2.4 V

Low level input voltage, V

IL

DVDD = 2.7 V to 5.5 V 0.8 V

p

DVDD = 4.5 V to 5.5 V 20 MHz

Input CLK frequenc

y

DVDD = 2.7 V to 3.3 V 10 MHz
DVDD = 4.5 V to 5.5 V, f

CLK

= 20 MHz 23 ns

Pulse duration, CLK high, t

w(CLKH)

DVDD = 2.7 V to 3.3 V, f

CLK

= 10 MHz 46 ns

DVDD = 4.5 V to 5.5 V, f

CLK

= 20 MHz 23 ns

Pulse duration, CLK low, t

w

(CLKL)

DVDD = 2.7 V to 3.3 V, f

CLK

= 10 MHz 46 ns
Rise time, I/O and control, CLK, CS 50 pF output load 4
Fall time, I/O and control, CLK, CS 50 pF output load 4

ns

reference specifications

MIN NOM MAX UNIT

AVDD = 3 V 2 AV

DD

V

VREFP

AVDD = 5 V 2.5 AV

DD

V

External reference voltage

AVDD = 3 V AGND 1 V

VREFM

AVDD = 5 V AGND 2 V

VREFP – VREFM 2 AVDD–AGND V

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

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electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted)

digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Logic inputs

I

IH

High-level input current DVDD = 5 V, DVDD = 3 V, Input = DV

DD

–1 1 µA

I

IL

Low-level input current DVDD = 5 V, DVDD = 3 V, Input = 0 V –1 1 µA

C

i

Input capacitance 10 15 pF

Logic outputs

V

OH

High-level output voltage IOH = 50 µA to 0.5 mA DVDD–0.4 V

V

OL

Low-level output voltage IOL = 50 µA to 0.5 mA 0.4 V

I

OZ

High-impedance-state output current DVDD = 5 V, DVDD = 3 V, Input = DV

DD

1 µA

I

OL

Low-impedance-state output current DVDD = 5 V, DVDD = 3 V, Input = 0 V –1 µA

C

o

Output capacitance 5 pF

3 V, AVDD = DV

DD

9 10 11

Internal clock

5 V, AVDD = DV

DD

18 20 22

MHz

dc specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 Bits

Accuracy

Integral nonlinearity, INL Best fit ±0.5 ±1 LSB
Differential nonlinearity , DNL ±0.5 ±1 LSB
Missing codes 0

E

O

Offset error ±0.1% ±0.15% FSR

E

G

Gain error ±0.1% ±0.2% FSR

Analog input

p

p

AIN, AVDD = 3 V, AVDD = 5 V 15 pF

CiInput capacitance

MUX input, AVDD = 3 V, AVDD = 5 V 25 pF

I

lkg

Input leakage current V

AIN

= 0 to AV

DD

±1 µA

p

AVDD = DVDD = 3 V 240 680

riInput MUX ON resistance

AVDD = DVDD = 5 V 215 340

Ω

Voltage reference input

r

i

Input resistance 2 kΩ

C

i

Input capacitance 300 pF

Power supply

p

pp

AVDD = DVDD = 3 V, f

CLK

= 10 MHz 4 5.5 mA

Operating supply current, I

DD

+

I

REF

AVDD = DVDD = 5 V, f

CLK

= 20 MHz

7 8.5 mA

p

AVDD+DVDD = 3 V 12 17 mW

PD

Power dissipation

AVDD+DVDD = 5 V 35 43 mW

AVDD = 3 V 1 8 µA

pp

p

Software

I

DD

+

I

REF

AVDD = 5 V 2 10 µA

IPDSupply current in power-down mode

AVDD = 3 V 0.5 1 mA

Auto

I

DD

+

I

REF

AVDD = 5 V 0.5 1 mA

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
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electrical characteristics over recommended operating free-air temperature range, supply
voltages, and reference voltages (unless otherwise noted) (continued)

ac specifications, AVDD = DVDD = 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

= 100 kHz,

fs = 1.25 MSPS, AVDD = 5 V 56 60 dB

Signal-to-noise ratio, SNR

I

,

80% of FS

fs = 625 KSPS, AVDD = 3 V 58 60 dB

f

= 100 kHz,

fs = 1.25 MSPS, AVDD = 5 V 55 60 dB

Signal-to-noise ratio

+

distortion, SINAD

I

,

80% of FS

fs = 625 KSPS, AVDD = 3 V 55 60 dB

f

= 100 kHz,

fs = 1.25 MSPS, AVDD = 5 V –60 –56 dB

Total harmonic distortion, THD

I

,

80% of FS

fs = 625 KSPS, AVDD = 3 V –60 –56 dB

f

= 100 kHz,

fs = 1.25 MSPS, AVDD = 5 V 9 9.3 Bits

Effective number of bits, ENOB

I

,

80% of FS

fs = 625 KSPS, AVDD = 3 V 9 9.3 Bits

p

f

= 100 kHz,

fs = 1.25 MSPS, AVDD = 5 V –63 –56 dB

Spurious free dynamic range, SFDR

I

,

80% of FS

fs = 625 KSPS, AVDD = 3 V –63 –56 dB

Analog input

Channel-to-channel cross talk –75 dB

p

–1 dB Full-scale 0 dB input sine wave 12 18 MHz

Full-power bandwidth

–3 dB Full-scale 0 dB input sine wave 30 MHz
–1 dB –20 dB input sine wave 15 20 MHz

Small-signal bandwidth

–3 dB –20 dB input sine wave 35 MHz

p

AVDD = 4.5 V to 5.5 V 0.0625 1.25 MSPS

Sam ling rate, f

s

AVDD = 2.7 V to 3.3 V 0.0625 0.625 MSPS

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

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timing requirements, AVDD = DVDD = 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DVDD = 4.5 V to 5.5 V 50 ns

t

c

(CLK)

Cycle time, CLK

DVDD = 2.7 V to 3.3 V 100 ns

t

(sample)

Reset and sampling time 6

SYSCLK

Cycles

t

c

Total conversion time 10

SYSCLK

Cycles

t

wL(EOC)

Pulse width, end of conversion, EOC 10

SYSCLK

Cycles

t

wL(INT)

Pulse width, interrupt 1

SYSCLK

Cycles

t

(STARTOSC)

Start-up time, internal oscillator 100 ns

t

d(CSH_CSTARTL)

Delay time, CS high to CSTAR T low 10 ns

DVDD = 5 V at 50 pF 20 ns

t

en

(RDL_DAV)

Enable time, data out

DVDD = 3 V at 50 pF 40 ns
DVDD = 5 V at 50 pF 5 ns

t

dis(RDH_DAV)

Disable time, data out

DVDD = 3 V at 50 pF 10 ns

t

su(CSL_WRL)

Setup time, CS to WR 5 ns

t

h(WRH_CSH)

Hold time, CS to WR 5 ns

t

w(WR)

Pulse width, write 1

Clock

Period

t

w(RD)

Pulse width, read 1

Clock

Period

t

su(DAV_WRH)

Setup time, data valid to WR 10 ns

t

h(WRH_DAV)

Hold time, data valid to WR 5 ns

t

su(CSL_RDL)

Setup time, CS to RD 5 ns

t

h(RDH_CSH)

Hold time, CS to RD 5 ns

t

h(WRL_EXTXLKH)

Hold time WR to clock high 5 ns

t

h(RDL_EXTCLKH)

Hold time RD to clock high 5 ns

t

h(CSTARTL_EXTCLKH)

Hold time CSTAR T to clock high 5 ns

t

su(WRH_EXTCLKH)

Setup time WR high to clock high 5 ns

t

su(RDH_EXTCLKH)

Setup time RD high to clock high 5 ns

t

su(CSTARTH_EXTCLKH)

Setup time CSTAR T high to clock high 5 ns

t

d(EXTCLK_CSTARTL)

Delay time clock low to CSTART low 5 ns

NOTE: Specifications subject to change without notice.

Data valid is denoted as DAV.

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
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TYPICAL CHARACTERISTICS

Figure 11

0

100

200

300

400

500

600

700

01234567

ANALOG MUX INPUT RESISTANCE

vs

INPUT CHANNEL NUMBER

AVDD = DVDD = 2.7 V

AVDD = DVDD = 5 V

Input Channel Number

Analog MUX Resistance –

Ω

Figure 12

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

SUPPLY CURRENT

vs

FREE AIR TEMPERATURE

AVDD = DVDD = 5 V

TA – Free Air Temperature – °C

AVDD = DVDD = 3 V

I

CC

– Supply Current – mA

Figure 13

0

1

2

3

4

5

6

7

0 2 4 6 8 101214161820

SUPPLY CURRENT

vs

CLOCK FREQUENCY

f

clock

– Clock Frequency – MHz

AVDD = DVDD = 5 V

AVDD = DVDD = 3 V

I

CC

– Supply Current – mA

Figure 14

ANALOG INPUT BANDWIDTH

vs

FREQUENCY

AVDD = DVDD = 5 V,
AIN = 90% of FS,
REF = 5 V,
TA = 25°C

f – Frequency – MHz

Analog Input Bandwidth – dB

–2

–3

–4

–6

0.1 1

–1

0

1

10 100

–5

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

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TYPICAL CHARACTERISTICS

Figure 15

–1.0

–0.5

0.0

0.5

1.0

0 1023

DNL – Differential Nonlinearity – LSB

Digital Output Code

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

AVDD = DVDD = 3 V,
External Ref = 3 V,
CLK = 10 MHz,
TA = 25°C

512256 768

Figure 16

–1.0

–0.5

0.0

0.5

1.0

0 1023

INL – Integral Nonlinearity – LSB

Digital Output Code

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

AVDD = DVDD = 3 V,
External Ref = 3 V,
CLK = 10 MHz,
TA = 25°C

512256 768

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS

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TYPICAL CHARACTERISTICS

Figure 17

–1.0

–0.5

0.0

0.5

1.0

0 1023

DNL – Differential Nonlinearity – LSB

Digital Output Code

DIFFERENTIAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

AVDD = DVDD = 5 V,
External Ref = 5 V,
CLK = 20 MHz,
TA = 25

°C

512256 768

Figure 18

–1.0

–0.5

0.0

0.5

1.0

0 1023

INL – Integral Nonlinearity – LSB

Digital Output Code

INTEGRAL NONLINEARITY

vs

DIGITAL OUTPUT CODE

AVDD = DVDD = 5 V,
External Ref = 5 V,
CLK = 20 MHz,
TA = 25°C

512256 768

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

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TYPICAL CHARACTERISTICS

Figure 19

0

1

2

3

4

5

6

7

8

9

10

50 100 150 200 250

ENOB – Effective Number of Bits – BITS

f – Frequency – kHz

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

AVDD = DVDD = 3 V,
External Ref = 3 V

Figure 20

0

1

2

3

4

5

6

7

8

9

10

50 100 150 200 250 300 350 400 450 500

ENOB – Effective Number of Bits – BITS

f – Frequency – kHz

EFFECTIVE NUMBER OF BITS

vs

FREQUENCY

AVDD = DVDD = 5 V,
External Ref = 5 V

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYPICAL CHARACTERISTICS

Figure 21

–120

–100

–80

–60

–40

–20

0

0 25 50 75 100 125 150 175 200 225 250 275

Magnitude – dB

f – Frequency – kHz

FAST FOURIER TRANSFORM

vs

FREQUENCY

AIN = 200 KHz
CLK = 10 MHz
AVDD = DVDD = 3 V
External Ref = 3 V

Figure 22

–120

–100

–80

–60

–40

–20

0

0 50 100 150 200 250 300 350 400 450 500 550

Magnitude – dB

f – Frequency – kHz

FAST FOURIER TRANSFORM

vs

FREQUENCY

AIN = 200 KHz
CLK = 20 MHz
AVDD = DVDD = 5 V
External Ref = 5 V

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,

PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

27

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

38 PINS SHOWN

4040066/D 11/98

0,25

0,75
0,50

0,15 NOM

Gage Plane

6,20
NOM

8,40
7,80

32

11,10

11,10

30

Seating Plane

10,9010,90

20

0,19

19

A

0,30

38

1

PINS **

A MAX

A MIN

DIM

1,20 MAX

9,60

9,80

28

M

0,13

0°–8°

0,10

0,65

38

12,60

12,40

0,15
0,05

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-153

TLV1571, TLV1578

2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS

SLAS170C –MARCH 1999 – REVISED FEBRUARY 2000

28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

16 PINS SHOWN

4040000/C 07/96

Seating Plane

0.400 (10,15)

0.419 (10,65)

0.104 (2,65) MAX

1

0.012 (0,30)

0.004 (0,10)

A

8

16

0.020 (0,51)

0.014 (0,35)

0.293 (7,45)

0.299 (7,59)

9

0.010 (0,25)

0.050 (1,27)

0.016 (0,40)

(15,24)

(15,49)

PINS **

0.010 (0,25) NOM

A MAX

DIM

A MIN

Gage Plane

20

0.500

(12,70)

(12,95)

0.510

(10,16)

(10,41)

0.400

0.410

16

0.600

24

0.610

(17,78)

28

0.700

(18,03)

0.710

0.004 (0,10)

M

0.010 (0,25)

0.050 (1,27)

0°–8°

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-013

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