Texas Instruments TLV1549CDR, TLV1549CD, TLV1549IP, TLV1549CP, TLV1549ID Datasheet

TLV1549C, TLV1549I, TLV1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

D

3.3-V Supply Operation

D

10-Bit-Resolution Analog-to-Digital
Converter (ADC)

D

Inherent Sample and Hold Function

D

Total Unadjusted Error...±1 LSB Max

D

On-Chip System Clock

D

T erminal Compatible With TLC1549 and
TLC1549x

D

Application Report Available

D

CMOS Technology

†

description

The TLV1549C, TLV1549I, and TLV1549M are
10-bit, switched-capacitor, successive­approximation, analog-to-digital converters. The
devices have two digital inputs and a 3-state
output [chip select (CS
CLOCK), and data output (DATA OUT)] that
provide a three-wire interface to the serial port of
a host processor.

The sample-and-hold function is automatic. The
converter incorporated in the device features
differential high-impedance reference inputs that
facilitate ratiometric conversion, scaling, and
isolation of analog circuitry from logic and supply
noise. A switched-capacitor design allows low­error conversion over the full operating free-air
temperature range.

), input-output clock (I/O

D, JG, OR P PACKAGE

(TOP VIEW)

REF+

ANALOG IN

REF–

GND

NC

ANALOG IN

NC

REF–

NC

NC – No internal connection

1
2
3
4

FK PACKAGE

(TOP VIEW)

NC

3212019

4
5
6
7
8

910111213

NC

REF+

NC

NC

GND

V

8

CC

I/O CLOCK

7

DATA OUT

6
5

CS

CC

NC

V

18
17
16
15
14

CS

NC

NC
I/O CLOCK
NC
DATA OUT
NC

The TLV1549C is characterized for operation from 0°C to 70°C. The TLV1549I is characterized for operation
from –40°C to 85°C. The TLV1549M is characterized for operation over the full military temperature range of
–55°C to 125°C.

AVAILABLE OPTIONS

PACKAGE

T

A

0°C to 70°C TLV1549CD — — TLV1549CP

–40°C to 85°C TLV1549ID — — TLV1549IP

–55°C to 125°C — TLV1549MFK TLV1549MJG —

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

Interfacing the TLV1549 10-Bit Serial-Out ADC to Popular 3.3-V Microcontrollers (SLAA005)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SMALL OUTLINE

(D)

CHIP CARRIER

(FK)

CERAMIC DIP

(JG)

Copyright  1995, Texas Instruments Incorporated

PLASTIC DIP

(P)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

ANALOG IN

Ci = 60 pF TYP
(equivalent input
capacitance)

functional block diagram

ANALOG IN

5 MΩ TYP

REF+ REF–

31

10-Bit

Analog-to-Digital

Converter

(switched capacitors)

10

CS

2

7
5

ANALOG IN

I/O CLOCK

Terminal numbers shown are for the D, JG, and P packages only .

Sample and

Hold

System Clock,
Control Logic,

Output

Data

Register

and I/O

Counters

10

10-to-1 Data
Selector and

Driver

4

6

DATA OUT

2

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I/O

DESCRIPTION

TLV1549C, TLV1549I, TLV1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

Terminal Functions

TERMINAL

NAME NO.

ANALOG IN 2 I Analog input. The driving source impedance should be ≤ 1 kΩ . The external driving source to ANALOG IN should

CS 5 I Chip select. A high-to-low transition on CS resets the internal counters and controls and enables DATA OUT and

DATA OUT 6 O This 3-state serial output for the A/D conversion result is in the high-impedance state when CS is high and active

GND 4 I The ground return for internal circuitry . Unless otherwise noted, all voltage measurements are with respect to GND.
I/O CLOCK 7 I The input/output clock receives the serial I/O CLOCK input and performs the following three functions:

REF+ 1 I The upper reference voltage value (nominally VCC) is applied to REF+. The maximum input voltage range is

REF– 3 I The lower reference voltage value (nominally ground) is applied to this REF–.
V

CC

8 I Positive supply voltage

have a current capability ≥ 10 mA.

I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system clock. A low-to-high
transition disables I/O CLOCK within a setup time plus two falling edges of the internal system clock.

when CS
the logic level corresponding to the MSB value of the previous conversion result. The next falling edge of I/O
CLOCK drives DATA OUT to the logic level corresponding to the next most significant bit, and the remaining bits
are shifted out in order with the LSB appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge
of I/O CLOCK, DAT A OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks
produce zeroes as the unused LSBs.

determined by the difference between the voltage applied to REF+ and the voltage applied to REF–.

is low. With a valid chip select, DATA OUT is removed from the high-impedance state and is driven to

1) On the third falling edge of I/O CLOCK, the analog input voltage begins charging the capacitor array and
continues to do so until the tenth falling edge of I/O CLOCK.

2) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.

3) It transfers control of the conversion to the internal state controller on the falling edge of the tenth clock.

detailed description

With chip select (CS) inactive (high), the I/O CLOCK input is initially disabled and DATA OUT is in the high­impedance state. When the serial interface takes CS
enabling of I/O CLOCK and the removal of DA TA OUT from the high-impedance state. The serial interface then
provides the I/O CLOCK sequence to I/O CLOCK and receives the previous conversion result from DA T A OUT .
I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.
The first ten I/O clocks provide the control timing for sampling the analog input.

There are six basic serial interface timing modes that can be used with the TLV1549. These modes are
determined by the speed of I/O CLOCK and the operation of CS
(1) a fast mode with a 10-clock transfer and CS
transfer and CS

active (low) continuously , (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high)

inactive (high) between transfers, (2) a fast mode with a 10-clock

between transfers, (4) a fast mode with a 16-bit transfer and CS
an 1 1- to 16-clock transfer and CS
and CS

active (low) continuously.

inactive (high) between transfers, and (6) a slow mode with a 16-clock transfer

The MSB of the previous conversion appears on DA T A OUT on the falling edge of CS
mode 5, within 21 µs from the falling edge of the tenth I/O CLOCK in mode 2 and mode 4, and following the
16th clock falling edge in mode 6. The remaining nine bits are shifted out on the next nine falling edges of the
I/O CLOCK. T en bits of data are transmitted to the host serial interface through DA T A OUT . The number of serial
clock pulses used also depends on the mode of operation, but a minimum of ten clock pulses is required for
conversion to begin. On the tenth clock falling edge, the internal logic takes DA TA OUT low to ensure that the
remaining bit values are zero if the I/O CLOCK transfer is more than ten clocks long.

T able 1 lists the operational modes with respect to the state of CS
can be used, and the timing on which the MSB of the previous conversion appears at the output.

active (low), the conversion sequence begins with the

as shown in Table 1. These modes are:

active (low) continuously , (5) a slow mode with

in mode 1, mode 3, and

, the number of I/O serial transfer clocks that

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TLV1549C, TLV1549I, TLV1549M

Fast Modes

Slow Modes

10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

Table 1. Mode Operation

MODES CS

Mode 1 High between conversion cycles 10 CS falling edge Figure 6
Mode 2 Low continuously 10 Within 21 µs Figure 7
Mode 3 High between conversion cycles 11 to 16
Mode 4 Low continuously 16
Mode 5 High between conversion cycles 11 to 16
Mode 6 Low continuously 16

†

This timing also initiates serial-interface communication.

‡

No more than 16 clocks should be used.

NO. OF

I/O CLOCKS

‡

‡

‡

‡

MSB AT DATA OUT

CS falling edge Figure 8
Within 21 µs Figure 9
CS falling edge Figure 10
16th clock falling edge Figure 11

†

TIMING

DIAGRAM

All the modes require a minimum period of 21 µs after the falling edge of the tenth I/O CLOCK before a new
transfer sequence can begin. During a serial I/O CLOCK data transfer, CS
CLOCK input is enabled. When CS

is toggled between data transfers (modes 1, 3, and 5), the transitions at CS

must be active (low) so that the I/O

are recognized as valid only if the level is maintained for a minimum period of 1.425 µs after the transition. If
the transfer is more than ten I/O clocks (modes 3, 4, 5, and 6), the rising edge of the eleventh clock must occur
within 9.5 µs after the falling edge of the tenth I/O CLOCK; otherwise, the device could lose synchronization with
the host serial interface and CS

has to be toggled to restore proper operation.

fast modes

The device is in a fast mode when the serial I/O CLOCK data transfer is completed within 21 µs from the falling
edge of the tenth I/O CLOCK. With a 10-clock serial transfer, the device can only run in a fast mode.

mode 1: fast mode, CS inactive (high) between transfers, 10-clock transfer

In this mode, CS is inactive (high) between serial I/O-CLOCK transfers and each transfer is ten clocks long. The
falling edge of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified delay time.

of CS
Also, the rising edge of CS

begins the sequence by removing DA TA OUT from the high-impedance state. The rising edge

disables I/O CLOCK within a setup time plus two falling edges of the internal system

clock.

mode 2: fast mode, CS active (low) continuously, 10-clock transfer

In this mode, CS is active (low) between serial I/O-CLOCK transfers and each transfer is ten clocks long. After
the initial conversion cycle, CS

is held active (low) for subsequent conversions. Within 21 µs after the falling

edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.

mode 3: fast mode, CS inactive (high) between transfers, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O-CLOCK transfers and each transfer can be 1 1 to 16 clocks
long. The falling edge of CS
rising edge of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS

begins the sequence by removing DA T A OUT from the high-impedance state. The

disables I/O CLOCK within a setup time plus two falling edges of the

internal system clock.

mode 4: fast mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O-CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS

is held active (low) for subsequent conversions. Within 21 µs after

the falling edge of the tenth I/O CLOCK, the MSB of the previous conversion appears at DATA OUT.

slow modes

In a slow mode, the serial I/O CLOCK data transfer is completed after 21 µs from the falling edge of the tenth
I/O CLOCK.

4

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TLV1549C, TLV1549I, TLV1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

mode 5: slow mode, CS inactive (high) between transfers, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O-CLOCK transfers and each transfer can be 1 1 to 16 clocks
long. The falling edge of CS
rising edge of CS
delay time. Also, the rising edge of CS
internal system clock.

ends the sequence by returning DA T A OUT to the high-impedance state within the specified

mode 6: slow mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O-CLOCK transfers and each transfer must be exactly 16 clocks
long. After the initial conversion cycle, CS
the sixteenth I/O CLOCK then begins each sequence by removing DA TA OUT from the low state, allowing the
MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next
16-clock transfer initiated by the serial interface.

analog input sampling

Sampling of the analog input starts on the falling edge of the third I/O CLOCK, and sampling continues for seven
I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK.

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S
This action charges all the capacitors to the input voltage.

begins the sequence by removing DA T A OUT from the high-impedance state. The

disables I/O CLOCK within a setup time plus two falling edges of the

is held active (low) for subsequent conversions. The falling edge of

switch and all ST switches simultaneously .

C

In the next phase of the conversion process, all ST and SC switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector
looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half V
the output register and the 512-weight capacitor is switched to REF–. If the voltage at the summing node is less
than the trip point of the threshold detector, a bit 1 is placed in the register and this 512-weight capacitor remains
connected to REF+ through the remainder of the successive-approximation process. The process is repeated
for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are determined.

With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to determine the bits from MSB to LSB.

), a bit 0 is placed in

CC

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5

TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

S

C

Threshold

Detector

512

NODE 512

REF–

V

REF+

REF– REF– REF– REF– REF– REF – REF – REF–

S

T

I

REF+ REF+ REF+ REF+ REF+ REF+

S

T

S

T

S

T

S

T

S

T

S

T

S

1124816128256

T

S

T

Figure 1. Simplified Model of the Successive-Approximation System

chip-select operation

The trailing edge of CS
A high-to-low transition on CS

starts all modes of operation, and CS can abort a conversion sequence in any mode.

within the specified time during an ongoing cycle aborts the cycle, and the device
returns to the initial state (the contents of the output data register remain at the previous conversion result).
Exercise care to prevent CS

from being taken low close to completion of conversion because the output data

may be corrupted.

reference voltage inputs

There are two reference inputs used with the TL V1549: REF+ and REF–. These voltage values establish the
upper and lower limits of the analog input to produce a full-scale and zero reading, respectively . The values of
REF+, REF–, and the analog input should not exceed the positive supply or be lower than GND consistent with
the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or
higher than REF+ and at zero when the input signal is equal to or lower than REF–.

To Output
Latches

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, V
Output voltage range, V
Positive reference voltage, V
Negative reference voltage, V

Peak input current (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to ground with REF– and GND wired together (unless otherwise noted).

6

(see Note 1): TLV1549C –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

TLV1549I –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV1549M –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

–0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

V

ref+

–0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ref–

: TLV1549C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

TLV1549I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLV1549M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CC

+ 0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

TLV1549C, TLV1549I, TLV1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V
Positive reference voltage, V
Negative reference voltage, V
Differential reference voltage, V
Analog input voltage (see Note 2) 0 V
High-level control input voltage, V
Low-level control input voltage, V
Clock frequency at I/O CLOCK (see Note 3) 0 2.1 MHz
Setup time, CS low before first I/O CLOCK↑, t
Hold time, CS low after last I/O CLOCK↓, t
Pulse duration, I/O CLOCK high, t
Pulse duration, I/O CLOCK low, t
Transition time, I/O CLOCK, t
Transition time, CS, t

Operating free-air temperature, T

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1 111111111), while input voltages less than that applied

CC

(see Note 2) V

ref+

(see Note 2) 0 V

ref–

– V

ref+

IH

IL

wH(I/O)

wL(I/O)

(see Note 5 and Figure 5) 1 µs

t(I/O)

t(CS)

A

to REF– convert as all zeros (0000000000). The TLV1549 is functional with reference voltages down to 1 V (V
the electrical specifications are no longer applicable.

3. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V), at least one I/O CLOCK rising edge (≥ 2 V) must occur
within 9.5 µs.

4. To minimize errors caused by noise at CS
clock after CS
CS

setup time has elapsed.

5. This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of
normal room temperature, the device functions with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

↓ before responding to the I/O CLOCK. Therefore, no attempt should be made to clock out the data until the minimum

(see Note 2) 2.5 V

ref–

VCC = 3 V to 3.6 V 2 V
VCC = 3 V to 3.6 V 0.6 V

(see Note 4) 1.425 µs

su(CS)

h(CS)

TLV1549C 0 70 °C
TLV1549I –40 85 °C

TLV1549M –55 125 °C

, the internal circuitry waits for a setup time plus two falling edges of the internal system

3 3.3 3.6 V

CC

ref +

+0.2 V

CC

10 µs

– V

); however,

ref–

CCVCC

0 ns
190 ns
190 ns

V

V

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7

TLV1549C, TLV1549I, TLV1549M

VOHHigh-level output voltage

V

VOLLow-level output voltage

V

IOZOff-state (high-impedance-state) output current

A

Analog input leakage current

A

CiInput capacitance

pF

10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

electrical characteristics over recommended operating free-air temperature range,
V

= V

CC

I

IH

I

IL

I

CC

†

All typical values are at VCC = 3.3 V, TA = 25°C.

= 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)

ref+

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

p

p

p

High-level input current VI = V
Low-level input current VI = 0 –0.005 –2.5 µA
Operating supply current CS at 0 V 0.4 2.5 mA

p

Maximum static analog reference current into REF+ V

p

p

p

TLV1549C, I (Analog) During sample cycle 30 55
TLV1549M, (Analog) During sample cycle 30
TLV1549C, I (Control) 5 15
TLV1549M, (Control) 5

VCC = 3 V, IOH = –1.6 mA 2.4
VCC = 3 V to 3.6 V, IOH = –20 µA VCC–0.1
VCC = 3 V, IOL = 1.6 mA 0.4
VCC = 3 V to 3.6 V, IOL = 20 µA 0.1
VO = VCC, CS at V
VO = 0, CS at V

CC

VI = V

CC

VI = 0 –1

= VCC, V

ref+

CC
CC

0.005 2.5 µA

= GND 10 µA

ref–

10

–10

µ

1

µ

p

8

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TLV1549C, TLV1549I, TLV1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

operating characteristics over recommended operating free-air temperature range,
V

= V

CC

t

conv

t

c

t

v

t

d(I/O-DATA)

t

, t

PZH

PZL

t

, t

PHZ

PLZ

t

r(bus)

t

f(bus)

t

d(I/O-CS)

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

= 3 V to 3.6 V, I/O CLOCK frequency = 2.1 MHz

ref+

PARAMETER TEST CONDITIONS MIN MAX UNIT

Linearity error (see Note 6) ±1 LSB
Zero error (see Note 7) See Note 2 ±1 LSB
Full-scale error (see Note 7) See Note 2 ±1 LSB
Total unadjusted error (see Note 8) ±1 LSB
Conversion time See Figures 6–11 21 µs

21

ref+

+10 I/O
CLOCK
periods

– V

ref–

µs

); however,

Total cycle time (access, sample, and conversion)

Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 5 10 ns
Delay time, I/O CLOCK↓ to DATA OUT valid See Figure 5 240 ns
Enable time, CS↓ to DATA OUT (MSB driven) See Figure 3 1.3 µs
Disable time, CS↑ to DATA OUT (high impedance) See Figure 3 180 ns
Rise time, data bus See Figure 5 300 ns
Fall time, data bus See Figure 5 300 ns
Delay time, 10th I/O CLOCK↓ to CS↓ to abort conversion (see Note10) 9 µs

to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V
the electrical specifications are no longer applicable.

6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

7. Zero error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the dif ference
between 1111111111 and the converted output for full-scale input voltage.

8. Total unadjusted error comprises linearity, zero, and full-scale errors.

9. I/O CLOCK period = 1/(I/O CLOCK frequency). Sampling begins on the falling edge of the third I/O CLOCK, continues for seven
I/O CLOCK periods, and ends on the falling edge of the tenth I/O CLOCK (see Figure 5).

10. Any transitions of CS
the internal clock (1.425 µs) after the transition.

are recognized as valid only if the level is maintained for a minimum of a setup time plus two falling edges of

See Figures 6–11
and Note 9

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9

TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

DATA OUT

CS

12 kΩ

V

CC

RL = 2.18 kΩ

Test Point

DATA OUT

CL = 100 pF

Figure 2. Load Circuit

CS

t

PZH

, t

0.8 V

PZL

2.4 V

0.4 V

2 V

t

PHZ
90%
10%

, t

PLZ

Figure 3. DATA OUT to Hi-Z Voltage Waveforms

2 V

0.8 V

I/O CLOCK

t

su(CS)

0.8 V

First

Clock

Last

Clock

0.8 V

Figure 4. CS to I/O CLOCK Voltage Waveforms

t

I/O CLOCK

t

d(I/O-DATA)

DATA OUT

t

t(I/O)

2 V

0.8 V

t

v

2.4 V

0.4 V

I/O CLOCK Period

2.4 V

0.4 V

t

r(bus)

2 V

0.8 V

, t

t(I/O)

0.8 V

f(bus)

Figure 5. I/O CLOCK and DATA OUT Voltage Waveforms

t

h(CS)

10

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ÏÏ

ÏÏ

TLV1549C, TLV1549I, TLV1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

(see Note A)

CS

I/O

CLOCK

DATA

OUT

CS

(see Note A)

I/O

CLOCK

DATA

OUT

12345678910 1

Sample Cycle B

MSB LSB

Initialize

Previous Conversion Data

Figure 6. Timing for 10-Clock Transfer Using CS

Must Be High on Power Up

12345678910 1

Sample Cycle B

MSB LSB

Initialize

Previous Conversion Data

Hi-Z State

A/D

Conversion

Interval

(≤ 21 µs)

Low Level

A/D Conversion

(≤ 21 µs)

Initialize

Interval

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

See Note B

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Initialize

Figure 7. Timing for 10-Clock Transfer Not Using CS

See Note C

CS

(see Note A)

I/O

CLOCK

DATA

OUT

12345678910 1

Sample Cycle B

MSB LSB

Initialize

Previous Conversion Data

11 16

Low

Level

A/D

Conversion

Interval

(≤ 21 µs)

Hi-Z

Initialize

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Figure 8. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed Within 21 µs)

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS
time has elapsed.

B. A low-to-high transition of CS

clock.

C. The first I/O CLOCK must occur after the end of the previous conversion.

↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

PARAMETER MEASUREMENT INFORMATION

(see Note A)

CLOCK

DATA

OUT

Figure 9. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed W ithin 21 µs)

(see Note A)

CS

I/O

CLOCK

DATA

OUT

CS

I/O

Initialize

Initialize

Must Be High on Power Up

12345678910 1

Sample Cycle B

MSB LSB

12345678910 1

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

MSB LSB

Previous Conversion Data

Sample Cycle B

Previous Conversion Data

14 15 16

Low Level

A/D Conversion

Interval

(≤ 21 µs)

11

See Note B

Low

Level

A/D

Conversion

Interval

(≤ 21 µs)

See Note C

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Initialize

16

Hi-Z State

Initialize

B9

Figure 10. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Completed After 21 µs)

(see Note A)

CS

I/O

CLOCK

DATA

OUT

Initialize

Must Be High on Power Up

12345678910 1

Sample Cycle B

MSB LSB

Previous Conversion Data

A/D Conversion Interval

14 15 16

See Note B

Low Level

(≤ 21 µs)

See Note C

B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Figure 11. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Completed After 21 µs)

NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal system

clock after CS
time has elapsed.

B. A low-to-high transition of CS

clock.

C. The first I/O CLOCK must occur after the end of the previous conversion.

↓ before responding to the I/O CLOCK. No attempt should be made to clock out the data until the minimum CS setup

disables I/O CLOCK within a maximum of a setup time plus two falling edges of the internal system

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV1549C, TLV1549I, TLV1549M

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

APPLICATION INFORMATION

1111111111

See Notes A and B

1111111110

1111111101

1000000001

1000000000

0111111111

Digital Output Code

V

0000000010

0000000001

0000000000

0 0.006 1.5315 1.5345 1.5375

NOTES: A. This curve is based on the assumption that V

to 1 (VZT) is 0.0015 V and the transition to full scale (VFT) is 3.0675 V. 1 LSB = 3 mV.

B. The full-scale value (VFS) is the step whose nominal midstep value has the highest absolute value. The zero-scale value (VZS) is

the step whose nominal midstep value equals zero.

VZT = VZS + 1/2 LSB

ZS

0.003

0.0015
VI – Analog Input Voltage – V

ref+

and V

V

FS

VFT = VFS – 1/2 LSB

3.066 3.069 3.072

3.0675

have been adjusted so that the voltage at the transition from digital 0

ref–

1023

1022

1021

513

512

511

2

1

0

Step

Analog Input ANALOG IN

5-V DC Regulated

To Source

Ground

2

1

3

REF+

REF–

Figure 12. Ideal Conversion Characteristics

TLV1549

5

CS

I/O CLOCK

DATA OUT

GND

4

7

Processor

6

Figure 13. Typical Serial Interface

Control

Circuit

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13

TLV1549C, TLV1549I, TLV1549M
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL

SLAS071C – JANUARY 1993 – REVISED MARCH 1995

APPLICATION INFORMATION

simplified analog input analysis

Using the equivalent circuit in Figure 14, the time required to charge the analog input capacitance from 0 to V
within 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

–tcń

RtC

VC+

ǒ

V

1–e

S

i

Ǔ

where

= Rs + r

R

t

i

The final voltage to 1/2 LSB is given by

(1/2 LSB) = VS – (VS/2048)

C

Equating equation 1 to equation 2 and solving for time t

–tcń

RtC

VS*ǒVSń

2048Ǔ+

ǒ

V

1–e

S

i

Ǔ

gives

c

and

t

(1/2 LSB) = Rt × Ci × ln(2048) (4)

c

Therefore, with the values given the time for the analog input signal to settle is

t

(1/2 LSB) = (Rs + 1 kΩ) × 60 pF × ln(2048)

c

This time must be less than the converter sample time shown in the timing diagrams.

S

(1)

(2)V

(3)

(5)

Driving Source

†

Driving source requirements:

• Noise and distortion for the source must be equivalent to the
resolution of the converter.

• Rs must be real at the input frequency.

†

R

s

V

V

S

VI= Input Voltage at ANALOG IN
VS= External Driving Source Voltage
Rs= Source Resistance
ri= Input Resistance
Ci= Equivalent Input Capacitance

I

r

i

1 kΩ MAX

TLV1549

V

C

C
50 pF MAX

i

Figure 14. Equivalent Input Circuit Including the Driving Source

14

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