Extremely Low Change on Offset Voltage
With Temperature . . . 0.003 µV/°C Typ
D
Low Input Offset Current
500 pA Max at T
D
AVD. . . 135 dB Min
D
CMRR and k
D
Single-Supply Operation
D
Common-Mode Input Voltage Range
SVR
= – 55°C to 125°C
A
. . . 120 dB Min
Includes the Negative Rail
D
No Noise Degradation With External
Capacitors Connected to V
DD–
description
The TLC2652 and TLC2652A are high-precision
chopper-stabilized operational amplifiers using
Texas Instruments Advanced LinCMOS
process. This process in conjunction with unique
chopper-stabilization circuitry produces opera
tional amplifiers whose performance matches or
exceeds that of similar devices available today.
Chopper-stabilization techniques make possible
extremely high dc precision by continuously
nulling input offset voltage even during variation in
temperature, time, common-mode voltage, and
power supply voltage. In addition, low-frequency
noise voltage is significantly reduced. This high
precision, coupled with the extremely high input
impedance of the CMOS input stage, makes the
TLC2652 and TLC2652A an ideal choice for
low-level signal processing applications such as
strain gauges, thermocouples, and other
transducer amplifiers. For applications that
require extremely low noise and higher usable
bandwidth, use the TLC2654 or TLC2654A
device, which has a chopping frequency of
10 kHz.
D008, JG, OR P PACKAGE
(TOP VIEW)
C
V
DD–
D014, J, OR N PACKAGE
V
NC
NC
IN–
NC
IN+
NC – No internal connection
1
XA
IN–
2
IN+
3
4
(TOP VIEW)
C
1
XB
C
2
XA
NC
3
IN–
4
IN+
5
NC
6
7
DD–
FK PACKAGE
(TOP VIEW)
XA
XB
V
V
3212019
4
5
6
7
8
910111213
NC
DD–
V
8
7
6
5
14
13
12
11
10
9
8
INT/EXT
NC
NC
C RETURN
C
XB
V
DD+
OUT
CLAMP
INT/EXT
CLK IN
CLK OUT
V
DD+
OUT
CLAMP
C RETURN
CLK IN
CLK OUT
18
NC
17
V
16
DD+
NC
15
OUT
14
CLAMP
The TLC2652 and TLC2652A input common-mode range includes the negative rail, thereby providing superior
performance in either single-supply or split-supply applications, even at power supply voltage levels as low as
±1.9 V.
Two external capacitors are required for operation of the device; however , the on-chip chopper-control circuitry
is transparent to the user. On devices in the 14-pin and 20-pin packages, the control circuitry is made accessible
to allow the user the option of controlling the clock frequency with an external frequency source. In addition, the
clock threshold level of the TLC2652 and TLC2652A requires no level shifting when used in the single-supply
configuration with a normal CMOS or TTL clock input.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Innovative circuit techniques are used on the TLC2652 and TLC2652A to allow exceptionally fast overload
recovery time. If desired, an output clamp pin is available to reduce the recovery time even further.
The device inputs and output are designed to withstand –100-mA surge currents without sustaining latch-up.
Additionally the TLC2652 and TLC2652A incorporate internal ESD-protection circuits that prevent functional
failures at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.2; however, care should be
exercised in handling these devices as exposure to ESD may result in degradation of the device parametric
performance.
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized
for operation from –40°C to 85°C. The Q-suffix devices are characterized for operation from –40°C to125°C.
The M-suffix devices are characterized for operation over the full military temperature range of –55°C to125°C.
The D008 and D014 packages are available taped and reeled. Add R suffix to the device type (e.g., TLC2652AC-8DR). Chips are tested at 25°C.
CHIP
FORM
(Y)
TLC2652Y
—
—
functional block diagram
V
DD+
7
Clamp
3
IN+
IN–
2
B
Main
B
A
+
–
Null
AB
C
XA
4
V
DD–
8
C RETURN
Pin numbers shown are for the D (14 pin), JG, and N packages.
+
–
C
XB
Circuit
C
IC
A
Compensation-
Biasing
Circuit
External Components
5
6
CLAMP
OUT
DISTRIBUTION OF TLC2652
INPUT OFFSET VOLTAGE
36
150 Units Tested From 1 Wafer Lot
32
V
= ±5 V
DD±
TA = 25°C
28
N Package
24
20
16
12
8
Percentage of Units – %
4
0
–3–2–10123
VIO – Input Offset Voltage – µV
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2652, TLC2652A, TLC2652Y
Advanced LinCMOS PRECISION CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS019C – SEPTEMBER 1988 – REVISED FEBRUARY 1999
TLC2652Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC2652C. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
80
(13)
(14)
(1)
(2)
(12)(11)(10)(9)
90
(8)
(7)(5)(4)
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (7) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
FOR THE PINOUT, SEE THE FUNCTIONAL
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage V
Supply voltage V
Differential input voltage, V
Input voltage, V
Voltage range on CLK IN and INT/EXT
Input current, I
Output current, I
Duration of short-circuit current at (or below) 25°C (see Note 3) unlimited. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or P package 260°C. . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JG package 300°C. . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between V
2. Differential voltages are at IN+ with respect to IN–.
3. The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum
dissipation rating is not exceeded.
has no bearing on testing or nontesting of other parameters.
f = 10 Hz25°C9494140
f = 1 kHz
f = 0 to 1 Hz25°C0.80.8
f = 0 to 10 Hz
f = 10 kHz
RL = 10 kΩ,
CL = 100 pF
RL = 10 kΩ,
CL = 100 pF
=
= 100 pF
=
,
A
25°C22.822.8
Full range1.41.4
25°C2.33.12.33.1
Full range1.71.7
25°C232335
25°C2.82.8
25°C1.91.9MHz
25°C48°48 °
MINTYPMAXMINTYPMAX
= ±5 V
DD±
TLC2652ITLC2652AI
n
z
µ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
A
V
g
V
Full range
0.003
0.03∗0.003
0.03
∗
V/°C
IIOInput offset current
pA
IIBInput bias current
pA
C
t
5to5
ICR
voltage range
S
g
V
R
See Note 5
V
V
g
R
10 kΩ
See Note 5
V
A
gg
V
R
kΩ
dB
Clamp on-state current
V
V
A
Clamp off-state current
R
100 kΩ
pA
CMRR
j
V
V
dB
k
ygj
dB
IDDSupply current
V
0
No load
mA
TLC2652, TLC2652A, TLC2652Y
Advanced LinCMOS PRECISION CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS019C – SEPTEMBER 1988 – REVISED FEBRUARY 1999
electrical characteristics at specified free-air temperature, VDD± = ±5 V (unless otherwise noted)
PARAMETERTEST CONDITIONS
Input offset voltage
IO
(see Note 7)
α
V
f
ch
∗
On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
Full range is –40° to 125°C for Q suffix, –55° to 125°C for M suffix.
NOTES: 4. Typical values are based on the input offset voltage shift observed through 168 hours of operating life test at TA = 150°C extrapolated
Temperature coefficient of
VIO
input offset voltage
Input offset voltage
long-term drift (see Note 4)
p
p
ICR
OM+
OM–
VD
SVR
ommon-mode inpu
Maximum positive peak
output voltage swing
Maximum negative peak
output voltage swing
Large-signal differential
voltage amplification
Internal chopping frequency25°C450450Hz
p
p
Common-mode rejection
ratio
Supply-voltage rejection
ratio (∆V
pp
at TA = 25° using the Arrhenius equation and assuming an activation energy of 0.96 eV.
5. Output clamp is not connected.
7. This parameter is not production tested. Thermocouple effects preclude measurement of the actual VIO of these devices in high
speed automated testing. VIO is measured to a limit determined by the test equipment capability at the temperature extremes. The
test ensures that the stabilization circuitry is performing properly.
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2652, TLC2652A, TLC2652Y
Advanced LinCMOS PRECISION CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS019C – SEPTEMBER 1988 – REVISED FEBRUARY 1999
TYPICAL CHARACTERISTICS
PHASE MARGIN
vs
FREE-AIR TEMPERATURE
50°
48°
46°
44°
m
φ
om – Phase Margin
42°
V
= ±5 V
DD±
RL = 10 kΩ
CL = 100 pF
40°
–75050
–50 –25
TA – Free-Air Temperature – ° C
1001252575
Figure 31
†
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
60°
50°
40°
30°
m
20°
φ
om – Phase Margin
10°
0°
0200400600
†
PHASE MARGIN
vs
LOAD CAPACITANCE
CL – Load Capacitance – pF
Figure 32
V
= ±5 V
DD±
RL = 10 kΩ
TA = 25°C
8001000
APPLICATION INFORMATION
capacitor selection and placement
The two important factors to consider when selecting external capacitors CXA and CXB are leakage and
dielectric absorption. Both factors can cause system degradation, negating the performance advantages
realized by using the TLC2652.
Degradation from capacitor leakage becomes more apparent with the increasing temperatures. Low-leakage
capacitors and standoffs are recommended for operation at T
recommended around the capacitor connections on both sides of the printed circuit board to alleviate problems
caused by surface leakage on circuit boards.
Capacitors with high dielectric absorption tend to take several seconds to settle upon application of power, which
directly affects input offset voltage. In applications where fast settling of input offset voltage is needed, it is
recommended that high-quality film capacitors, such as mylar, polystyrene, or polypropylene, be used. In other
applications, however, a ceramic or other low-grade capacitor can suffice.
Unlike many choppers available today , the TLC2652 is designed to function with values of C
range of 0.1 µF to 1 µF without degradation to input offset voltage or input noise voltage. These capacitors
should be located as close as possible to the C
many choppers, connecting these capacitors to V
XA
and C
DD–
pins and returned to either V
XB
causes degradation in noise performance. This problem
The TLC2652 has an internal clock that sets the chopping frequency to a nominal value of 450 Hz. On 8-pin
packages, the chopping frequency can only be controlled by the internal clock; however, on all 14-pin packages
and the 20-pin FK package, the device chopping frequency can be set by the internal clock or controlled
externally by use of the INT/EXT
If external clocking is desired, connect INT/EXT
trip point is 2.5 V above the negative rail; however, CLK IN can be driven from the negative rail to 5 V above
the negative rail. If this level is exceeded, damage could occur to the device unless the current into CLK IN is
limited to ±5 mA. When operating in the single-supply configuration, this feature allows the TLC2652 to be driven
directly by 5-V TTL and CMOS logic. A
divide-by-two frequency divider interfaces with
CLK IN and sets the clock chopping frequency.
The duty cycle of the external is not critical but
should be kept between 30% and 60%.
overload recovery/output clamp
When large differential input voltage conditions
are applied to the TLC2652, the nulling loop
attempts to prevent the output from saturating by
driving C
levels. Once the overdrive condition is removed,
a period of time is required to allow the built-up
charge to dissipate. This time period is defined as
overload recovery time (see Figure 33). Typical
overload recovery time for the TLC2652 is
significantly faster than competitive products;
however, if required, this time can be reduced
further by use of internal clamp circuitry
accessible through CLAMP if required.
and CXB to internally-clamped voltage
XA
and CLK IN pins. T o use the internal 450-Hz clock, no connection is necessary .
to V
and the external clock to CLK IN. The external clock
DD–
0
V
= ±5 V
DD±
TA = 25°C
–5
O
V
0
I
–50
VI – Input Voltage – mV VO – Output Voltage – V
V
0 10203040
t – Time – ms
50 6070 80
Figure 33. Overload Recovery
The clamp is a switch that is automatically activated when the output is approximately 1 V from either supply
rail. When connected to the inverting input (in parallel with the closed-loop feedback resistor), the closed-loop
gain is reduced, and the TLC2652 output is prevented from going into saturation. Since the output must source
sink current through the switch (see Figure 7), the maximum output voltage swing is slightly reduced.
thermoelectric effects
To take advantage of the extremely low offset voltage drift of the TLC2652, care must be taken to compensate
for the thermoelectric effects present when two dissimilar metals are brought into contact with each other (such
as device leads being soldered to a printed circuit board). Dissimilar metal junctions can produce thermoelectric
voltages in the range of several microvolts per degree Celsius (orders of magnitude greater than the 0.01-µV/°C
typical of the TLC2652).
To help minimize thermoelectric effects, careful attention should be paid to component selection and
circuit-board layout. Avoid the use of nonsoldered connections (such as sockets, relays, switches, etc.) in the
input signal path. Cancel thermoelectric effects by duplicating the number of components and junctions in each
device input. The use of low-thermoelectric-coefficient components, such as wire-wound resistors, is also
beneficial.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2652, TLC2652A, TLC2652Y
Advanced LinCMOS PRECISION CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS019C – SEPTEMBER 1988 – REVISED FEBRUARY 1999
APPLICATION INFORMATION
latch-up avoidance
Because CMOS devices are susceptible to latch-up due to their inherent parasitic thyristors, the TLC2652 inputs
and output are designed to withstand –100-mA surge currents without sustaining latch-up; however, techniques
to reduce the chance of latch-up should be used whenever possible. Internal protection diodes should not, by
design, be forward biased. Applied input and output voltages should not exceed the supply voltage by more than
300 mV. Care should be exercised when using capacitive coupling on pulse generators. Supply transients
should be shunted by the use of decoupling capacitors (0.1 µF typical) located across the supply rails as close
to the device as possible.
The current path established if latch-up occurs is usually between the supply rails and is limited only by the
impedance of the power supply and the forward resistance of the parasitic thyristor. The chance of latch-up
occurring increases with increasing temperature and supply voltage.
electrostatic discharge protection
The TLC2652 incorporates internal ESD-protection circuits that prevent functional failures at voltages at or
below 2000 V. Care should be exercised in handling these devices, as exposure to ESD may result in
degradation of the device parametric performance.
theory of operation
Chopper-stabilized operational amplifiers offer the best dc performance of any monolithic operational amplifier .
This superior performance is the result of using two operational amplifiers, a main amplifier and a nulling
amplifier, plus oscillator-controlled logic and two external capacitors to create a system that behaves as a single
amplifier. With this approach, the TLC2652 achieves submicrovolt input offset voltage, submicrovolt noise
voltage, and offset voltage variations with temperature in the nV/°C range.
The TLC2652 on-chip control logic produces two dominant clock phases: a nulling phase and an amplifying
phase. The term chopper-stabilized derives from the process of switching between these two clock phases.
Figure 34 shows a simplified block diagram of the TLC2652. Switches A and B are make-before-break types.
During the nulling phase, switch A is closed shorting the nulling amplifier inputs together and allowing the nulling
amplifier to reduce its own input offset voltage by feeding its output signal back to an inverting input node.
Simultaneously , external capacitor C
remain nulled during the amplifying phase.
IN+
IN–
stores the nulling potential to allow the offset voltage of the amplifier to
During the amplifying phase, switch B is closed connecting the output of the nulling amplifier to a noninverting
input of the main amplifier. In this configuration, the input offset voltage of the main amplifier is nulled. Also,
external capacitor C
nulled during the next nulling phase.
This continuous chopping process allows offset voltage nulling during variations in time and temperature over
the common-mode input voltage range and power supply range. In addition, because the low-frequency signal
path is through both the null and main amplifiers, extremely high gain is achieved.
The low-frequency noise of a chopper amplifier depends on the magnitude of the component noise prior to
chopping and the capability of the circuit to reduce this noise while chopping. The use of the Advanced LinCMOS
process, with its low-noise analog MOS transistors and patent-pending input stage design, significantly reduces
the input noise voltage.
The primary source of nonideal operation in chopper-stabilized amplifiers is error charge from the switches. As
charge imbalance accumulates on critical nodes, input offset voltage can increase, especially with increasing
chopping frequency. This problem has been significantly reduced in the TLC2652 by use of a patent-pending
compensation circuit and the Advanced LinCMOS process.
stores the nulling potential to allow the offset voltage of the main amplifier to remain
XB
The TLC2652 incorporates a feed-forward design that ensures continuous frequency response. Essentially , the
gain magnitude of the nulling amplifier and compensation network crosses unity at the break frequency of the
main amplifier. As a result, the high-frequency response of the system is the same as the frequency response
of the main amplifier. This approach also ensures that the slewing characteristics remain the same during both
the nulling and amplifying phases.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2652, TLC2652A, TLC2652Y
Advanced LinCMOS PRECISION CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS019C – SEPTEMBER 1988 – REVISED FEBRUARY 1999
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
14
1
0.069 (1,75) MAX
A
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.004 (0,10)
DIM
8
7
PINS **
0.010 (0,25)
0.157 (4,00)
0.150 (3,81)
M
0.244 (6,20)
0.228 (5,80)
Seating Plane
0.004 (0,10)
8
14
0.008 (0,20) NOM
0°–8°
16
Gage Plane
0.010 (0,25)
0.044 (1,12)
0.016 (0,40)
A MAX
A MIN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
NOTES: A. All linear dimensions are in inches (millimeters).
26
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
4040140/D 10/96
TLC2652, TLC2652A, TLC2652Y
Advanced LinCMOS PRECISION CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS019C – SEPTEMBER 1988 – REVISED FEBRUARY 1999
MECHANICAL DATA
J (R-GDIP-T**) CERAMIC DUAL-IN-LINE PACKAGE
14 PIN SHOWN
14
1
0.065 (1,65)
0.045 (1,14)
0.100 (2,54)
0.070 (1,78)
PINS **
DIM
A MAX
B
8
C
7
0.020 (0,51) MIN
0.200 (5,08) MAX
A MIN
B MAX
B MIN
C MAX
C MIN
Seating Plane
0.310
(7,87)
0.290
(7,37)
0.785
(19,94)
0.755
(19,18)
0.300A0.300
(7,62)
0.245
(6,22)
0.310
(7,87)
0.290
(7,37)
0.785
(19,94)
0.755
(19,18)
(7,62)
0.245
(6,22)
181614
0.310
(7,87)
0.290
(7,37)
0.910
(23,10)
0.300
(7,62)
0.245
(6,22)
20
0.310
(7,87)
0.290
(7,37)
0.975
(24,77)
0.930
(23,62)
0.300
(7,62)
0.245
(6,22)
0.100 (2,54)
0.023 (0,58)
0.015 (0,38)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
NOTES: A. All linear dimensions are in inches (millimeters).
28
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4040107/C 08/96
TLC2652, TLC2652A, TLC2652Y
Advanced LinCMOS PRECISION CHOPPER-STABILIZED
OPERATIONAL AMPLIFIERS
SLOS019C – SEPTEMBER 1988 – REVISED FEBRUARY 1999
MECHANICAL DATA
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
16 PIN SHOWN
16
1
0.035 (0,89) MAX
PINS **
DIM
A
9
0.260 (6,60)
0.240 (6,10)
8
0.070 (1,78) MAX
0.020 (0,51) MIN
0.200 (5,08) MAX
A MAX
A MIN
Seating Plane
14
0.775
(19,69)
0.745
(18,92)
16
0.775
(19,69)
0.745
(18,92)
18
0.920
(23.37)
0.850
(21.59)
20
0.975
(24,77)
0.940
(23,88)
0.310 (7,87)
0.290 (7,37)
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)