Texas Instruments TLC1551IFN, TLC1550MJ, TLC1550MFKB, TLC1550IFNR, TLC1550INW Datasheet
...
D
Power Dissipation...40 mW Max
D
Advanced LinEPIC Single-Poly Process
Provides Close Capacitor Matching for
Better Accuracy
D
Fast Parallel Processing for DSP and µP
Interface
D
Either External or Internal Clock Can Be
Used
D
Conversion Time ...6 µs
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Total Unadjusted Error... ±1 LSB Max
D
CMOS Technology
description
The TLC1550x and TLC1551 are data acquisition
analog-to-digital converters (ADCs) using a 10-bit,
switched-capacitor, successive-approximation
network. A high-speed, 3-state parallel port directly
interfaces to a digital signal processor (DSP) or
microprocessor (µP) system data bus. D0 through
D9 are the digital output terminals with D0 being the
least significant bit (LSB). Separate power
terminals for the analog and digital portions
minimize noise pickup in the supply leads.
Additionally, the digital power is divided into two
parts to separate the lower current logic from the
higher current bus drivers. An external clock can be
applied to CLKIN to override the internal system
clock if desired.
The TLC1550I and TLC1551I are characterized for
operation from –40°C to 85°C. The TLC1550M is
characterized over the full military range of –55°C
to 125°C.
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
J† OR NW PACKAGE
(TOP VIEW)
REF+
REF–
ANLG GND
AIN
ANLG V
DD
DGTL GND1
DGTL GND2
DGTL V
DGTL V
DD1
DD2
EOC
D0
D1
†
Refer to the mechanical data for the JW
package.
FK OR FN PACKAGE
ANLG GND
4
321
5
AIN
ANLG V
DGTL GND1
DGTL GND2
DGTL V
DGTL V
DD
NC
DD1
DD2
6
7
8
9
10
11
12
13 14
EOC
NC – No internal connection
1
2
3
4
5
6
7
8
9
10
11
12
(TOP VIEW)
REF–
REF+
15 16 17
D0
D1NCD2D3D4
RD
24
WR
23
CLKIN
22
CS
21
D9
20
D8
19
D7
18
D6
17
D5
16
D4
15
D3
14
D2
13
RDWRCLKIN
NC
28 27 26
18
25
24
23
22
21
20
19
CS
D9
D8
NC
D7
D6
D5
AVAILABLE OPTIONS
T
A
–40°C to 85°C –
–55°C to 125°C TLC1550MFK – TLC1550MJ –
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either VCC or ground.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinEPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
CERAMIC CHIP CARRIER
(FK)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PLASTIC CHIP CARRIER
PACKAGE
(FN)
TLC1550IFN
TLC1551IFN
CERAMIC DIP
(J)
–
Copyright 1995, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PLASTIC DIP
(NW)
TLC1550INW
–
2–1
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
functional block diagram
EOC
CS
WR
RD
DGTL
V
DD1
100 kΩ
NOM
CLKIN
REF+
REF–
AIN
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
AIN
Ci = 60 pF TYP
(equivalent input
capacitance)
Frequency
Divided by 2
Control
Logic
Clock Detector
Internal
Clock
Successive-
Approximation
Register
10
10-Bit
Capacitor
DAC and S/H
AIN
10
D0–D9
Comp
5 MΩ TYP
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DESCRIPTION
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
Terminal Functions
TERMINAL
NAME NO.†NO.
ANLG GND 4 3 Analog ground. The reference point for the voltage applied on terminals ANLG VDD, AIN, REF+, and REF–.
AIN 5 4 Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output.
ANLG V
DD
CLKIN 26 22 Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a
CS 25 21 Chip-select. CS must be low for RD or WR to be recognized by the A/D converter.
D0 13 11 Data bus output. D0 is bit 1 (LSB).
D1 14 12 Data bus output. D1 is bit 2.
D2 16 13 Data bus output. D2 is bit 3.
D3 17 14 Data bus output. D3 is bit 4.
D4 18 15 Data bus output. D4 is bit 5.
D5 19 16 Data bus output. D5 is bit 6.
D6 20 17 Data bus output. D6 is bit 7.
D7 21 18 Data bus output. D7 is bit 8.
D8 23 19 Data bus output. D8 is bit 9.
D9 24 20 Data bus output. D9 is bit 10 (MSB).
DGTL GND1 7 6 Digital ground 1. The ground for power supply DGTL V
DGTL GND2 9 7 Digital ground 2. The ground for power supply DGTL V
DGTL V
DD1
DGTL V
DD2
EOC 12 10 End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferred
RD 28 24 Read input. When CS is low and RD is taken low , the data is placed on the data bus from the output latch. The
REF+ 2 1 Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts
REF– 3 2 Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF– converts
WR 27 23 Write input. When CS is low , conversion is started on the rising edge of WR. On this rising edge, the ADC holds
†
Terminal numbers for FK and FN packages.
‡
Terminal numbers for J and NW packages.
6 5 Analog positive power supply voltage. The voltage applied to this terminal is designated V
10 8 Digital positive power-supply voltage 1. DGTL V
11 9 Digital positive power-supply voltage 2. DGTL V
‡
.
DD3
few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high
or left unconnected.
and is the substrate connection.
DD1
.
DD2
supplies the logic. The voltage applied to DGTL V
designated V
applied to DGTL V
to the output latch. EOC
output latch stores the conversion results at the most recent negative edge of EOC
resets EOC to a high within the t
to 1111111111. Analog input voltages between REF+ and REF– convert to the appropriate result in a ratiometric
manner.
to 0000000000.
the analog input until conversion is completed. Before and after the conversion period, which is given by t
the ADC remains in the sampling mode.
DD1
.
is designated V
DD2
can be connected to the µP- or DSP-interrupt terminal or can be continuously polled.
d(EOC)
DD1
supplies only the higher-current output buffers. The voltage
DD2
.
DD2
specifications.
. The falling edge of RD
DD1
conv
is
,
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
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