Texas Instruments TLC1541IN, TLC1541IFN, TLC1541IDWR, TLC1541IDW, TLC1541CN Datasheet

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TLC1541

10-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10-Bit Resolution A/D Converter

Microprocessor Peripheral or Standalone Operation

On-Chip 12-Channel Analog Multiplexer

Built-In Self-Test Mode

Software-Controllable Sample-and-Hold Function

T otal Unadjusted Error...±1 LSB Max

Pinout and Control Signals Compatible With TLC540 and TLC549 Families of 8-Bit A/D Converters

CMOS Technology

PARAMETER VALUE

Channel Acquisition Sample Time Conversion Time (Max) Samples Per Second (Max) Power Dissipation (Max)

5.5 µs 21 µs

32 × 10

6 mW

description

The TLC1541 is a CMOS A/D converter built around a 10-bit switched-capacitor successiveapproximation A/D converter. The device is designed for serial interface to a microprocessor or peripheral using a 3-state output with up to four control inputs ( including independent SYSTEM CLOCK, I/O CLOCK, chip select [CS

], and ADDRESS INPUT ). A 2.1-MHz system clock for the TLC1541, with a design that includes simultaneous read/write operation, allows highspeed data transfers and sample rates up to 32 258 samples per second. In addition to the high-speed converter and versatile control logic, there is an on-chip, 12-channel analog multiplexer that can be used to sample any one of 11 inputs or an internal self-test voltage and a sample-andhold function that operates automatically.

AVAILABLE OPTIONS

PACKAGE

SMALL

OUTLINE

(DW)

PLASTIC CHIP

CARRIER

(FN)

PLASTIC

DIP

(N)

0°C to 70°C TLC1541CDW TLC1541CFN TLC1541CN

–40°C to 85°C TLC1541IDW TLC1541IFN TLC1541IN

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

INPUT A0 INPUT A1 INPUT A2 INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7 INPUT A8

GND

SYSTEM CLOCK I/O CLOCK ADDRESS INPUT DATA OUT CS REF+ REF– INPUT A10 INPUT A9

DW OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

4 5 6 7 8

18 17 16 15 14

I/O CLOCK ADDRESS INPUT DATA OUT CS REF+

INPUT A3 INPUT A4 INPUT A5 INPUT A6 INPUT A7

FN PACKAGE

(TOP VIEW)

INPUT A2

INPUT A1

INPUT A0

INPUT A10

REF–

SYSTEM CLOCK

INPUT A8

GND

INPUT A9

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The converters incorporated in the TLC1541 feature differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and analog circuitry isolation from logic and supply noises. A totally switched-capacitor design allows low-error conversion in 21 µs over the full operating temperature range.

The TLC1541 is available in DW, FN, and N packages. The C-suffix versions are characterized for operation from 0°C to 70°C. The I-suffix versions are characterized for operation from –40°C to 85°C.

functional block diagram

12-Channel

Analog

Multiplexer

Sample and

Hold

10-Bit

Switched-Capacitors

Analog-to-Digital

Converter

Self-Test

Reference

Output

Data

10-to-1 Data

Selector and

Driver

Control Logic

and I/O

Counters

Input

Multiplexer

Input Address

REF+ REF–

DATA OUT

ANALOG

INPUTS

ADDRESS

INPUT

I/O CLOCK

SYSTEM

CLOCK

1 2 3 4 5 6 7 8 9 11 12

14 13

18 15 19

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

Ci = 60 pF TYP (equivalent input capacitance)

5 MΩ TYP

INPUT

A0–A10

INPUT

A0–A10

TLC1541

10-BIT ANALOG-TO-DIGITAL CONVERTER

WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

operating sequence

MSB LSB

Don’t Care Don’t Care

MSB LSB

wH(CS)

conv

See Note A

See Note C

HI-Z

State

HI-Z State

Sample Cycle C

Access Cycle C

Sample Cycle B

Access Cycle B

Previous Conversion Data A

Conversion Data B

A9 B9

MSB LSB MSB MSB LSB MSB

(

see Note B

)

B9 B8 B7 B6 B5 B4 B3 B2 B1 B0A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

B3 B2 B1 B0 C3 C2 C1 C0

Don’t Care

1 2 3 4 56 78 9 10 1 2 3 4 56 78 9 10

I/O

CLOCK

ADDRESS

INPUT

DATA

OUT

NOTES: A. The conversion cycle, which requires 44 system clock periods, initiates on the tenth falling edge of the I/O clock after CS goes low

for the channel whose address exists in memory at that time. When CS

is kept low during conversion, the I/O clock must remain

low for at least 44 system clock cycles to allow the conversion to complete.

B. The most significant bit (MSB) is automatically placed on the DAT A OUT bus after CS

is brought low. The remaining nine bits (A8–A0)

clock out on the first nine I/O clock falling edges.

C. To minimize errors caused by noise at the CS

input, the internal circuitry waits for three system clock cycles (or less) after a chip-select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock-in address data until the minimum chip-select setup time elapses.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage, V

(see Note 1) 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

(any input) –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current (any input) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I suffix –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, T

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: DW or N package 260°C. . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted).

TLC1541 10-BIT ANALOG-TO-DIGITAL CONVERTER WITH SERIAL CONTROL AND 11 INPUTS

SLAS073C – DECEMBER 1995 – REVISED AUGUST 1996

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

4.75 5 5.5 V

Positive reference voltage, V

ref+

(see Note 2) 2.5 V

CCVCC

+0.1 V

Negative reference voltage, V

ref–

(see Note 2) –0.1 0 2.5 V

Differential reference voltage, V

ref+

– V

ref–

(see Note 2) 1 V

CCVCC

+0.2 V

Analog input voltage (see Note 2) 0 V

High-level control input voltage, V

2 V

Low-level control input voltage, V

0.8 V

Input/output clock frequency, f

clock(I/O)

0 1.1 MHz

System clock frequency, f

clock(SYS)

clock(I/O)

2.1 MHz

Setup time, address bits before I/O CLOCK↑, t

su(A)

400 ns

Hold time, address bits after I/O CLOCK↑, t

h(A)

0 ns

Setup time, CS low before clocking in first address bit, t

su(CS)

(see Note 3 and Operating Sequence)

System

clock

cycles

Pulse duration, CS high during conversion, t

wH(CS)

(see Operating Sequence) 44

System

clock

cycles

Pulse duration, SYSTEM CLOCK high, t

wH(SYS)

210 ns

Pulse duration, SYSTEM CLOCK low, t

wL(SYS)

190 ns

Pulse duration, I/O CLOCK high, t

wH(I/O)

404 ns

Pulse duration, I/O CLOCK low, t

wL(I/O)

404 ns

clock(SYS)

≤ 1048 kHz 30

System

clock(SYS)

> 1048 kHz 20

Clock transition time (see Note 4)

clock(I/O)

≤ 525 kHz 100

I/O

clock(I/O)

> 525 kHz 40

C suffix 0 70

O erating free-air tem erature, T

I suffix –40 85

°C

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied

to REF– convert as all zeros (0000000000). For proper operation, REF+ voltage must be at least 1 V higher than REF– voltage. Also, the total unadjusted error may increase as this differential reference voltage falls below 4.75 V.

3. To minimize errors caused by noise at the chip select input, the internal circuitry waits for three system clock cycles (or less) after a chip select falling edge is detected before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum chip select setup time elapses.

4. The amount of time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

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