Texas Instruments TL16PNP550AFN, TL16PNP550AFNR Datasheet

TL16PNP550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

PnP Card Autoconfiguration Sequence
Compliant

D

External Terminal-to-Bypass PnP
Autoconfiguration Sequence

D

In UART Bypass Mode, the Stand-Alone
PnP Controller is Configured With One
Logical Device

D

Provides 10-Interrupts IRQ3–IRQ7,
IRQ9–IRQ12, IRQ15

D

Simple 3-Pin Interface to SGS-Thomson
EEPROM 2K/4K ST93C56/66

D

High Output Current Drive. No External
Buffer Needed for Data and Interrupt
Signals

D

Programmable Auto-RTS and Auto-CTS

D

In Auto-CTS Mode, CTS Controls
Transmitter

D

In Auto-RTS Mode, Receiver FIFO Contents
and Threshold Control RTS

D

The Serial and Modem Control Outputs
Drive a 1-Meter RJ11 Cable Directly if
Equipment Is on the Same Power Drop

D

Capable of Running With All Existing
TL16C450 Software

D

After Reset, All Registers Are Identical to
the TL16C450 Register Set

D

Clock Prescalar Allows 22-MHz Oscillator
Clock to be Divided by 12, 6, 3, or 1

D

In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data

D

Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2

16

–1) and Generates an Internal 16×

Clock

D

On-Chip I/O Port Address Decoding

D

In PnP Bypass Mode, 6 External Terminals
Configure the I/O Base Address and
Interrupt Mapping

D

Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream

D

Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel

D

Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity-Bit Generation

and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1 Mbit Per

Second)

D

False Start Bit Detection

D

Complete Status Reporting Capabilities

D

3-State Outputs Provide TTL Drive for
Bidirectional Data Bus and Interrupt Lines

D

Line Break Generation and Detection

D

Internal Diagnostic Capabilities:
– Loopback Controls for Communications

Link Fault Isolation
– Break, Parity, Overrun, and Framing

Error Simulation

D

Fully Prioritized Interrupt System Controls

D

Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)

D

Transmitter and Receiver Run at the Same
Speed

D

Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation for the Internal ACE

D

Available in 68-Pin PLCC

description

The TL16PNP550A is a functional upgrade of the TL16C550C asynchronous communications element (ACE),
which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up
(character or TL16C450 mode), the TL16PNP550A, like the TL16C550C, can be placed in an alternate mode
(FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1996, Texas Instruments Incorporated

SGS-Thomson is a trademark of SGS-Thomson Incorporated.

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can
significantly reduce software overload and increase system efficiency by automatically controlling serial data
flow using RTS

output and CTS input signals.

The TL16PNP550A responds to the plug-and-play (PnP) autoconfiguration process. The autoconfiguration
process puts all PnP cards in a configuration mode, isolates one PnP card at a time, assigns a card select
number (CSN), and reads the card resource data structure from the EEPROM. After the resource requirements
and capabilities are determined for all cards, the autoconfiguration process uses the CSN to configure the card
by writing to the configuration registers. The TL16PNP550A only implements configuration registers for I/O
applications with one logical device and no direct memory access (DMA) support. Finally , the process activates
the TL16PNP550A card and removes it from configuration mode. After the configuration process, the ACE starts
responding to industry standard architecture (ISA) bus cycles. This device can also be configured to bypass
the PnP autoconfiguration sequence. In this mode the TL16PNP500A can be configured to select the COM port
address and IRQ level. In the UART bypass mode, the UART is disabled and this device is configured to be a
stand-alone PnP controller that supports one logical device and no DMA support.

The TL16PNP550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE operation. Reported status information includes the type of transfer operation in progress, the status
of the operation, and any error conditions encountered.

The TL16PNP550A includes a clock prescalar that divides the 22-MHz input clock by 12, 6, 3, or 1. The prescalar
output clock is fed to the programmable baud rate generator, which is capable of dividing this clock by divisors
from 1 to (2

16

– 1).

TL16PNP550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

28 29

CTS
DCD
EEPROM
SIO
V

CC

SCLK
CS
PNPS0
PNPS1
SOUT
DTR
RTS
GND
EXINTR
AEN
RESETDRV
A11

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

30

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

D0
D1
D2
D3

GND

D4
D5
D6
D7

IRQ15

IRQ3
IRQ4

V

CC

IRQ5
IRQ6
IRQ7
IRQ9

31 32 33 34

FN PACKAGE

(TOP VIEW)

ACONFIG1

ACONFIG0

87 65493

UARTBYPASS

SIN

ICONFIG3

ICONFIG2

ICONFIG1

ICONFIG0

A4A5A6

IRQ12

CS

GND

A0A1A2

A3

168672

35 36 37 38 39

66 65

27

IRQ10

IRQ11

PNPBYPASS

GND

64 63 62 61

40 41 42 43

A7A8A9

A10

XOUT

XIN

DSR

RI

IOW

IOR

V

CC

V

CC

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

PnP

Controller

ACE

Divide by
12, 6, 3, 1

66 67,681–4

PNPBYPASS

ACONFIG (0–1)

ICONFIG (0–4)

Oscillator

32–38, 40–44
10–13, 15–18

45
46

9
8

19–21, 23–29

55
57

54
58

SCLK
SIO
CS
EEPROM

To
EEPROM

EXINTR

UARTBYPASS

To External
Logical Device

UARTBYPASS

CS

To External

Logical Device

A0–A11

D0–D7

RESETDRV

AEN

IOW

IOR

IRQ 3–7, 9–12, 15

To ISA

Bus

SIN
SOUT
RTS
CTS
DTR
DCD
RI

6
51
49
60
50
59
61

10–13, 15–18

32–34

9
8

A0–A2

IOW

IOR

D0–D7

To RS–232
Transceivers

To ISA Bus

CLK From Prescalar

CS

_IN MR

63
64

XIN

XOUT

CLK
(to the ACE)

(prescalar)

22 MHz

INTRPT

PNPS1
PNPS0

47

7

52
53

7

30

8

3

8

8

8

2

4

DSR

62

TL16PNP550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ACE functional block diagram

Receiver

Buffer

Register

Divisor

Latch (LS)

Divisor

Latch (MS)

Baud

Generator

Receiver

FIFO

Line

Status

Register

Transmitter

Holding

Register

Modem

Control

Register

Modem

Status

Register

Line

Control

Register

Transmitter

FIFO

Interrupt

Enable

Register

Interrupt

Identification

Register

FIFO

Control

Register

Select

and

Control

Logic

Interrupt

Control

Logic

S
e

l
e
c

t

Data

Bus

Buffer

SIN

SOUT

CTS
DTR
DSR
DCD
RI

INTRPT

60
50
62
59
61

51

6

A0

32

D(7–0)

18–15, 13 –10

Internal
Data Bus

A1
A2

CS

MR

IOR

IOW

S

e

l
e
c

t

Receiver

Shift

Register

Receiver

Timing and

Control

Transmitter

Timing and

Control

Transmitter

Shift

Register

Modem

Control

Logic

8

V

CC

V

SS

Power
Supply

RTS

49

Autoflow
Control
(AFE)

8

8

8

8

8

8

8

33
34

(from PnP)

(from PnP)

8
9

CLK
(from
Prescalar)

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME

NO.

FN

I/O

DESCRIPTION

A0–A6
A7–A11

32–38
40–44

I 12-bit ISA address terminals. All 12 bits are used during PnP autoconfiguration sequence. After

autoconfiguration, bits A0–A2 select the ACE registers and bits A3 –A9 are used in the address decoding
to generate chip select for the device.

ACONFIG0,
ACONFIG1

67, 68 I Address configure. In PnP bypass mode, both ACONFIG0 and ACONFIG1 configure the COM port base

address.
AEN 46 I Address enable. AEN disables the ACE and PnP controller during DMA.
CS 54 O Chip select. CS is a 3-state output. It controls the activity of the EEPROM. A 100 µA pulldown circuit is

connected to this terminal.
CS 30 O Chip select. CS is the I/O chip select for the logical device.
CTS 60 I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the

modem status register (MSR). Bit 0 (∆CTS) of the modem status register indicates that this signal has

changed states since the last read from the MSR. When the modem status interrupt is enabled when CTS

changes states and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the

auto-CTS mode to control the transmitter.
D0–D3

D4–D7

10–13
15–18

I/O Data bus. D0 – D7 are eight data lines with 3-state outputs that provide a bidirectional path for data, control,

and status information between the ACE and the CPU. The output drive sinks 24 mA at 0.4 V and sources

12 mA at 2.4 V.
DCD 59 I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of

the MSR. Bit 3 (∆DCD) of the MSR indicates that this signal has changed levels since the last read from the

MSR. When the modem status interrupt is enabled when DCD

changes states, an interrupt is generated.

DSR 62 I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the

MSR. Bit 1 (∆DSR) of the MSR indicates this signal has changed states since the last read from the MSR.

If the modem status interrupt is enabled when the DSR

changes states, an interrupt is generated.

DTR 50 O Data terminal ready . When active (low), DTR informs a modem or data set that the ACE is ready to establish

communication. DTR

is placed in its active level by setting the DTR bit of the MCR. DTR is placed in its

inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit.
EEPROM 58 I/O EEPROM access. EEPROM is a 3-state bidirectional signal. When it is pulled low, either the TL16PNP550A

or controller is accessing the EEPROM. A 100 µA pullup circuit is connected to this terminal.
EXINTR 47 I External interrupt. During UARTBYPASS mode, the external logical device interrupt (EXINTR) is mapped

to the configured IRQs.
GND 14, 31,

48, 65

Ground (0 V). These four GND terminals must be tied to ground for proper operation.

ICONFIG0–
ICONFIG3

1–4 I IRQ configure. In PnP bypass mode, ICONFIG0, ICONFIG2, and ICONFIG3 configure the required IRQ.

IOR 8 I Read input. When IOR is active while the ACE is selected, the CPU is allowed to read from the ACE.
IOW 9 I Write input. When IOW is active while the ACE is selected, the CPU is allowed to write to the ACE.
IRQ3–IRQ4

IRQ5–IRQ7
IRQ9–IRQ12
IRQ15

20–21
23–25
26–29

19

O 3-state interrupt requests. When active (high), IRQx informs the CPU that the ACE has an interrupt to be

serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data is available

or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt.

IRQx is generated when one or all of the above conditions occur and the value of bits 0–3 in the interrupt

request level (0×70) is equal to x (of IRQx). The output drive sinks 24 mA at 0.4 V and sources 12 mA at

2.4 V.

PNPBYPASS 66 I Bypass PnP configuration sequence. When PNPBYPASS is tied to GND, the PnP autoconfiguration

sequence is bypassed.
PNPS1–

PNPS0

52–53 O PnP internal states. See the PNPS1 and PNPS0 truth table in the PnP states section of this document.

RESETDRV 45 I Reset. When active (high), RESETDRV clears most ACE registers and puts the ACE in wait for key state.

The CSN is reset to 0×00. All configuration registers are set to their power-up values.

TL16PNP550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions (Continued)

TERMINAL

NAME

NO.

FN

I/O

DESCRIPTION

RI 61 I Ring indicator. RI is modem status signal. Its condition can be checked by reading bit 6 (RI) of the MSR. BIt

2 (TERI) of the MSR indicates that RI

has transitioned from a low to a high level since the last read from the

MSR. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

RTS 49 O Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data.

RTS

is set to its active level low by setting the RTS modem control register bit and is set to its inactive (high)
level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR.
In auto-RTS mode, RTS

is set to its inactive level by the receiver threshold control logic.

SCLK 55 O 3-state EEPROM clock. SCLK is a 3-state EEPROM clock output that controls address and data transfer.

A 100 µA pulldown circuit is connected to this terminal.

SIN 6 I Serial data. SIN is input from a connected communications device.
SIO 57 I/O 3-State bidirectional EEPROM serial data bus. During output mode, SIO provides only read opcode and

address which are sourced at the falling edge of SCLK. During input mode it provides the data which is
captured at the rising edge of SCLK. A 100 µA pulldown circuit is connected to this terminal.

SOUT 51 O Composite serial data output to a connected communication device. SOUT is set to the marking (high) level

as a result of master reset.

UARTBYPASS 7 I UART bypass. When it is active, UARTBYPASS disables the UART and the TL16PNP550A acts as a PnP

stand-alone controller.

V

CC

5, 22,
39, 56

5-V supply voltage.

XIN, XOUT 63, 64 I/O External clock. XIN and XOUT connect the TL16PNP550A to the main timing reference, a 22-MHz clock or

crystal.

detailed description

autoflow control

Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the input must be active before the
transmitter FIFO can emit data (see Figure 1). Auto-RTS becomes active when the receiver needs more data
and notifies the sending serial device (see Figure 1). When RTS

is connected to CTS, data transmission does
not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated if ACE1 and ACE2
are TL16PNP550As with enabled autoflow control. If autoflow control is not enabled, overrun errors occur when
the transmit data rate exceeds the receiver FIFO read latency.

RCV
FIFO

Serial to

Parallel

Flow

Control

XMT
FIFO

Parallel

to Serial

Flow

Control

Parallel

to Serial

Flow

Control

Serial to

Parallel

Flow

Control

XMT
FIFO

RCV
FIFO

ACE1 ACE2

D7–D0

SIN SOUT

RTS

CTS

SOUT SIN

CTS

RTS

D7–D0

Figure 1. Autoflow Control Example (Auto-RTS and Auto-CTS)

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

auto-RTS (see Figure 1)

Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level
of 1, 4, or 8, (see Figure 3), RTS

is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send
an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS

until after it has begun sending the additional byte. RTS

is automatically reasserted once the receiver FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 4), RTS

is deasserted after the first data bit of the sixteenth character

is present on the SIN line. RTS

is reasserted when the receiver FIFO has at least one available byte space.

auto-CTS (see Figure 1)

The transmitter circuitry checks CTS

before sending the next data byte. When CTS is active, it sends the next

byte. To stop the transmitter from sending the following byte, CTS

must be released before the middle of the
last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, changes of CTS

level do not trigger host interrupts because the device
automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error may result.

enabling autoflow control and auto-CTS

Autoflow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to

1. Autoflow incorporates both auto-RTS and auto-CTS. If only auto-CTS is desired, bit 1 in the MCR should be
cleared (this assumes a control signal is driving CTS

).

Start Bits 0–7 Start Bits 0–7 Start Bits 0–7

Stop Stop Stop

SOUT

CTS

NOTE A: When CTS is low, the transmitter keeps sending serial data out. If CTS goes high before the middle of the last stop bit of the current

byte, the transmitter finishes sending the current byte but it does not send the next byte. When CTS

goes from high to low, the transmitter

begins sending data again.

Figure 2. CTS Functional Timing Waveforms

The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.

Start Byte N Start Byte N+1 Start Byte

Stop Stop Stop

SIN

RTS

RD

(RD RBR)

12

N N+1

NOTES: A. N = receiver FIFO trigger level (1, 4, or 8 bytes)

B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.

Figure 3. RTS Functional Timing Waveforms, Receiver FIFO Trigger Level = 1, 4, or 8 Bytes

TL16PNP550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

enabling autoflow control and auto-CTS (continued)

Byte 14 Byte 15

SIN

RTS

RD

(RD RBR)

Start Byte 18 StopStart Byte 16 Stop

RTS Released After the

First Data Bit of Byte 16

NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receiver FIFO is full after finishing the

sixteenth byte.

B. RTS

is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than

one byte of space available.

C. When the receiver FIFO is full, the first receiver buffer register read reasserts RTS

.

Figure 4. RTS Functional Timing Waveforms, Receiver FIFO Trigger Level = 14 Bytes

flow control and interrupt

When flow control is enabled, bit 0 (∆CTS) of the modem status register does not cause a modem status
interrupt. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs, and
a typical character time is 10 µs (start bit, 8 data bits, and a stop bit).

The TL16PNP550A ACE includes a programmable, on-board, baud rate generator that divides a reference
clock input by 1 to (2

16

– 1) for producing a 16 × clock to drive the internal transmitter logic. Provisions are
included to use this 16 × clock to drive the receiver logic. The ACE includes complete modem control capability
and a processor interrupt system that may be software tailored to minimize the system overhead for handling
the communications link.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range at any input, V

I

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

A

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds, T

C

: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CC

4.75 5 5.25 V

High-level input voltage, V

IH

2 V

CC

V

Low-level input voltage, V

IL

–0.5 0.8 V

Operating free-air temperature, T

A

0 70 °C

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

OH

‡

High-level output voltage IOH = –12 mA VCC–0.8 V

V

OL

‡

Low-level output voltage IOL = 24 mA 0.5 V

V

OH

High-level output voltage

IOH = –4 mA (see Note 2),
VCC = 0.8 V

VCC–0.8 V

V

OL

Low-level output voltage IOL = 4 mA (see Note 2) 0.5 V

p

V

= 5.25 V , V

= 0,

IlInput current

CC

,

VI = 0 to 5.25 V,

SS

,

All other terminals floating

±1µA

V

= 5.25 V,V

= 0

,

I

OZ

High-i

mpedance-state output cur-

V

CC

5.25 V, V

SS

0,

VO = 0 to 5.25 V,

±10 µA

OZ

rent

O

Pullup and pulldown circuits are off

µ

VCC = 5.25 V , TA = 25°C,

CC A

SIN, DSR, DCD, CTS, and RI at 2 V ,

I

CC

Supply current

All other inputs at 0.8 V ,

5mA

CC

y

Clock at 4 MHz (no crystal used)

,

No load on outputs

,

No load on out uts,

Baud rate = 50 kbit/s

C

i(CLK)

Clock input capacitance 15 20 pF

C

o(CLK)

Clock output capacitance

VCC = 0, VSS = 0,

20 30 pF

C

i

Input capacitance

f

= 1 MHz,

T

A

=

25°C

,

All oth

e

r terminals groun

ded

6 10 pF

C

o

Output capacitance

All other terminals grounded

10 20 pF

f

(XIN–XOUT)

Oscillator speed (XIN and XOUT) 16 22 MHz

†

All typical values are at VCC = 5 V and TA = 25°C.

‡

These parameters apply only for IRQx and D7–D0.

NOTE 2: These parameters apply for all outputs except XOUT, IRQx, and D7–D0.

clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature

PARAMETER

ALTERNATE

SYMBOLS

TEST

CONDITIONS

MIN MAX UNIT

t

d1

Delay time, chip select (CS) high to clock (SCLK) high t

SHCH

50 ns

t

d2

Input valid to clock (SCLK) high t

DVCH

100 ns

t

pd1

Propagation delay time, clock (SCLK) high to input transition
(SIO)

t

CHDX

100 ns

t

pd2

Propagation delay time, clock (SCLK) high to output valid
(SIO)

t

CHQV

500 ns

t

pd3

Propagation delay time, clock (SCLK) low to chip select
transition (CS)

t

CLSL

See Figure 18

and Figure 19

2

clock

periods

t

d3

Delay time, chip select (CS) low to output Hi-Z (SIO) t

SLQZ

100 ns

t

w(SCLKH)

Pulse duration, clock (SCLK) high to clock (SCLK) low
(see Note 3)

t

CHCL

250 ns

t

w(SCLKL)

Pulse duration, clock (SCLK) low to clock (SCLK) high
(see Note 3)

t

CLCH

250 ns

f

clock

Clock frequency (SCLK) (see Note 4) F

CLK

0.5 0.68 MHz

NOTES: 3. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (t

SLSH

) between consecutive instruction cycles according

to the ST93C56 specification.

4. The SCLK signal is attained by internally frequency dividing the XIN signal by 32.

TL16PNP550A

ASYNCHRONOUS COMMUNICATIONS ELEMENT

WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature

PARAMETER

ALTERNATE

SYMBOL

FIGURE TEST CONDITIONS MIN MAX UNIT

t

cR

Cycle time, read (tw7 + td8 + td9) RC 87 ns

t

cW

Cycle time, write (tw6 + td5 + td6) WC 87 ns

t

w1

†

Pulse duration, XIN high t

XH

Figure 5 f = 16 MHz maximum 25 ns

t

w2

†

Pulse duration, XIN low t

XL

Figure 5 f = 16 MHz maximum 25 ns

t

w6

Pulse duration, write strobe (IOW) t

WR

Figure 6 75 ns

t

w7

Pulse duration, read strobe (IOR) t

RD

Figure 7 75 ns

t

w8

Pulse duration, master reset t

MR

1 µs

t

su3

Setup time, data valid before

IOW

↑ t

DS

Figure 6 15 ns

t

h1

Hold time, chip select (CS) valid after address (A0
– A2) becomes invalid

t

CH

Figure 6,

Figure 7

From the first rising
edge of XIN after
address invalid

20 ns

t

h2

Hold time, data valid after IOW↑ t

DH

Figure 6 5 ns

t

d4

Delay time, chip select (CS) valid after address
valid (A0 – A2)

t

CSRW

Figure 6,

Figure 7

From the first rising
edge of XIN after
address valid

30 ns

t

d5

Delay time, address valid (A0 – A2) before

IOW

↓ t

AW

Figure 6 7 ns

t

d6

Delay time, address valid (A0 – A2) before

IOR

↓ t

AR

Figure 7 7 ns

t

d7

Delay time, chip select (CS) valid to data valid
(D7 – D0)

t

CSVD

Figure 7 CL = 75 pF 30 ns

t

d8

Delay time,

IOR

↑ to floating data (D7 – D0) t

HZ

Figure 7 CL = 75 pF 20 ns

t

d9

Delay time, EXINTR↑

or EXINTR

↓ to IRQx↑

or

IRQx

↓

Figure 8 15 ns

†

This only applies when PNPBYPASS is low.

oscillator cell maximum switching characteristics, VCC = 4.75 V, TJ = 115°C

FROM TO

INTRINSIC

DELTA

DELAY (ns)

PARAMETER

(INPUT) (OUTPUT)

DELAY

(ns)

DELAY

(ns/pF)

CL = 15 pF CL = 50 pF CL = 85 pF CL = 100 pF

t

PLH

–0.25 0.300 4.26 14.76 25.26 29.77

t

PHL

XIN

XOUT

–0.24 0.206 2.85 10.06 17.27 20.36

t

r

Output rise time, XOUT 5.83 21.15 36.47 43.04

t

f

Output fall time, XOUT 3.76 13.50 23.24 27.41

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C

L

= 75 pF (see Figure 5)

PARAMETER

ALTERNATE

SYMBOL

TEST CONDITIONS MIN MAX UNIT

t

w3

†

Pulse duration, PNPS1 low t

LW

f = 16 MHz, CLK ÷ 2 50 ns

t

w4

†

Pulse duration, PNPS1 high t

HW

f = 16 MHz, CLK ÷ 2 50 ns

t

d1

†

Delay time, XIN↑ to PNPS1↑ t

BLD

45 ns

t

d2

†

Delay time, XIN↑↓ to PNPS1↓ t

BHD

45 ns

†

This only applies when PNPBYPASS

is low.

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL

SLLS190B – MARCH 1995 – REVISED MARCH 1996

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 5)

PARAMETER

ALTERNATE

SYMBOL

FIGURE TEST CONDITIONS MIN MAX UNIT

t

d10

Delay time, stop (SIN) to set INTRPT or read
RBR to LSI interrupt (IRQx)

t

SINT

Figure 9,

Figure 10,

Figure 11

1

RCLK

cycle

t

d11

Delay time, read RBR/LSR (IOR) to reset
INTRPT (IRQx)

t

RINT

Figure 9,

Figure 10,

Figure 11

CL = 75 pF 70 ns

NOTE 5: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification

register or line status register).

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Figure 12)

PARAMETER

ALTERNATE

SYMBOL

TEST CONDITIONS MIN MAX UNIT

t

d12

Delay time, initial write (IRQx) to transmit start (SOUT) t

IRS

8 26

baudout

cycles

t

d13

Delay time, start (SOUT) to INTRPT (IRQx) t

STI

8 10

baudout

cycles

t

d14

Delay time, IOW (WR THR) to reset INTRPT (IRQx) t

HR

CL = 75 pF 50 ns

t

d15

Delay time, initial write (IOW) to INTRPT (THRE†) (IRQx) t

SI

16 34

baudout

cycles

t

d16

Delay time, read IIR† (IOR) to reset INTRPT (THRE†)
(IRQx)

t

IR

CL = 75 pF 35 ns

†

THRE = transmitter holding register empty; IIR = interrupt identification register.

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C

L

= 75 pF

PARAMETER

ALTERNATE

SYMBOL

FIGURE MIN MAX UNIT

t

d17

Delay time, WR MCR (IOW) to output (RTS, DTS) t

MDO

Figure 13 50 ns

t

d18

Delay time, modem interrupt (CTS, DSR, DCD/RI) to set INTRPT
(IRQx)

t

SIM

Figure 13 35 ns

t

d19

Delay time, RD MSR (IOR) to reset INTRPT (IRQx) t

RIM

Figure 13 40 ns

t

d20

Delay time, CTS low to SOUT↓ Figure 14 24

baudout

cycles

t

d21

Delay time, receiver threshold byte (SIN) to RTS↑ Figure 15 3

baudout

cycles

t

d22

Delay time, read of last byte in receiver FIFO (IOR) to RTS↓ Figure 15 3

baudout

cycles

t

d23

Delay time, first data bit of 16th character (SIN) to RTS↑ Figure 16 3

baudout

cycles

t

d24

Delay time, RD RBR (IOR) ↓ to RTS↓ Figure 16 3

baudout

cycles