Texas Instruments TL16PIR552PH Datasheet

D
D
IEEE 1284 Bidirectional Parallel Data (PD) Port – Compatible With Standard Centronics
Parallel Interface
– Support for Parallel Protocols: Extended
Capability Port (ECP) and Enhanced
Parallel Port (EPP) – Data Path 16-Byte FIFO Buffer – Direct Memory Access (DMA) Transfer – Decompression of Run Length Encoded
Data in ECP Reverse Mode – Direct Connection to Printer, No External
Transceiver is Needed
D
Serial Ports Have Infrared Data Association (IrDA) Inputs and Outputs – 1200 bps to 115.2 kbps Data Rate
D
16-Byte FIFOs Reduce CPU Interrupts
D
12 mA Drive Current for All 1284 Control Terminals and Parallel Port Data Terminals
D
Programmable Auto Flow Control on the UARTs
D
Capable of Running With All Existing TL16C450 Software
D
After Reset, All Registers Are Identical to the TL16C450 Register Set
D
Up to 16-MHz Clock Rate for Up to 1-Mbaud Operation
D
In the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
description
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
D
Programmable Baud-Rate Generator Allows Division of Any Input Reference Clock by 1 to (2 Internal 16× Clock
D
Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream
D
On-Board Prescaler With Programmable Divisor Values From 0 to 33
D
Independent Control of Transmit, Receive, Line Status, and Data-Set Interrupts on Each Channel
D
Fully Programmable Serial-Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation
and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud Generation (DC to 1 Mbit Per
Second)
D
False Start-Bit Detection
D
Complete Status Reporting Capabilities
D
3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
D
Line Break Generation and Detection
D
Internal Diagnostic Capabilities: – Loopback Controls for Communications
Link-Fault Isolation – Break, Parity, Overrun, and Framing
Error Simulation
D
Fully Prioritized Interrupt System Controls
D
Modem-Control Functions (CTS, RTS, DSR, DTR
, RI, and DCD)
D
Available in 80-Pin Quad Flatpack (QFP) Package
16
–1) and Generates an
The TL16PIR552 has a dual-channel universal asynchronous receiver/transmitter (UART). The UART is similar to the TL16C550C. The device serves two serial input/output ports simultaneously in microcomputer or microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete status of each channel of the dual UART can be read by the CPU at any time during functional operation. The information obtained includes the type and condition of the transfer operation being performed and the error condition.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
TL16PIR552 DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
description (continued)
The receiver and transmitter FIFOs in the UARTs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through RTS
The TL16PIR552 UART includes a programmable baud-rate generator capable of dividing a reference clock by divisors from 1 to 65535 and producing a 16× reference clock for the internal transmitter logic. Provisions are also included to use this 16× clock for the receiver logic. The UART accommodates a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start bit, eight data bits, stop bit).
Each serial channel has a prescaler with programmable divisor values from 0 to 33. The serial ports also have a dedicated infrared serial data input (IRSIN0/1) and the serial data outputs multiplex between a RS-232-type serial output or an infrared serial data output. This is selected through an internal register bit and uses the same SOUT0/1 output terminals. The same UART circuit is used for the data path for the IrDA or the RS-232 operations. Channel 0 is powered up at IR0 and channel 1 is powered up during the RS-232 mode.
In addition to dual communication capabilities, the TL16PIR552 provides the user with an IEEE 1284 host side compatible, bidirectional, parallel data port. The parallel port operates in a compatible, FIFO, extended capability port (ECP) with RLE data decompression mode, and in a enhanced parallel port (EPP) mode. The default mode of operation is compatible with the Centronics printer port. The parallel port and the two serial ports provide IBM PC/AT-compatible computers with a single device to serve a 3-port system.
output and CTS input signals.
PH PACKAGE
(TOP VIEW)
CC
RTS0
CTS0
DSR0
V
64 63 62 61 6059 58 57 5655 5453 52 51 50 49 48 4746 45 4443 4241
RI0
CC
RI1
65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1819 20 2122 2324
D7D6D5
D4
IRSIN0
DCD0
SIN0 GND
SOUT1
DTR1
RTS1
CLK_OUT1
V
SIN1
DSR1 DCD1
IRSIN1
CTS1
IBM and PC/AT are trademarks of International Business Machines Corporation.
CC
SOUT0
DTR0
V
D3D2D1
STROBE
AUTOFD
D0
GND
GND
INIT
SELECTIN
A0A1A2
PD0
IOW
PD1
IOR
PD2
CS0
PD3
TC
PD5
PD4
GND
CC
V
RESET
PDACK
PD6
CS1
RXRDY1
PD7
PPCS
ECPCS
INTRPT1
RXRDY0
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
SELECT
PERROR
INTRPT0 IOCHRDY BDO
V
CC
CLK_OUT0 PDRQ PINTR TXRDY1 TXRDY0 XOUT GND XIN TEST ACK BUSY
FAULT
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
functional block diagram
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
CLK_OUT0
prescaler
# 0 D7–D0
A2–A0
RESET
INTRPT0
RXRDY0
TXRDY0
CLK_OUT1
prescaler
# 1
RESET
INTRPT1
RXRDY1
TXRDY1
IOW
IOR
CS0
CS1
36
73
1–8
12–10
13 14 19 15 40 42 32
19 20 41 43 33
UART 0
UART 1
61 60
63 64 66 67
72 71 79 76 77 80
IR Encoder
and
Transmit
M U X
IR Incoder
and
Transmit
M U X
IR Decoder
Receiver
IR Decoder
Receiver
M
59
U X
M U X
65
68
70
78
75
SOUT0
IRSIN0
SIN0
RTS0 DTR0 CTS0 DSR0 DCD0 RI0
SOUT1
IRSIN1
SIN1
RTS1 DTR1 CST1 DSR1 DCD1 RI1
28
TEST
29
XIN
XOUT
31
22 MHz
RESET
TC
PDACK
PPCS
ECPCS
PINTR
PDRQ
IOCHRDY
NOTE A: Terminal numbers shown are for the PH package.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
19 16
17 21 22 34 35 39
1284
Port
44–47, 49–52 57
54 55 56 27 26 25
23 24
PD7–PD0 AUTOFD INIT SELECTIN STROBE ACK BUSY FAULT PERROR SELECT
3
TL16PIR552
I/O
DESCRIPTION
DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
NAME NO.
A0–A2 10–12 I Register select. A0–A2 are address lines that select the internal registers in the device. ACK 27 I Data acknowledge. In compatibility mode ACK is pulled low by the peripheral device to acknowledge
AUTOFD 57 O Autofeed. In compatibility mode AUTOFD is set low in conjunction with SELECTIN being set high to request
BDO 38 O Bus buffer output. BDO output is active (high) when the CPU is not reading data. It controls the system bus
BUSY 26 I Busy. In compatibility mode BUSY is driven high to indicate that the peripheral is not ready to receive data.
CLK_OUT0, CLK_OUT1
CS0, CS1 15,20 I Chip select. CS0 and CS1 are active low inputs that act as an enable for the write operation and a read
CTS0, CTS1
D7–D0 1–8 I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
DCD0, DCD1
DSR0, DSR1
DTR0, DTR1
ECPCS 22 I Chip select. ECPCS is used for the ECP parallel port internal registers, and is an active low signal.
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
36, 73 O Prescaler Outputs. CLK_OUT0 and CLK_OUT1 drive the UARTs.
63 79
66 77
64 76
60 71
transfer of a data byte from the host. In ECP mode, ACK AUTOFD to indicate data is available. In EPP mode, ACK signal is active high and is positive-edge triggered.
a 1284 mode. Then AUTOFD low. In EPP mode, AUTOFD is an active low output that is used to denote data read or write operations. It also provides a ninth data bit that is used to determine whether address or data information is present on the data lines in the forward mode. In EPP mode this signal is active low to denote data read or write operations. In ECP mode, AUTOFD handshaking with ACK lines contain the ECP address or data. The host drives this signal to flow control in the reverse direction. It is an “interlocked” handshake with ACK phase.
driver.
In the ECP mode, BUSY is driven high to indicate that the peripheral is not ready to receive data and is driven low to indicate that the peripheral is ready to receive data in forward mode. In reverse mode, BUSY is low when the information on the data lines are commands (RLE) and it is high when the information on the data lines is data. In EPP mode, BUSY is active low. It is driven inactive as a positive acknowledgment from the peripheral device that data or address information is completed. It is active when the peripheral is ready for the next data and address transfer. In ECP mode, BUSY deasserts to indicate that the peripheral can accept data. It handshakes with STROBE indicates whether the data lines contain the ECP command information or data. The peripheral uses this signal to control flow in the forward direction. It is an “interlocked” handshake with STROBE provides command information in the reverse direction.
operation for the UART. CS0
I Clear to send. CTS0 and CTS1 are modem-status signals whose condition can be verified by reading bit
4 (CTS) of the MSR. Bit 0 (CTS) of the MSR indicates that CTS0 last read operation from the MSR. When the modem-status interrupt is enabled, CTS0 states, and an interrupt is generated. CTS0 transmitter.
information between the CPU and the device.
I Data carrier detect. DCD0 and DCD1 are modem status signals whose condition can be verified by reading
bit 7 (DCD) of the modem status register (MSR). Bit 3 (DCD) of the MSR indicates that DCD0 has changed state since the last read from MSR. If the modem status interrupt is enabled when DCD0 or DCD1
I Data set ready. DSR0 and DSR1 are modem status signals whose condition can be verified by reading bit
5 (DSR) of the MSR. Bit 1 (DSR) of the MSR indicates that DSR0 last read from MSR. If the modem status interrupt is enabled when DSR0 interrupt is generated.
O Data terminal ready . When active, (low), DTR0 or DTR1 informs a modem or data set that the UART is ready
to establish communication. DTR0 register (MCR) to 1. DTR loop-mode operation, or resetting bit 0 of the MCR.
to transfer data from the peripheral device to the host. It is asserted low by the peripheral device
is used by the peripheral device to interrupt the host. This
is set high after the peripheral device acknowledges the signal by setting ACK
requests a byte of data from the peripheral when asserted,
in the reverse direction. In the forward direction AUTOFD indicates whether the data
. AUTOFD also provides command information in the forward
enables UART0 and CS1 enables UART1.
or CTS1 is also used in the auto-CTS mode to control the
changes state, an interrupt is generated.
or DTR1 is placed in the active state by setting bit 0 of the modem-control
x is placed in the inactive state either as a result of a master reset, during
is used in a closed loop handshake with the host
in the forward direction. In the reverse direction BUSY
. BUSY also
or CTS1 has changed states since the
or CTS1 changes
or DCD1
or DSR1 has changed state since the
or DSR1 changes state, an
4
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I/O
DESCRIPTION
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
NAME NO.
FAULT 25 I Fault indication. In compatibility mode FAULT is set high to acknowledge the 1284 mode requested. The
GND 9, 30,
INIT 54 O Initiation. In compatibility mode INIT is pulsed low to reset the interface and force a return to the compatibility
INTRPT0, INTRPT1
IOCHRDY 39 O ISA channel ready. IOCHRDY is an open drain output that extends the length of a bus cycle when it is
IOR 14 I Read input. IOR is an active low input signal that enables the selected channel to output data to D7–D0.
IOW 13 I Write input. IOW is an active low input signal that enables the data to be input to either a UART or to the
IRSIN0, IRSIN1 65, 78 I Serial data. IRSIN0 and IRSIN1 are serial inputs from an IR serial data communication device. PD0–PD7 52–49,
PDACK 17 I Parallel port DMA acknowledge. PDACK is an active low input. PDRQ 35 O DMA Request. PDRQ is used for parallel port DMA requests during ECP and FIFO modes. PERROR 23 I Peripheral error. In compatibility mode PERROR is driven high when the device encounters an error in the
PINTR 34 O Parallel port interrupt. PINTR is a 3-state output. In EPP mode this is an active high, positive-edge triggered
PPCS 21 I Chip select. PPCS is used for the parallel port internal registers and is an active-low signal. RI0,
RI1
RESET 19 I Reset. RESET is an active high reset that when asserted, clears all UART s and parallel port printer internal
RTS0, RTS1
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
48, 53,
69
40,41 O Interrupt (0–1). When active (high), INTRPT0 or INTRPT1 informs the CPU that the UART has an interrupt
47–44
67,80 I Ring Indicator. RI0 and RI1 are modem-status signals whose condition can be verified by reading bit 6 (RI)
61 72
EPP mode is user defined. In ECP mode FAULT a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP mode the peripheral is permitted (but not required) to drive this terminal low to request a reverse transfer. The request is merely a “hit” to the host; the host has ultimate control over the transfer direction. FAULT is typically used to generate an interrupt to the host CPU.
Ground terminal.
mode idle phase.In ECP mode INIT the peripheral to drive the bidirectional data lines when SELECTIN When driven low, this signal initiates a termination cycle that results in the interface returning to the compatibility mode.
to be serviced. Four conditions that cause an interrupt to be issued include a receiver error, received data is available, an empty transmitter holding register, or an enabled modem-status interrupt.
inactive.
The data output depends upon the register selected by the address A2–A0 inputs and chip select.
parallel port. The data destination depends upon the register selected by the address inputs A2–A0 and chip select.
I/O Parallel data bits (0–7). PD0–PD7 provide a byte wide input or 47–44 output port to the system. These bits
contain address, data, or RLE command data.
paper path. In ECP mode the peripheral drives PERROR low to acknowledge a reverse request (INIT Based on this signal the host determines when it is permitted to drive the data bus. In EPP mode the signal is user defined.
input.
of the MSR. Bit 2 (TERI) of the MSR indicates that the RI0 level since the last read operation from MSR. If the modem-status interrupt is enabled when this transition occurs, an interrupt is generated.
registers.
O Request to send. When active, RTS0 or RTS1 informs the modem or data set that the UART is ready to
receive data. RTS0 set to inactive (high) either as a result of master reset or during loop-mode operations or by resetting bit 1 (RTS) of the MCR. In the auto-RTS logic.
or RTS1 is set to its active level by setting the RTSx modem-control register bit and is
is driven low to place the channel in the reverse direction and it allows
mode, RTSx is set to its inactive level by the receiver threshold-control
generates an error interrupt when asserted. It provides
is high. In EPP mode INIT is active low.
/RI1 input has transitioned from a low to a high
).
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
5
TL16PIR552
I/O
DESCRIPTION
DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
NAME NO.
RXRDY0, RXRDY1
SELECT 24 I Select. In compatibility mode SELECT is set high to indicate that the printer is on line. In ECP mode SELECT
SELECTIN 55 O Select. In compatibility mode SELECTIN is set low by the host to select the peripheral device. It is set high
SIN0, SIN1 68,75 I Serial data. SIN0 and SIN1 are inputs from a connected communication device. SOUT0,
SOUT1
STROBE 56 O Data strobe. In compatibility mode STROBE is set active low to transfer data into the input latch of the
TC 16 I T erminal count. TC is an active high input during DMA and when PDACK is low . TC indicates that the data
TEST 28 I T est. TEST is tied low during normal operation. To turn the oscillator of f and measure ICCQ current, TEST
TXRDY0, TXRDY1
V
CC
XIN XOUT
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
42,43 O Receiver ready . Receiver direct-memory access (DMA) signaling is available with RXRDY0 or RXRDY1.
59, 70 O Serial outputs. Either IR output format or UART output format. Composite serial data outputs are to be
32,33 O Transmitter ready. Transmitter DMA signaling is available with TXRDY0 and TXRDY1. When operating in
18, 37,
58 62,
74 2931I/O Crystal input and output terminals. A 22-MHz clock is required to meet the internal timing required by the
When operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control-register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least one character in the receiver FIFO or receiver holding register, RXRDY0 but there are no characters in the FIFO or holding register, RXRDYx (FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDYx when it has been active but there are no more characters in the FIFO or holding register, it goes inactive (high).
indicates an affirmative response for each extensibility byte. It is high when the requested mode is supported. In EPP mode the signal is user defined.
to request the 1284 mode. In ECP mode SELECTIN to terminate the ECP mode and return to the compatibility mode. In EPP mode SELECTIN output that is used to denote address read or write operations.
connected to a communication device. SOUT0 and SOUT1 are set to the marking state (1) as a result of a master reset operation.
peripheral device. Data is valid while STROBE handshake with BUSY to transfer data or address information from the host to the peripheral device. In EPP mode this signal is set low to denote an address or data write operation to the peripheral and is set high to denote and address or data read operation from the peripheral.
transfer is complete.
is tied active (high).
the FIFO mode, one of two types of DMA signalling can be selected through FCR3. When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between the CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple DMA transfers are made continuously until the transmit FIFO has been filled.
5-V supply voltage.
1284 parallel port (minimum 40 to 60% duty cycle).
and RXRDY1 are active (low). When RXRDYx has been active
goes inactive (high). In DMA mode 1
goes active (low);
is driven high by the host. It is driven low by the host
is an active low
is low. In ECP mode STROBE is used in a closed-loop
detailed description
autoflow control
Autoflow control is comprised of auto-CTS the transmitter FIFO can emit data (see Figure 1). With auto-RTS needs more data and notifies the sending serial device (see Figure 1). When RTSx transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated when UART1 and UART2 are TL16PIR552s with enabled autoflow control. If not, overrun errors occur when the transmit-data rate exceeds the receiver FIFO read latency.
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
and auto-RTS. With auto-CTS, the CTSx input must be active before
, RTSx becomes active when the receiver
is connected to CTSx, data
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
UART1 UART2
SINx SOUTx
RTSx
SOUTx SINx
CTSx
CTSx
RTSx
Parallel
to Serial
XMT
FIFO
Flow
Control
Serial to
Parallel
RCV
FIFO
Flow
Control
D7–D0
RCV
FIFO
XMT
FIFO
Serial to
Parallel
Flow
Control
Parallel
to Serial
Flow
Control
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
auto-RTS (see Figure 1)
Auto-RTS
data-flow control originates in the receiver timing and control block (see functional block diagram) and is linked to the programmed receiver-FIFO trigger level. When the receiver-FIFO level reaches a trigger level of 1, 4, or 8 (see Figure 3), RTSx
is deasserted. With trigger levels of 1, 4, and 8, the sending UART may send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send) because it may not recognize the deassertion of RTSx
until after it has begun sending the additional byte. RTSx is automatically reasserted once the receiver (RCV) FIFO is emptied by reading the receiver buffer register(RBR).
If the trigger level is 14 (see Figure 6), RTSx present on the SINx line. RTSx
is reasserted when the RCV FIFO has at least one available byte space.
is deasserted after the first data bit of the sixteenth character is
D7–D0
auto-CTS
(see Figure 1)
The transmitter circuitry checks CTSx byte. To stop the transmitter from sending the following byte, CTSx
before sending the next data byte. When CTSx is active, it sends the next
must be released before the middle of the last stop bit that is currently being sent (see Figure 2). The auto-CTS system. When flow control is enabled, the CTSx automatically controls its own transmitter. Without auto-CTS
level changes do not trigger host interrupts because the device
, the transmitter sends any data present in the
function reduces interrupts to the host
transmit FIFO and a receiver overrun error may result.
enabling autoflow control and auto-CTS
Autoflow control is enabled by setting modem-control register (MCR) bit 5 (autoflow enable or AFE) and bit 1 (RTS) to 1. Autoflow incorporates both auto-RTS MCR should be reset to 0 (this assumes a control signal is driving CTSx
auto-CTS
SOUTx
CTSx
NOTE A: When CTSx is low, the transmitter keeps sending serial data out. When CTSx goes high before the middle of the last stop bit of the current
and auto-RTS functional timing
Start Bits 0–7 Start Bits 0–7 Start Bits 0–7
byte, the transmitter finishes sending the current byte but it does not send the next byte. When CTSx begins sending data again.
Stop Stop Stop
and auto-CTS. When only auto-CTS is desired, bit 1 in the
).
goes from high to low, the transmitter
Figure 2. CTS Functional Timing
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7
TL16PIR552 DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
The receiver-FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
SINx
RTSx
IOR
(IOR RBR)
NOTES: A. N = RCV-FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding
Start Byte N Start Byte N+1 Start Byte
Stop Stop Stop
12
N N+1
auto-RTS
section.
Figure 3. RTS Functional Timing, RCV-FIFO Trigger Level = 1,4, or 8 Bytes
SINx
RTSx
IOR
(IOR RBR)
NOTE A: RTSx is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the sixteenth
byte. RTSx than one byte of space available. When the receive FIFO is full, the first receive buffer-register read reasserts RTSx
Byte 14 Byte 15
RTS Released After the
First Data Bit of Byte 16
is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more
Start Byte 18 StopStart Byte 16 Stop
.
Figure 4. RTS Functional Timing, Receiver - FIFO Trigger Level = 14 Bytes
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, I Output clamp current, I Output clamp current, level shift, I Virtual junction, T
150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. This applies to external input and bidirectional buffers. VI < VCC does not apply to fail-safe terminals.
3. This applies to external output and bidirectional buffers. VO < VCC does not apply to fail-safe terminals.
–0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
–0.5 V to V
I
–0.5 V to V
O
(V
IK
OK
< 0 or V
I
(V
O
> VCC) (See Note 2) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
< 0 or V
OK
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
> VCC) (See Note 3) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
< 0 or V
O
> VCC) (See Note 3) ±20 mA. . . . . . . . . . . . . . . . . . . . . . .
O
CC CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V Input voltage, V High-level input voltage, V Low-level input voltage, V Input transition (rise and fall) time, t Operating ambient temperature range, T Virtual junction temperature, T
CC
I
IH
IL
t
A
J
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
V
OH
V
OL
V
IT+
V
IT–
V
hys
I
OZ
I
IL
I
IH
12 mA for 1284 control, 3 mA for all other outputs
Applies to external input and bidirectional buffers with hysteresis. All input buffers have hysteresis.
§
A 3-state or open-drain output must be in the high-impedance state.
NOTE 4: All 1284 output and data terminals are low-noise TTL 12 mA drivers. The type of the driver, push/pull or open drain, is switched
High-level output voltage IOH = Rated Low-level output voltage IOL = Rated Positive-going input threshold voltage Negative-going input threshold voltage Hysteresis‡ (V 3-state-output Hi-Z current VI = VCC or GND Low-level input current VI = GND –1 µA High-level input current VI = V
dynamically based on the 1284 mode.
IT+
– V
) TTL compatible 0.25 0.7 V
IT–
TTL compatible 2 V TTL compatible 0.8 V
CC
4.75 5 5.25 V 0 V 2 V
–0.5 0.8 V
0 25 ns 0 25 70 °C 0 25 115 °C
COMMERCIAL
MIN MAX
VCC –0.8 V
§
CC CC
0.5 V
±10 µA
1 µA
V V
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
9
TL16PIR552 DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
system timing requirements over recommended ranges of supply voltage and operating free-air temperature
ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
t
Cycle time, read (tw7 + td8) RC 65 ns
cR
t
Cycle time, write (tw6 + td5) WC 59 ns
cW
t
Pulse duration, IOW t
w1
t
Pulse duration, IOR t
w2
t
Pulse duration, RESET t
w3
t
Setup time, data valid before IOW t
su1
t
Setup time, CTS before midpoint of stop bit 16 10 ns
su2
t
Hold time, CS valid after IOW t
h1
t
Hold time, address valid after IOW t
h2
t
Hold time, data valid after IOW t
h3
t
Hold time, chip select valid after IOR t
h4
t
Hold time, address valid after IOR t
h5
t
Delay time, CS valid before IOW t
d1
t
Delay time, address valid before IOW t
d2
t
Delay time, CS valid to IOR t
d3
t
Delay time, address valid to IOR t
d4
t
Delay time, IORto data valid t
d5
t
Delay time, IORto floating data t
d6
WR
RD
MR
DS
WCS
WA
DH
RCS
RA
CSW
AW
CSR
AR
RVD
HZ
5 50 ns 6 50 ns
1 µs
5 20 ns
5 15 ns 5 15 ns 5 15 ns 6 20 ns 6 20 ns 5 10 ns 5 13 ns 6 10 ns 6 13 ns 6 CL = 75 pF 20 ns 6 CL = 75 pF 10 ns
receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 5)
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
Delay time, stop to INTRPTx or read RBR to
t
d7
LSI INTRPT or stop to RXRDY Delay time, read RBR/INTRPT or read to RXRDY
t
d8
or IOR
to INTRPTx
NOTE 5: In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt-
identification register or line-status register).
t
SINT
t
RINT
7, 8, 9,
10, 11
7, 8, 9,
10, 11
RCLK
1
cycle
CL = 75 pF 70 ns
10
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature
PARAMETER ALT. SYMBOL FIGURE TEST CONDITIONS MIN MAX UNIT
baud-
t
Delay time, INTRPTx to SOUTx t
d9
t
Delay time, start to INTRPTx t
d10
t
Delay time, IOW to INTRPTx t
d11
t
Delay time, IOW to INTRPTx t
d12
t
Delay time, IOR IIRto INTRPTx t
d13
t
Delay time, IOWto TXRDYx t
d14
t
Delay time, SOUTx to TXRDYx
d15
THRE = transmitter holding-register empty; IIR = interrupt-identification register.
IRS
STI
HR
WXI
t
SXA
SI
IR
12 8 24
12 8 10
12 CL = 75 pF 50 ns
12 16 34
12 CL = 75 pF 35 ns
13,14 CL = 75 pF 30 ns
13, 14 CL = 75 pF 9
modem-control switching characteristics over recommended ranges of supply voltage and
= 75 pF
operating free-air temperature, C
PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT
t
Delay time, CTSx, DSRx, DCDx to INTRPTx or RIto INTRPTx t
d16
t
Delay time, IORto INTRPTx 15 24
d17
t
Delay time, CTSx to SOUTx 16 2
d18
t
Delay time, midpoint of stop bit to RTSx 17 2
d19
t
Delay time, IOR to RTSx 17 2
d20
t
Delay time, first data bit of the sixteenth character to RTSx 18 2
d21
t
Delay time, IORto RTSx t
d22
t
Delay time, IOWto RTSx, DTRx↑↓ t
d23
L
RIM
MDO
SIM
15 35 ns
18 40 ns 15 35 ns
out
cycles
baud-
out
cycles
baud-
out
cycles
baud-
out
cycles
baudout
cycles
baudout
cycles
baudout
cycles
baudout
cycles
baudout
cycles
IR signal switching characteristics over recommended ranges of supply voltage and operating free-air temperature, C
t
Delay time, internal SOUTx to SOUTx (IR mode) 19 8
d24
t
Delay time, incoming IRSINxto internal SINx 19 15 ns
d25
= 75 pF
L
PARAMETER ALT. SYMBOL FIGURE MIN MAX UNIT
baud-
out
cycles
parallel-port timing requirements over recommended ranges of supply voltage and operating free-air temperature
PARAMETER FIGURE MIN MAX UNITS
t
d26
t
d27
t
w4
Delay time, FAULT to PINTR (ECP) 20 20 ns Delay time, ACKto PINTR (EPP) 20 20 ns Pulse duration, PINTR (ECP) to PINTR (ECP)(ECP and EPP modes) 20 80 100 ns
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
11
TL16PIR552 DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
parallel-port EPP data or address write cycle timing requirements over recommended ranges of supply voltage and operating free-air temperature
PARAMETER FIGURE MIN MAX UNITS
t
h6
t
d28
t
d29
t
d30
t
d31
t
d32
t
d33
t
d34
t
d35
t
d36
t
d37
t
d38
t
d39
Hold time, BUSY to PD invalid 21 60 140 ns Delay time, IOWto PD valid 21 10 30 ns Delay time, BUSY to STROBE 21 60 100 ns Delay time, STROBE to AUTOFD 21 0 10 ns Delay time, BUSY to AUTOFD 21 60 100 ns Timeout, IOW to BUSY 21 10 12 µs Delay time, SELECTIN to BUSY 21 200 ns Delay time, IOW to IOCHRDY 21 0 25 ns Delay time, BUSY to IOCHRDY 21 60 120 ns Delay time, Delay time, IOWto STROBE 21 0 40 ns Delay time, IOW to IOW or IOR 21 60 ns Delay time, BUSY to STROBE 21 20 40 ns
IOCHRDY
to IOW↑ 21 30 ns
parallel-port EPP data or adress read cycle timing requirements over recommended ranges of supply voltage and operating free-air temperature
PARAMETER FIGURE MIN MAX UNITS
t
h7
t
h8
t
d40
t
d41
t
d42
t
d43
t
d44
t
d45
t
d46
t
d47
Hold time, AUTOFD, SELECTIN to PD hi-Z 22 10 ns Hold time, IOR to D hi-Z (Hold Time) 22 0 20 ns Delay time, BUSY to AUTOFD, SELECTIN 22 120 200 ns Delay time, AUTOFD, SELECTIN to PD Valid 22 110 ns Delay time, IOR to IOCHRDY 22 0 25 ns Delay time, BUSY to IOCHRDY 22 80 130 ns Delay time, PD valid to D valid 22 0 25 ns Timeout, IORto BUSY 22 10 12 µs Delay time, IOR to IOW or IOR 22 60 ns Delay time, IOCHRDY to IOR 22 30 ns
parallel-port FIFO timing requirements over recommended ranges of supply voltage and operating free-air temperature
PARAMETER FIGURE MIN MAX UNITS
t
su3
t
h9
t
w5
t
d48
t
d49
Setup time, PD valid to STROBE 23 550 ns Hold time, PD hold from STROBE 23 500 ns Pulse duration, STROBE pulse width low 23 500 ns Delay time, STROBE to BUSY active 23 125 ns Delay time, BUSY to STROBE 23 600 ns
12
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
parallel-port (ECP) reverse timing requirements over recommended ranges of supply voltage and operating free-air temperature
PARAMETER FIGURE MIN MAX UNITS
t
su4
t
d50
t
d51
t
d52
t
d53
t
d54
parallel-port (ECP) forward timing requirements over recommended ranges of supply voltage and operating free-air temperature
t
su5
t
h10
t
d55
t
d56
t
d57
t
d58
t
d59
t
d60
Setup time, PD valid to ACK 24 0 ns Delay time, AUTOFD to PD changed 24 0 ns Delay time, ACK to AUTOFD 24 80 200 ns Delay time, ACK to AUTOFD 24 80 120 ns Delay time, AUTOFD to ACK 24 25 ns Delay time, AUTOFD to ACK 24 150 ns
PARAMETER FIGURE MIN MAX UNITS
Setup time, PD valid to STROBE 25 0 90 ns Hold time, BUSY to PD changed 25 30 180 ns Delay time, AUTOFD valid to STROBE 25 0 45 ns Delay time, BUSY to AUTOFD changed 25 25 180 ns Delay time, STROBE to BUSY 25 370 ns Delay time, STROBE to BUSY 25 295 ns Delay time, BUSY to STROBE 25 80 120 ns Delay time, BUSY to STROBE 25 20 60 ns
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
13
TL16PIR552 DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
A0–A2
CS0, CS1
IOW
D7–D0
A0–A2
, CS1
CS0
50%
50% 50%
Valid Valid
Valid Valid
t
h1
t
t
d1
t
d2
50% 50%
t
su1
w1
Active
Valid Data
Figure 5. Write-Cycle Timing
50%
50%
Valid Valid
Valid Valid
t
h2
50%
t
h3
50%
50%
IOR
D7–D0
t
h4
t
t
d3
t
d4
50% 50%
t
d5
w2
Active
t
h5
Valid Data
Figure 6. Read-Cycle Timing
t
d6
14
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Sample Clock
TL16C450 Mode:
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
RCLK
(Internal)
8 CLKs
SINx
Sample Clock
(Internal)
INTRPTx
(data ready)
INTRPTx
(RCV error)
IOR
(read RBR)
IOR
(read LSR)
Parity StopStart Data Bits 5–8
t
d7
Figure 7. Receiver Timing
50%
50%
Active
t
d8
50%
50%
t
d8
50%50%
Active
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
15
TL16PIR552 DUAL UART WITH DUAL IrDA AND 1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
SINx
Sample Clock
Trigger Level
INTRPTx
(FCR6, 7 = 0, 0)
INTRPTx
Line-Status
Interrupt (LSI)
IOR
(RD LSR)
IOR
(RD RBR)
NOTE A: For a timeout interrupt, td7 = 9 RCLKs.
Data Bits 5–8
(see Note A)
Figure 8. Receive FIFO First Byte (Sets DR Bit)
Stop
(FIFO at or above
50%
t
d7
t
d8
Active
t
50%50%
50%
50%
50%
d8
Active
trigger level) (FIFO below
trigger level)
SINx
Sample Clock
Timeout or
Trigger Level
Interrupt
(see Note A)
Line-Status
Interrupt (LSI)
IOR
(RD LSR)
IOR
(RD RBR)
Previous Byte
Read From FIFO
NOTE A: For a timeout interrupt, td7 = 9 RCLKs.
Stop
50%
t
d7
Top Byte of FIFO
t
d7
Active Active
50% 50%
t
d8
t
d8
50%
50%50%
50%
Figure 9. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set)
(FIFO at or above trigger level)
(FIFO below trigger level)
16
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