IEEE 1284 Bidirectional Parallel Data (PD)
Port
– Compatible With Standard Centronics
Parallel Interface
– Support for Parallel Protocols: Extended
Capability Port (ECP) and Enhanced
Parallel Port (EPP)
– Data Path 16-Byte FIFO Buffer
– Direct Memory Access (DMA) Transfer
– Decompression of Run Length Encoded
Data in ECP Reverse Mode
– Direct Connection to Printer, No External
Transceiver is Needed
D
Serial Ports Have Infrared Data Association
(IrDA) Inputs and Outputs
– 1200 bps to 115.2 kbps Data Rate
D
16-Byte FIFOs Reduce CPU Interrupts
D
12 mA Drive Current for All 1284 Control
Terminals and Parallel Port Data Terminals
D
Programmable Auto Flow Control on the
UARTs
D
Capable of Running With All Existing
TL16C450 Software
D
After Reset, All Registers Are Identical to
the TL16C450 Register Set
D
Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation
D
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
description
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
D
Programmable Baud-Rate Generator
Allows Division of Any Input Reference
Clock by 1 to (2
Internal 16× Clock
D
Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
D
On-Board Prescaler With Programmable
Divisor Values From 0 to 33
D
Independent Control of Transmit, Receive,
Line Status, and Data-Set Interrupts on
Each Channel
D
Fully Programmable Serial-Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1 Mbit Per
Second)
D
False Start-Bit Detection
D
Complete Status Reporting Capabilities
D
3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
D
Line Break Generation and Detection
D
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link-Fault Isolation
– Break, Parity, Overrun, and Framing
Error Simulation
D
Fully Prioritized Interrupt System Controls
D
Modem-Control Functions (CTS, RTS, DSR,
DTR
, RI, and DCD)
D
Available in 80-Pin Quad Flatpack (QFP)
Package
16
–1) and Generates an
The TL16PIR552 has a dual-channel universal asynchronous receiver/transmitter (UART). The UART is similar
to the TL16C550C. The device serves two serial input/output ports simultaneously in microcomputer or
microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual UART can be read by the CPU at any time during
functional operation. The information obtained includes the type and condition of the transfer operation being
performed and the error condition.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1996, Texas Instruments Incorporated
1
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
description (continued)
The receiver and transmitter FIFOs in the UARTs store up to 16 bytes including three additional bits of error
status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can
significantly reduce software overload and increase system efficiency by automatically controlling serial data
flow through RTS
The TL16PIR552 UART includes a programmable baud-rate generator capable of dividing a reference clock
by divisors from 1 to 65535 and producing a 16× reference clock for the internal transmitter logic. Provisions
are also included to use this 16× clock for the receiver logic. The UART accommodates a 1-Mbaud serial rate
(16-MHz input clock) so that a bit time is 1 µs and a typical character time is 10 µs (start bit, eight data bits, stop
bit).
Each serial channel has a prescaler with programmable divisor values from 0 to 33. The serial ports also have
a dedicated infrared serial data input (IRSIN0/1) and the serial data outputs multiplex between a RS-232-type
serial output or an infrared serial data output. This is selected through an internal register bit and uses the same
SOUT0/1 output terminals. The same UART circuit is used for the data path for the IrDA or the RS-232
operations. Channel 0 is powered up at IR0 and channel 1 is powered up during the RS-232 mode.
In addition to dual communication capabilities, the TL16PIR552 provides the user with an IEEE 1284 host side
compatible, bidirectional, parallel data port. The parallel port operates in a compatible, FIFO, extended
capability port (ECP) with RLE data decompression mode, and in a enhanced parallel port (EPP) mode. The
default mode of operation is compatible with the Centronics printer port. The parallel port and the two serial ports
provide IBM PC/AT-compatible computers with a single device to serve a 3-port system.
A0–A210–12IRegister select. A0–A2 are address lines that select the internal registers in the device.
ACK27IData acknowledge. In compatibility mode ACK is pulled low by the peripheral device to acknowledge
AUTOFD57OAutofeed. In compatibility mode AUTOFD is set low in conjunction with SELECTIN being set high to request
BDO38OBus buffer output. BDO output is active (high) when the CPU is not reading data. It controls the system bus
BUSY26IBusy. In compatibility mode BUSY is driven high to indicate that the peripheral is not ready to receive data.
CLK_OUT0,
CLK_OUT1
CS0, CS115,20IChip select. CS0 and CS1 are active low inputs that act as an enable for the write operation and a read
CTS0,
CTS1
D7–D01–8I/OData bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
DCD0,
DCD1
DSR0,
DSR1
DTR0,
DTR1
ECPCS22IChip select. ECPCS is used for the ECP parallel port internal registers, and is an active low signal.
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
36, 73OPrescaler Outputs. CLK_OUT0 and CLK_OUT1 drive the UARTs.
63
79
66
77
64
76
60
71
transfer of a data byte from the host. In ECP mode, ACK
AUTOFD
to indicate data is available. In EPP mode, ACK
signal is active high and is positive-edge triggered.
a 1284 mode. Then AUTOFD
low. In EPP mode, AUTOFD is an active low output that is used to denote data read or write operations.
It also provides a ninth data bit that is used to determine whether address or data information is present
on the data lines in the forward mode. In EPP mode this signal is active low to denote data read or write
operations. In ECP mode, AUTOFD
handshaking with ACK
lines contain the ECP address or data. The host drives this signal to flow control in the reverse direction.
It is an “interlocked” handshake with ACK
phase.
driver.
In the ECP mode, BUSY is driven high to indicate that the peripheral is not ready to receive data and is
driven low to indicate that the peripheral is ready to receive data in forward mode. In reverse mode, BUSY
is low when the information on the data lines are commands (RLE) and it is high when the information on
the data lines is data. In EPP mode, BUSY is active low. It is driven inactive as a positive acknowledgment
from the peripheral device that data or address information is completed. It is active when the peripheral
is ready for the next data and address transfer. In ECP mode, BUSY deasserts to indicate that the peripheral
can accept data. It handshakes with STROBE
indicates whether the data lines contain the ECP command information or data. The peripheral uses this
signal to control flow in the forward direction. It is an “interlocked” handshake with STROBE
provides command information in the reverse direction.
operation for the UART. CS0
IClear to send. CTS0 and CTS1 are modem-status signals whose condition can be verified by reading bit
4 (CTS) of the MSR. Bit 0 (∆CTS) of the MSR indicates that CTS0
last read operation from the MSR. When the modem-status interrupt is enabled, CTS0
states, and an interrupt is generated. CTS0
transmitter.
information between the CPU and the device.
IData carrier detect. DCD0 and DCD1 are modem status signals whose condition can be verified by reading
bit 7 (DCD) of the modem status register (MSR). Bit 3 (∆DCD) of the MSR indicates that DCD0
has changed state since the last read from MSR. If the modem status interrupt is enabled when DCD0 or
DCD1
IData set ready. DSR0 and DSR1 are modem status signals whose condition can be verified by reading bit
5 (DSR) of the MSR. Bit 1 (∆DSR) of the MSR indicates that DSR0
last read from MSR. If the modem status interrupt is enabled when DSR0
interrupt is generated.
OData terminal ready . When active, (low), DTR0 or DTR1 informs a modem or data set that the UART is ready
to establish communication. DTR0
register (MCR) to 1. DTR
loop-mode operation, or resetting bit 0 of the MCR.
to transfer data from the peripheral device to the host. It is asserted low by the peripheral device
is used by the peripheral device to interrupt the host. This
is set high after the peripheral device acknowledges the signal by setting ACK
requests a byte of data from the peripheral when asserted,
in the reverse direction. In the forward direction AUTOFD indicates whether the data
. AUTOFD also provides command information in the forward
enables UART0 and CS1 enables UART1.
or CTS1 is also used in the auto-CTS mode to control the
changes state, an interrupt is generated.
or DTR1 is placed in the active state by setting bit 0 of the modem-control
x is placed in the inactive state either as a result of a master reset, during
is used in a closed loop handshake with the host
in the forward direction. In the reverse direction BUSY
. BUSY also
or CTS1 has changed states since the
or CTS1 changes
or DCD1
or DSR1 has changed state since the
or DSR1 changes state, an
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I/O
DESCRIPTION
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
NAMENO.
FAULT25IFault indication. In compatibility mode FAULT is set high to acknowledge the 1284 mode requested. The
GND9, 30,
INIT54OInitiation. In compatibility mode INIT is pulsed low to reset the interface and force a return to the compatibility
INTRPT0,
INTRPT1
IOCHRDY39OISA channel ready. IOCHRDY is an open drain output that extends the length of a bus cycle when it is
IOR14IRead input. IOR is an active low input signal that enables the selected channel to output data to D7–D0.
IOW13IWrite input. IOW is an active low input signal that enables the data to be input to either a UART or to the
IRSIN0, IRSIN165, 78ISerial data. IRSIN0 and IRSIN1 are serial inputs from an IR serial data communication device.
PD0–PD752–49,
PDACK17IParallel port DMA acknowledge. PDACK is an active low input.
PDRQ35ODMA Request. PDRQ is used for parallel port DMA requests during ECP and FIFO modes.
PERROR23IPeripheral error. In compatibility mode PERROR is driven high when the device encounters an error in the
PINTR34OParallel port interrupt. PINTR is a 3-state output. In EPP mode this is an active high, positive-edge triggered
PPCS21IChip select. PPCS is used for the parallel port internal registers and is an active-low signal.
RI0,
RI1
RESET19IReset. RESET is an active high reset that when asserted, clears all UART s and parallel port printer internal
RTS0,
RTS1
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
48, 53,
69
40,41OInterrupt (0–1). When active (high), INTRPT0 or INTRPT1 informs the CPU that the UART has an interrupt
47–44
67,80IRing Indicator. RI0 and RI1 are modem-status signals whose condition can be verified by reading bit 6 (RI)
61
72
EPP mode is user defined. In ECP mode FAULT
a mechanism for peer-to-peer communication. This signal is valid only in the forward direction. During ECP
mode the peripheral is permitted (but not required) to drive this terminal low to request a reverse transfer.
The request is merely a “hit” to the host; the host has ultimate control over the transfer direction. FAULT
is typically used to generate an interrupt to the host CPU.
Ground terminal.
mode idle phase.In ECP mode INIT
the peripheral to drive the bidirectional data lines when SELECTIN
When driven low, this signal initiates a termination cycle that results in the interface returning to the
compatibility mode.
to be serviced. Four conditions that cause an interrupt to be issued include a receiver error, received data
is available, an empty transmitter holding register, or an enabled modem-status interrupt.
inactive.
The data output depends upon the register selected by the address A2–A0 inputs and chip select.
parallel port. The data destination depends upon the register selected by the address inputs A2–A0 and
chip select.
I/OParallel data bits (0–7). PD0–PD7 provide a byte wide input or 47–44 output port to the system. These bits
contain address, data, or RLE command data.
paper path. In ECP mode the peripheral drives PERROR low to acknowledge a reverse request (INIT
Based on this signal the host determines when it is permitted to drive the data bus. In EPP mode the signal
is user defined.
input.
of the MSR. Bit 2 (TERI) of the MSR indicates that the RI0
level since the last read operation from MSR. If the modem-status interrupt is enabled when this transition
occurs, an interrupt is generated.
registers.
ORequest to send. When active, RTS0 or RTS1 informs the modem or data set that the UART is ready to
receive data. RTS0
set to inactive (high) either as a result of master reset or during loop-mode operations or by resetting bit
1 (RTS) of the MCR. In the auto-RTS
logic.
or RTS1 is set to its active level by setting the RTSx modem-control register bit and is
is driven low to place the channel in the reverse direction and it allows
mode, RTSx is set to its inactive level by the receiver threshold-control
generates an error interrupt when asserted. It provides
is high. In EPP mode INIT is active low.
/RI1 input has transitioned from a low to a high
).
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TL16PIR552
I/O
DESCRIPTION
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
Terminal Functions
TERMINAL
NAMENO.
RXRDY0,
RXRDY1
SELECT24ISelect. In compatibility mode SELECT is set high to indicate that the printer is on line. In ECP mode SELECT
SELECTIN55OSelect. In compatibility mode SELECTIN is set low by the host to select the peripheral device. It is set high
SIN0, SIN168,75ISerial data. SIN0 and SIN1 are inputs from a connected communication device.
SOUT0,
SOUT1
STROBE56OData strobe. In compatibility mode STROBE is set active low to transfer data into the input latch of the
TC16IT erminal count. TC is an active high input during DMA and when PDACK is low . TC indicates that the data
TEST28IT est. TEST is tied low during normal operation. To turn the oscillator of f and measure ICCQ current, TEST
TXRDY0,
TXRDY1
V
CC
XIN
XOUT
NOTE 1: All parallel port control outputs are open drain outputs in the Centronics mode, and push-pull outputs in other modes.
42,43OReceiver ready . Receiver direct-memory access (DMA) signaling is available with RXRDY0 or RXRDY1.
59, 70OSerial outputs. Either IR output format or UART output format. Composite serial data outputs are to be
32,33OTransmitter ready. Transmitter DMA signaling is available with TXRDY0 and TXRDY1. When operating in
18, 37,
58 62,
74
2931I/OCrystal input and output terminals. A 22-MHz clock is required to meet the internal timing required by the
When operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO
control-register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode
0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports
multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been
emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), if there is at least one character in the receiver
FIFO or receiver holding register, RXRDY0
but there are no characters in the FIFO or holding register, RXRDYx
(FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDYx
when it has been active but there are no more characters in the FIFO or holding register, it goes inactive
(high).
indicates an affirmative response for each extensibility byte. It is high when the requested mode is
supported. In EPP mode the signal is user defined.
to request the 1284 mode. In ECP mode SELECTIN
to terminate the ECP mode and return to the compatibility mode. In EPP mode SELECTIN
output that is used to denote address read or write operations.
connected to a communication device. SOUT0 and SOUT1 are set to the marking state (1) as a result of
a master reset operation.
peripheral device. Data is valid while STROBE
handshake with BUSY to transfer data or address information from the host to the peripheral device. In EPP
mode this signal is set low to denote an address or data write operation to the peripheral and is set high
to denote and address or data read operation from the peripheral.
transfer is complete.
is tied active (high).
the FIFO mode, one of two types of DMA signalling can be selected through FCR3. When operating in the
TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer
is made between the CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple DMA transfers
are made continuously until the transmit FIFO has been filled.
5-V supply voltage.
1284 parallel port (minimum 40 to 60% duty cycle).
and RXRDY1 are active (low). When RXRDYx has been active
goes inactive (high). In DMA mode 1
goes active (low);
is driven high by the host. It is driven low by the host
is an active low
is low. In ECP mode STROBE is used in a closed-loop
detailed description
autoflow control
Autoflow control is comprised of auto-CTS
the transmitter FIFO can emit data (see Figure 1). With auto-RTS
needs more data and notifies the sending serial device (see Figure 1). When RTSx
transmission does not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated
when UART1 and UART2 are TL16PIR552s with enabled autoflow control. If not, overrun errors occur when
the transmit-data rate exceeds the receiver FIFO read latency.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
and auto-RTS. With auto-CTS, the CTSx input must be active before
, RTSx becomes active when the receiver
is connected to CTSx, data
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
UART1UART2
SINxSOUTx
RTSx
SOUTxSINx
CTSx
CTSx
RTSx
Parallel
to Serial
XMT
FIFO
Flow
Control
Serial to
Parallel
RCV
FIFO
Flow
Control
D7–D0
RCV
FIFO
XMT
FIFO
Serial to
Parallel
Flow
Control
Parallel
to Serial
Flow
Control
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
auto-RTS (see Figure 1)
Auto-RTS
data-flow control originates in the receiver timing and control block (see functional block diagram)
and is linked to the programmed receiver-FIFO trigger level. When the receiver-FIFO level reaches a trigger
level of 1, 4, or 8 (see Figure 3), RTSx
is deasserted. With trigger levels of 1, 4, and 8, the sending UART may
send an additional byte after the trigger level is reached (assuming the sending UART has another byte to send)
because it may not recognize the deassertion of RTSx
until after it has begun sending the additional byte. RTSx
is automatically reasserted once the receiver (RCV) FIFO is emptied by reading the receiver buffer
register(RBR).
If the trigger level is 14 (see Figure 6), RTSx
present on the SINx line. RTSx
is reasserted when the RCV FIFO has at least one available byte space.
is deasserted after the first data bit of the sixteenth character is
D7–D0
auto-CTS
(see Figure 1)
The transmitter circuitry checks CTSx
byte. To stop the transmitter from sending the following byte, CTSx
before sending the next data byte. When CTSx is active, it sends the next
must be released before the middle of the
last stop bit that is currently being sent (see Figure 2). The auto-CTS
system. When flow control is enabled, the CTSx
automatically controls its own transmitter. Without auto-CTS
level changes do not trigger host interrupts because the device
, the transmitter sends any data present in the
function reduces interrupts to the host
transmit FIFO and a receiver overrun error may result.
enabling autoflow control and auto-CTS
Autoflow control is enabled by setting modem-control register (MCR) bit 5 (autoflow enable or AFE) and bit 1
(RTS) to 1. Autoflow incorporates both auto-RTS
MCR should be reset to 0 (this assumes a control signal is driving CTSx
auto-CTS
SOUTx
CTSx
NOTE A: When CTSx is low, the transmitter keeps sending serial data out. When CTSx goes high before the middle of the last stop bit of the current
and auto-RTS functional timing
StartBits 0–7StartBits 0–7StartBits 0–7
byte, the transmitter finishes sending the current byte but it does not send the next byte. When CTSx
begins sending data again.
StopStopStop
and auto-CTS. When only auto-CTS is desired, bit 1 in the
).
goes from high to low, the transmitter
Figure 2. CTS Functional Timing
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
The receiver-FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
SINx
RTSx
IOR
(IOR RBR)
NOTES: A. N = RCV-FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Output clamp current, level shift, I
Virtual junction, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. This applies to external input and bidirectional buffers. VI < VCC does not apply to fail-safe terminals.
3. This applies to external output and bidirectional buffers. VO < VCC does not apply to fail-safe terminals.
Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V
Input transition (rise and fall) time, t
Operating ambient temperature range, T
Virtual junction temperature, T
CC
I
IH
IL
t
A
J
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
V
OH
V
OL
V
IT+
V
IT–
V
hys
I
OZ
I
IL
I
IH
†
12 mA for 1284 control, 3 mA for all other outputs
‡
Applies to external input and bidirectional buffers with hysteresis. All input buffers have hysteresis.
§
A 3-state or open-drain output must be in the high-impedance state.
NOTE 4: All 1284 output and data terminals are low-noise TTL 12 mA drivers. The type of the driver, push/pull or open drain, is switched
High-level output voltageIOH = Rated
Low-level output voltageIOL = Rated
Positive-going input threshold voltage
Negative-going input threshold voltage
Hysteresis‡ (V
3-state-output Hi-Z currentVI = VCC or GND
Low-level input currentVI = GND–1µA
High-level input currentVI = V
dynamically based on the 1284 mode.
IT+
– V
)TTL compatible0.250.7V
IT–
‡
‡
TTL compatible2V
TTL compatible0.8V
†
†
CC
4.7555.25V
0V
2V
–0.50.8V
025ns
02570°C
025115°C
COMMERCIAL
MINMAX
VCC –0.8V
§
CC
CC
0.5V
±10µA
1µA
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT. SYMBOL FIGURE TEST CONDITIONSMINMAXUNIT
t
Cycle time, read (tw7 + td8)RC65ns
cR
t
Cycle time, write (tw6 + td5)WC59ns
cW
t
Pulse duration, IOWt
w1
t
Pulse duration, IORt
w2
t
Pulse duration, RESETt
w3
t
Setup time, data valid before IOW↑t
su1
t
Setup time, CTS↑ before midpoint of stop bit1610ns
modem-control switching characteristics over recommended ranges of supply voltage and
= 75 pF
operating free-air temperature, C
PARAMETERALT. SYMBOL FIGUREMINMAXUNIT
t
Delay time, CTSx, DSRx, DCDx↓ to INTRPTx↑ or RI↑ to INTRPTx↑t
d16
t
Delay time, IOR↑ to INTRPTx↓1524
d17
t
Delay time, CTSx↓ to SOUTx↓162
d18
t
Delay time, midpoint of stop bit to RTSx↑172
d19
t
Delay time, IOR↓ to RTSx↓172
d20
t
Delay time, first data bit of the sixteenth character to RTSx↑182
d21
t
Delay time, IOR↓ to RTSx↓t
d22
t
Delay time, IOW↑ to RTSx, DTRx↑↓t
d23
L
RIM
MDO
SIM
1535ns
1840ns
1535ns
out
cycles
baud-
out
cycles
baud-
out
cycles
baud-
out
cycles
baudout
cycles
baudout
cycles
baudout
cycles
baudout
cycles
baudout
cycles
IR signal switching characteristics over recommended ranges of supply voltage and operating
free-air temperature, C
t
Delay time, internal SOUTx↓ to SOUTx↑ (IR mode)198
d24
t
Delay time, incoming IRSINx↑ to internal SINx↓1915ns
d25
= 75 pF
L
PARAMETERALT. SYMBOL FIGUREMINMAXUNIT
baud-
out
cycles
parallel-port timing requirements over recommended ranges of supply voltage and operating
free-air temperature
PARAMETERFIGUREMINMAXUNITS
t
d26
t
d27
t
w4
Delay time, FAULT↓ to PINTR (ECP)↓2020ns
Delay time, ACK↓ to PINTR (EPP)↓2020ns
Pulse duration, PINTR (ECP)↓ to PINTR (ECP)↑ (ECP and EPP modes)2080100ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
parallel-port EPP data or address write cycle timing requirements over recommended ranges of
supply voltage and operating free-air temperature
PARAMETERFIGUREMINMAXUNITS
t
h6
t
d28
t
d29
t
d30
t
d31
t
d32
t
d33
t
d34
t
d35
t
d36
t
d37
t
d38
t
d39
Hold time, BUSY↓ to PD invalid2160140ns
Delay time, IOW↓ to PD valid211030ns
Delay time, BUSY↓ to STROBE↑2160100ns
Delay time, STROBE↓ to AUTOFD↓21010ns
Delay time, BUSY↑ to AUTOFD↑2160100ns
Timeout, IOW↓ to BUSY↑211012µs
Delay time, SELECTIN↑ to BUSY↓21200ns
Delay time, IOW↓ to IOCHRDY↓21025ns
Delay time, BUSY↑ to IOCHRDY↑2160120ns
Delay time,
Delay time, IOW↓ to STROBE↓21040ns
Delay time, IOW↑ to IOW or IOR↓2160ns
Delay time, BUSY↓ to STROBE↓212040ns
IOCHRDY
↑ to IOW↑2130ns
parallel-port EPP data or adress read cycle timing requirements over recommended ranges of
supply voltage and operating free-air temperature
PARAMETERFIGUREMINMAXUNITS
t
h7
t
h8
t
d40
t
d41
t
d42
t
d43
t
d44
t
d45
t
d46
t
d47
Hold time, AUTOFD, SELECTIN↑ to PD hi-Z2210ns
Hold time, IOR↑ to D hi-Z (Hold Time)22020ns
Delay time, BUSY↑ to AUTOFD, SELECTIN↑22120200ns
Delay time, AUTOFD, SELECTIN↓ to PD Valid22110ns
Delay time, IOR↓ to IOCHRDY↓22025ns
Delay time, BUSY↑ to IOCHRDY↑2280130ns
Delay time, PD valid to D valid22025ns
Timeout, IOR↓to BUSY↑221012µs
Delay time, IOR↑ to IOW or IOR↓2260ns
Delay time, IOCHRDY↑ to IOR↑2230ns
parallel-port FIFO timing requirements over recommended ranges of supply voltage and operating
free-air temperature
PARAMETERFIGUREMINMAXUNITS
t
su3
t
h9
t
w5
t
d48
t
d49
Setup time, PD valid to STROBE↓23550ns
Hold time, PD hold from STROBE↑23500ns
Pulse duration, STROBE pulse width low23500ns
Delay time, STROBE↓ to BUSY↑ active23125ns
Delay time, BUSY↓ to STROBE↓23600ns
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
parallel-port (ECP) reverse timing requirements over recommended ranges of supply voltage and
operating free-air temperature
PARAMETERFIGUREMINMAXUNITS
t
su4
t
d50
t
d51
t
d52
t
d53
t
d54
parallel-port (ECP) forward timing requirements over recommended ranges of supply voltage and
operating free-air temperature
t
su5
t
h10
t
d55
t
d56
t
d57
t
d58
t
d59
t
d60
Setup time, PD valid to ACK↓240ns
Delay time, AUTOFD↓ to PD changed240ns
Delay time, ACK↑ to AUTOFD↓2480200ns
Delay time, ACK↑ to AUTOFD↓2480120ns
Delay time, AUTOFD↓ to ACK↓2425ns
Delay time, AUTOFD↑ to ACK↑24150ns
PARAMETERFIGUREMINMAXUNITS
Setup time, PD valid to STROBE↓25090ns
Hold time, BUSY↓ to PD changed2530180ns
Delay time, AUTOFD valid to STROBE↓25045ns
Delay time, BUSY↓ to AUTOFD changed2525180ns
Delay time, STROBE↓ to BUSY↑25370ns
Delay time, STROBE↑ to BUSY↓25295ns
Delay time, BUSY↓ to STROBE↓2580120ns
Delay time, BUSY↑ to STROBE↑252060ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
A0–A2
CS0, CS1
IOW
D7–D0
A0–A2
, CS1
CS0
50%
50%50%
ValidValid
ValidValid
t
h1
t
t
d1
t
d2
50%50%
t
su1
w1
Active
Valid Data
Figure 5. Write-Cycle Timing
50%
50%
ValidValid
ValidValid
t
h2
50%
t
h3
50%
50%
IOR
D7–D0
t
h4
t
t
d3
t
d4
50%50%
t
d5
w2
Active
t
h5
Valid Data
Figure 6. Read-Cycle Timing
t
d6
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Sample Clock
TL16C450 Mode:
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
RCLK
(Internal)
8 CLKs
SINx
Sample Clock
(Internal)
INTRPTx
(data ready)
INTRPTx
(RCV error)
IOR
(read RBR)
IOR
(read LSR)
ParityStopStartData Bits 5–8
t
d7
Figure 7. Receiver Timing
50%
50%
Active
t
d8
50%
50%
t
d8
50%50%
Active
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TL16PIR552
DUAL UART WITH DUAL IrDA AND
1284 PARALLEL PORT
SLLS222A – DECEMBER 1995 – REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
SINx
Sample Clock
Trigger Level
INTRPTx
(FCR6, 7 = 0, 0)
INTRPTx
Line-Status
Interrupt (LSI)
IOR
(RD LSR)
IOR
(RD RBR)
NOTE A: For a timeout interrupt, td7 = 9 RCLKs.
Data Bits 5–8
(see Note A)
Figure 8. Receive FIFO First Byte (Sets DR Bit)
Stop
(FIFO at or above
50%
t
d7
t
d8
Active
t
50%50%
50%
50%
50%
d8
Active
trigger level)
(FIFO below
trigger level)
SINx
Sample Clock
Timeout or
Trigger Level
Interrupt
(see Note A)
Line-Status
Interrupt (LSI)
IOR
(RD LSR)
IOR
(RD RBR)
Previous Byte
Read From FIFO
NOTE A: For a timeout interrupt, td7 = 9 RCLKs.
Stop
50%
t
d7
Top Byte of FIFO
t
d7
ActiveActive
50%50%
t
d8
t
d8
50%
50%50%
50%
Figure 9. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set)
(FIFO at or above
trigger level)
(FIFO below
trigger level)
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Loading...
+ 36 hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.