Texas Instruments TL16PC564BPZ, TL16PC564BLVPZ Datasheet

TL16PC564B, TL16PC564BLV

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

Integrated Asynchronous Communications Element (ACE) Compatible With PCMCIA PC Card Standard Release 2.01

Consists of a Single TL16C550 ACE Plus PCMCIA Interface Logic

Provides Common I-Bus/Z-Bus Microcontroller Inputs for Most Intel



Zilog

Fully Programmable 256-Byte Card

Subsystems



and

Information Structure (CIS) and 8-Byte Card Configuration Register (CCR)

Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop and Parity) to or From Serial Data Stream

Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts

Subsystem Selectable Serial-Bypass Mode Provides Subsystem With Direct Parallel Access to the FIFOs

description

The TL16PC564B/BL V† is designed to provide all the functions necessary for a Personal Computer Memory Card International Association (PCMCIA) universal asynchronous receiver transmitter (UART) subsystem interface. This interface provides a serial-to-parallel conversion for data to and from a modem coder-decoder/digital signal processor (CODEC/DSP) function to a PCMCIA parallel data-port format. A computer central processing unit (CPU), through a PCMCIA host controller, can read the status of the asynchronous communications element (ACE) interface at any point in the operation. Reported status information includes the type of transfer operation in process, the status of the operation, and any error conditions encountered.

Attribute memory consists of a 256-byte card information structure (CIS) and eight 8-byte card configuration registers (CCR). The CIS, implemented with a dual-port random-access memory (DPRAM), is available to both the host CPU and subsystem (modem), as are the CCRs. This DPRAM is used in place of the electrically erasable programmable read-only memory (EEPROM) normally used for the CIS. At power up, attribute memory is initialized by the subsystem.

The TL16PC564B/BLV uses a TL16C550 ACE-type core with an expanded 64 × 11 receiver first-in-first-out (FIFO) memory and a 64 × 8 transmitter FIFO memory . The receiver trigger logic flags have been adjusted in order to take full advantage of the increased capacity when in the extended mode. In addition, eight of the UART registers have been mapped into the subsystem (modem) memory space as read-only registers. This allows the subsystem to read UART status information.

Fully Programmable Serial-Interface Characteristics: – 5-, 6-, 7-, or 8-Bit Characters – Even-, Odd-, or No-Parity Bit Generation

and Detection – 1-, 1 1/2-, or 2-Stop Bit Generation – Baud-Rate Generation

Fully Prioritized Interrupt System Controls

Modem Control Functions

Provides TL16C450 Mode at Reset Plus Selectable Normal TL16C550 Operation or Extended 64-Byte FIFO Mode

Selectable Auto-RTS Mode Deactivates RTS

at 14 Bytes in 550 Mode and at

56 Bytes in Extended 550 Mode

Selectable Auto-CTS Mode Deactivates Serial Transfers When CTS

Available in 100 Pin Thin Quad Flatpack

is Inactive

(PZ) Package

A subsystem-selectable serial-bypass mode has been implemented to allow the subsystem to bypass the serial portion of the UART and write directly to the receiver FIFO and read directly from the transmitter FIFO. Interrupt operation is not affected in this mode.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a registered trademark of Intel System, Inc. Zilog is a registered trademark of Zilog Incorporated

†

Patent pending

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

PZ PACKAGE

(TOP VIEW)

EXTEND

VTEST

SSAB

GND

ARBCLKI

GND

ARBCLKO ARBPGM0 ARBPGM1

RST

NANDOUT

GND SAD7 SAD6

GND SAD5 SAD4 SAD3 SAD2

SAD1

SA8

SAD0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

HD3

100

HD4

HD5

HD6

HD7

CE1OEHA9

GND

HA8

IREQ

HA7

HA6

HA5

HA4

HA3

HA2

GND

HA1

HA0

HD0

HD1

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

HD2 STSCHG REG

INPACK TESTOUT GND GND RESET GND SA7 IOWR IORD CE2 SA6

SA5 SA4 SA3 SA2 SA1 GND SA0

UARTCLK

†

IRQ

ALE (AS)

†

The terminal names not enclosed in parentheses correspond to an Intel microcontroller signal, and the terminal names enclosed in parentheses correspond to a Zilog microcontroller signal.

†

SELZ/I

RD(DS)

†

GND

WR(R/W)

SIN

DTR

RTS

OUT1

GND

RCLK

XIN

GND

OUT2

DSR

SOUT

CTS

DCD

BAUDOUT

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block diagram

TL16PC564B, TL16PC564BLV

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

HD7–HD0

HA9–HA0

REG

CE1 CE2

IORD

ARBCLKI

ARBPGM1–

ARBPGM0

SAD7–SAD0

SA8–SA0

SELZ/I

SSAB

ALE(AS

(R/W)

(DS)

RESET

95, 96, 98–100, 75–77

†

92, 90, 87, 85–81, 79, 78

†

73 94 62

89 93 63

5 9,8

†

14, 15, 17–20, 23, 25

†

24,65,61, 59–55,53

28 3 26

)

31 29 32

Host CPU

Control

Logic

Reset

Control

Subsystem

Control

Logic

Reset

Validation

DATA ADDR

OE WE Reset

Attribute

Memory

(CIS 256 × 8,

CCR 8 × 8

plus arbitration

logic)

DATA

ADDR OE WE

71 74 27 88 51 11

ARBCLKO

INPACK STSCHG IRQ IREQ UARTCLK RST

IOWR

XIN

SIN

RCLK

CTS DCD DSR

33 40

49 48

46 50

EXTEND

†

Bit 0 is the least significant bit.

Divide by N

Reset

UART

TL16C550C

UART Select

Master Clock

Reset

38 34 37 44 35 45

BAUDOUT DTR OUT1 OUT2 RTS SOUT

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TL16PC564B, TL16PC564BLV

INTER

I/O

DESCRIPTION

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

Terminal Functions

TERMINAL

NAME NO.

ALE (AS) 26 S I Address-latch enable/address strobe. ALE(AS) is an address-latch enable in the Intel mode

ARBCLKO 7 M O Arbitration clock output. ARBCLKO is equal to the input on ARBCLKI divided by the

ARBCLKI 5 M I Arbitration clock input. ARBCLKI is the base clock used in arbitration for the attribute memory

ARBPGM0 ARBPGM1

BAUDOUT 38 U O Baud output. BAUDOUT is an active-low 16× signal for the transmitter section of the UART.

CE1 CE2

CS 32 S I Chip select. CS is the active-low chip select from the Zilog or Intel microcontroller. CTS 49 U I Clear to send. CTS is an active-low modem status signal whose condition can be checked by

DCD 48 U I Data carrier detect. DCD is an active-low modem-status signal whose condition can be

DSR 46 U I Data set ready. DSR is an active-low modem status signal whose condition can be checked

DTR 34 U O Data terminal ready. DSD is an active-low signal. When active, DTR informs the modem or

EXTEND 1 U I FIFO extend. When EXTEND is high, the UART is configured as a standard TL16C550 with

GND 4,6,13,16,30,

†

Host = H, Subsystem = S, UART = U, Miscellaneous = M

8 9

94 62

39,41,43,54,

66,68,69,80,91

INTER-

†

FACE

and an address strobe in the Zilog mode. ALE (AS active low for a Zilog subsystem.

binary-coded divisor input on ARBPGM (1–0).

DRAM and the reset validation circuitry.

M I Arbitration clock divisor program. These two bits set the divisor for ARBCLKI. Divide by 1, 2,

H I Card enable 1 and card enable 2 are active-low signals. CE1 enables even-numbered

M Common ground

4, and 8 are available.

The clock rate is established by the reference clock (UARTCLK) frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT section by tying this output to the RCLK input.

address bytes, and CE2 on HA0, CE1 These signals have internal pullup resistors.

reading bit 4 (CTS) of the modem status register (MSR). Bit 0 (delta clear to send) of the MSR indicates that the signal has changed states since the last read from the MSR. If the modem-status interrupt is enabled when CTS

checked by reading bit 7 (DCD) of the MSR. Bit 3 (delta data carrier detect) of the MSR indicates that the signal has changed states since the last read from the MSR. If the modem-status interrupt is enabled when DCD

by reading bit 5 (DSR) of the MSR. Bit 1 (delta data set ready) of the MSR indicates that the signal has changed states since the last read from the MSR. If the modem-status interrupt is enabled when DSR

data set that the UART is ready to establish communication. DTR by setting the DTR bit 0 of the modem control register (MCR) to a high level. DTR in the inactive state either as a result of a reset, doing a loop-mode operation, or resetting bit 0 (DTR) of the MCR.

16-byte transmit and receive FIFOs. When EXTEND bit 5 is high, the FIFOs are extended to 64 bytes and the receiver-interrupt trigger levels adjust accordingly. EXTEND enables the auto-RTS

, and CE2 allows an 8-bit host to access all data on HD0 through HD7 if desired.

enables odd-numbered address bytes. A multiplexing scheme based

changes states, an interrupt is generated.

low in conjunction with FIFO control register (FCR) bit 4 set high function.

) is active high for an Intel subsystem and

may also be used for the receiver

changes states, an interrupt is generated.

is placed in the active state

is placed

is low and FIFO control register (FCR)

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INTER

I/O

DESCRIPTION

TL16PC564B, TL16PC564BLV

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

Terminal Functions

TERMINAL

NAME NO.

HA0 HA1 HA2 HA3 HA4 HA5 HA6 HA7 HA8 HA9

HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7

INPACK 71 H O Input port acknowledge. INPACK is an active-low output signal that is asserted when the card

IORD 63 H I I/O read strobe. IORD is an active-low input signal activated to read data from the card I/O space.

IOWR 64 H I I/O write strobe. IORW is an active-low input signal activated to write data to the card I/O space.

IREQ 88 H O Interrupt request. IREQ is an active-low output signal asserted by the card to indicate to the host

IRQ 27 S O Interrupt request. This active-high IRQ to the subsystem indicates a host CPU write to attribute

NANDOUT 12 M O This is a production test output. OE 93 H I Output enable. OE is an active-low input signal used to gate memory read data from the card. This

OUT1 OUT2

RCLK 40 U I Receiver clock. RCLK is the 16×-baud-rate clock input for the receiver section of the UART. RD(DS) 29 S I Read enable or data strobe input. RD(DS) is the active-low read enable in the Intel mode and the

REG 73 H I Attribute memory select. This active-low input signal is generated by the host CPU and accesses

RESET 67 H I Reset. RESET is an active-high input that serves as the master reset for the device. RESET clears

RI 50 U I Ring indicator. RI is an active-low modem status signal whose condition can be checked by reading

†

Host = H, Subsystem = S, UART = U, Miscellaneous = M

78 79 81 82 83 84 85 87 90 92

77 76 75

100

99 98 96 95

37 44

INTER-

†

FACE

H I The 10-bit address bus addresses the attribute memory (bits 1 –8) and addresses the internal

H I/O The 8-bit bidirectional data bus transfers data to and from the attribute memory and the internal

U O Output 1 and output 2 are active-low signals. OUT1 and OUT2 are user-defined output terminals

UART as either PCMCIA I/O (bits 0–2) or as a standard COM port (bits 0–9).

UART.

responds to an I/O read cycle at the address on the HA bus.

The REG I/O transfer to take place. This signal has an internal pullup resistor.

CPU that a card device requires host software service. This signal doubles as READY/BUSY during power-up initialization.

memory has occurred.

signal has an internal pullup resistor.

that are set to their active state by setting respective MCR bits (OUT1 and OUT2) high. OUT1 OUT2 resetting bit 2 (OUT1) or bit 3 (OUT2) of the MCR. This signal has an open-drain outputs.

active-low data strobe in the Zilog mode.

attribute memory (OE memory access is excluded. This signal has an internal pullup resistor and hysteresis on the input buffer .

the UART, placing the card in an unconfigured state. This signal has an internal pullup resistor.

bit 6 (RI) of the MSR. The trailing-edge ring indicator (TERI) bit 2 of the MSR indicates that RI transitioned from a low to a high state since the last read from the MSR. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

signal and at least one of the card enable inputs (CE1, CE2) must also be active for the

are set to their inactive (high) state as a result of a reset, doing loop-mode operation, or by

and WE active) and I/O space (IORD or IOWR active). PCMCIA common

and

has

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SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

Terminal Functions

TERMINAL

RST 11 M O This is the qualified active-low reset signal. RST has a fail-safe open-drain output. RTS 35 U O Request to send is an active-low signal. When active, RTS informs the modem of the data set

SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7

SA8 24 S I Address bit 8 is bit 8 of the subsystem address bus. SAD0

SAD1 SAD2 SAD3 SAD4 SAD5 SAD6 SAD7

SELZ/I 28 S I Select Zilog or Intel mode. SELZ/I is used to select between a Zilog-like or Intel-like

SIN 33 U I Serial data input. SIN moves information from the communication line or modem to the

SOUT 45 U O Serial out. SOUT is the composite serial data output to a connected communication device.

SSAB 3 S I Separate subsystem address bus. SSAB is used to select between a multiplexed address/data

STSCHG 74 H O Status change. STSCHG is an optional active-low output signal used to alert the host that a

TESTOUT 70 M O This is a production test output. UARTCLK 51 M O UART clock. UARTCLK is a clock output whose frequency is determined by the frequency on

VTEST 2 M I VTEST is an active-high production test input with an internal pulldown resistor. It can be left

WE 89 H I Write enable. WE is an active-low input signal used for strobing attribute-memory write data into

WR(R/W) 31 S I Write or read/write enable. WR(R/W) is the active-low write enable in the Intel mode and

XIN 42 M I Crystal input. XIN is a clock input divided internally based on the PGMCLK register value, then

†

Host = H, Subsystem = S, UART = U, Miscellaneous = M

53 55 56 57 58 59 61 65

25 23 20 19 18 17 15 14

10,21,22,36,

47,52,60, 72,86,97

INTERFACE

I/O DESCRIPTION

†

that the UART is ready to receive data. RTS control register bit and is set to its inactive (high) state either as a result of a reset, doing loop-mode operation, or by resetting bit 1 (RTS) of the MCR.

S I When SSAB is high, this is the subsystem address bus and SAD (7–0) is the subsystem data

S I/O Subsystem address/data 7 – 0. This is a multiplexed bidirectional address/data bus to the

M 3.3-V or 5-V supply voltage

bus. When SSAB is low, this bus is not used and SAD(7–0) is the subsystem multiplexed address/data bus.

attribute-memory DPRAM and CCRs when SSAB is low . This becomes a bidirectional data bus when SSAB is high.

microcontroller. 1 = Zilog, 0 = Intel.

TL16PC564B UART receiver circuits. Data on the serial bus is disabled when operating in the loop mode.

SOUT is set to the marking (logic 1) state as a result of a reset.

bus subsystem interface (SSAB = 0) and a subsystem interface with separate address and data buses (SSAB = 1). This signal has an internal pulldown resistor.

subsystem write to attribute memory has occurred. This signal has an open-drain output.

XIN and the divisor value on the PGMCLK register.

open or tied to ground.

the card. This signal has an internal pullup resistor

read/write

used as the primary UART clock input.

in the Zilog mode.

is set to its active state by setting the RTS modem

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TL16PC564B, TL16PC564BLV

PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

detailed description

reset-validation circuit

A reset-validation circuit has been implemented to qualify the active-high RESET input. At power up, the level on the RST inverted state of that stable value of RESET . Any changes on RESET must be valid for eight ARBCLKI clocks before the change is reflected on RST RST

is driven by a low-noise, open-drain, fail-safe output buffer.

host CPU memory map

The host CPU attribute memory space is mapped as follows:

output is unknown. Whenever RESET is stable for at least eight ARBCLKIs, RST reflects the

. This 8-clock filter provides needed hysteresis on the master reset input.

Host CPU Address Bits 9–1 (HA0 = 0) Attribute Memory Space

0 – 255 CIS

256 CCR0 257 CCR1 258 CCR2 259 CCR3 260 CCR4 261 CCR5 262 CCR6 263 CCR7

The host CPU I/O space is mapped as follows:

Address Mode (hex)

Normal Mode COM1 COM2 COM3 COM4 I/O Space

0 (DLAB = 0) 0 (DLAB = 0) 0 (DLAB = 1) 1 (DLAB = 0) 1 (DLAB = 1)

†

3F8 2F8 3E8 2E8 UART receiver buffer register (RBR) – read only

†

3F8 2F8 3E8 2E8 UART transmitter holding register (THR) – write only

†

3F8 2F8 3E8 2E8 UART divisor latch LSB (DLL)

†

3F9 2F9 3E9 2E9 UART interrupt enable register (IER)

†

3F9 2F9 3E9 2E9 UART divisor latch MSB (DLM) 2 3FA 2FA 3EA 2EA UART interrupt identification register (IIR) – read only 2 3FA 2FA 3EA 2EA UART FIFO control register (FCR) – write only 3 3FB 2FB 3EB 2EB UART line control register (LCR) 4 3FC 2FC 3EC 2EC UART modem control register (MCR) – bit 5 read only 5 3FD 2FD 3ED 2ED UART line status register (LSR) 6 3FE 2FE 3EE 2EE UART modem status rgister (MSR) 7 3FF 2FF 3EF 2EF UART scratch register (SCR)

†

DLAB is bit 7 of the line control register (LCR).

subsystem memory map

The subsystem attribute memory space is mapped as follows:

Subsystem Address Bits 8–0 Attribute Memory Space

0 – 255 CIS

256 CCR0 257 CCR1 258 CCR2 259 CCR3 260 CCR4 261 CCR5 262 CCR6 263 CCR7

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SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

subsystem memory map (continued)

The subsystem control space is mapped as follows:

Subsystem Address Bits 8–0 Control Space

272 Control Register 288 PGMCLK Register (write only)

The subsystem UART space is mapped as follows:

Subsystem Address Bits 8–0 UART Space

304 UART MCR bit 5 (write only) 304 UART DLL (read only) 305 UART IER (read only) 306 UART FCR (read only) 307 UART LCR (read only) 308 UART MCR (read only) 309 UART LSR (read only) 310 UART MSR (read only) 311 UART DLM (read only) 320 UART transmitter FIFO (read only) 320 UART receiver FIFO (write only)

†

Only when serial bypass mode is enabled

†

host CPU/attribute-memory interface

The host CPU/attribute-memory interface is comprised of one port of the internal DPRAM, the eight CCRs, and necessary control circuitry . Signals HA0 and CE1 low when both signals have been asserted by the host CPU. This output is combined with REG address, HA(9–1), to provide the chip enable for the DPRAM and CCRs. This composite chip enable in combination with WE

subsystem/attribute-memory interface

The subsystem/attribute-memory interface is comprised of the second port of the internal DPRAM, the eight CCRs, and necessary control circuitry. When in multiplexed mode (SSAB = 0), the combination of signals SELZ /I to latch the address on SA8 and SAD(7–0). When in the Zilog mode (SELZ/I [WR (SELZ/I

When in nonmultiplexed mode (SSAB = 1), SA(7–0) become the lower-order address bits, SAD(7–0) are strictly the bidirectional data bus, and ALE(AS

and ALE(AS) allows either a positive-pulse Intel or a negative-pulse Zilog address latch-enable strobe

(R/W)], data strobe [RD(DS)], and decoded address allows ZBUS access. When in the Intel configuration

low), the combination of read [RD(DS)], write [WR(R/W)], and decoded address allows IBUS access.

SSAB SELZ/I

0 0 0 1 SA8, SAD(7–0) Intel read 0 0 1 0 SA8, SAD(7–0) Intel write 0 1 0 1 SA8, SAD(7–0) Zilog read 0 1 0 0 SA8, SAD(7–0) Zilog write 1 0 0 1 SA(8–0) Intel read 1 0 1 0 SA(8–0) Intel write 1 1 0 1 SA(8–0) Zilog read 1 1 0 0 SA(8–0) Zilog write

or OE allows writes and reads to the DPRAM and CCRs.

) is nonfunctional. All other interface signals function the same.

RD(DS)WR(R/W) Address Operation

are gated together internally so that the output of the gate is

and the decoded

high), the combination of read/write

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PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

attribute-memory arbitration

Arbitration for the attribute memory is necessary whenever there is simultaneous access to the same DPRAM or CCR address for the conditions of:

• Host CPU read and subsystem write

• Host CPU write and subsystem read

• Host CPU write and subsystem write

If arbitration were not provided, attribute-memory data would be corrupted and invalid data read due to uncontrolled access to the same DPRAM or CCR address.

The arbitration control circuitry synchronizes the asynchronous accesses of the host CPU and subsystem to the DPRAM and CCR and controls the access based on the pending host CPU and subsystem attribute-memory operation. The synchronizing and control circuitry needs a clock called the arbitration clock. The external clock (ARBCLKI) goes through a programmable divider and can be divided by one, two, four, or eight to generate a clock frequency within an allowed range for the arbitration logic to work correctly . The output of this frequency divider is named ARBCLKO. The programmable divider bits are defined as follows:

ARBPGM1 ARBPGM0

L H ARBCLKI/2 H L ARBCLKI/4 H H ARBCLKI/8

The upper period limit of ARBCLKO is N/6, where N (ns) is the shortest of the two attribute-memory accesses, host CPU or subsystem. The lower period limit of ARBCLKO is based on the DPRAM specifications at the supply voltage used:

5 V = 14-ns clock cycle (71 MHz) 3 V = 26-ns clock cycle (38.5 MHz)

For any arbitration condition, attribute-memory access is controlled to ensure valid data is read for a port that is doing a read operation and valid data is written for a port that is doing a write operation. When both the host CPU and subsystem are performing simultaneous write operations to the same address, the host CPU is allowed to write and the subsystem write is ignored.

host CPU/subsystem handshake

Two signals are provided for handshaking between the host CPU and the subsystem. The active-high IRQ signifies to the subsystem that the host CPU has written data into attribute memory . The subsystem can clear IRQ by writing a 1 to bit 6 of the subsystem control register. The active-low STSCHG that the subsystem has written data to attribute memory provided bit 2 of the subsystem control register (STSCHG control of these signals is synchronized to ARBCLKO to ensure there are no false assertions/deassertions.

enable) is high. The host CPU can clear STSCHG by reading any location in attribute memory . The

L ARBCLKI/1

INTERNAL

ARITRATION CLOCK

signifies to the host CPU

There is additional arbitration performed for instances of simultaneous assertion/deasseration of IRQ or STSCHG deasserted prior to being asserted, but the write ultimately wins arbitration. When the host CPU read occurs more than one-half an arbitration clock after the subsystem write, STSCHG a similar fashion.

. When a subsystem write and host CPU read occurs simultaneously, STSCHG may be briefly

is deasserted. IRQ is arbitrated in

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TL16PC564B, TL16PC564BLV PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER

SLLS225A – MARCH 1996 – REVISED FEBRUARY 1998

host CPU/UART interface

The UART select is derived from either host CPU address information or logic levels on CE1

, CE2 and REG. In the address mode, host CPU address bits HA9, HA7, HA6, HA5, and HA3 are combined with conditional derivatives of HA4 and HA8 to select the UART (HA4 and HA8 select COM ports 1–4 based on settings in the subsystem control register). CE1 with REG

enable the UART in the event that these signals are present. In the event that CE1 or CE2 are not

and CE2 are combined such that either of these two signals in combination

present, the UART must be accessed in the address mode previously described. The UART select in conjunction with IORD

and IOWR allows host CPU accesses to the UART. Host CPU address bits HA2–HA0

are decoded to select which UART register is to be accessed. All UART registers remain intact with the exception of the FIFO control register (FCR) and the modem-control

control RTS

operation and FIFO depth as follows:

BIT 5 BIT 4 EXTEND RTS OPERATION FIFO DEPTH

X X H Normal 16 bytes 0 0 L Normal 16 bytes 0 1 L Auto 16 bytes 1 0 L Normal 64 bytes 1 1 L Auto 64 bytes

FCR bit 5 high and EXTEND low redefine the receiver FIFO trigger levels set by FCR bits 6 and 7 as follows:

BIT 7 BIT 6 TRIGGER LEVEL

0 0 1 0 1 16 1 0 32 1 1 56

The MCR (host CPU address 4) bit 5 is read only. Bit 5 is controlled by the subsystem to enable (high) the auto-CTS

mode of operation

subsystem/UART interface

The UART provides a serial-communications channel to the subsystem with enhanced RTS auto-RTS

description). This channel is capable of operating at 115 kbps and is the main communications

control (see

channel to the subsystem (refer to the TL16C550 specification for the detailed description of the serial-communications channel).

Many of the UART registers have been mapped into the subsystems memory space as read only . In addition, MCR bit 5 (subsystem address 130 hex) is controlled by the subsystem to enable (high) auto-CTS subsystem can read the MCR at address 134 hex. When reading the FCR (subsystem address 132 hex), bits 1 and 2 are always high, and bits 4 and 5 are low only when EXTEND high (64-byte FIFOs and auto-RTS

enabled) (refer to the subsystem memory map).

is low and the host CPU has set them

. The

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