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THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

features

Simultaneous Sampling of 4 Single-Ended Signals or 2 Differential Signals or Combination of Both

Integrated 16-Word FIFO

Signal-to-Noise and Distortion Ratio: 59 dB at f

= 2 MHz

Differential Nonlinearity Error: ±1 LSB

Integral Nonlinearity Error: ±1 LSB

Auto-Scan Mode for 2, 3, or 4 Inputs

3-V or 5-V Digital Interface Compatible

Low Power: 216 mW Max

5-V Analog Single Supply Operation

Internal Voltage References . . . 50 PPM/°C and ±5% Accuracy

Parallel µC/DSP Interface

description

The THS10064 is a CMOS, low-power, 10-bit, 6 MSPS analog-to-digital converter (ADC). The speed, resolution, bandwidth, and single-supply operation are suited for applications in radar, imaging, high-speed acquisition, and communications. A multistage pipelined

applications

Radar Applications

Communications

Control Applications

High-Speed DSP Front-End

Automotive Applications

DA (TSSOP) PACKAGE

D0 D1 D2 D3 D4 D5

BGND

D6 D7 D8

D9 RA0 RA1

CONV_CLK (CONVST

DATA_AV

)

(TOP VIEW)

AINP AINM BINP BINM REFIN REFOUT REFP REFM AGND AV

CS0 CS1 WR

(R/W) RD DV

DGND

architecture with output error correction logic provides for no missing codes over the full operating temperature range. Internal control registers are used to program the ADC into the desired mode. The THS10064 consists of four analog inputs, which are sampled simultaneously . These inputs can be selected individually and configured to single-ended or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to improve data transfers to the processor. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.

An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. Two different conversion modes can be selected. In single conversion mode, a single and simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal (CONVST

). The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the THS10064. The internal clock oscillator is switched off in continuous conversion mode.

The THS10064C is characterized for operation from 0°C to 70°C, and the THS10064I is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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THS10064 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

AVAILABLE OPTIONS

0°C to 70°C THS10064CDA

–40°C to 85°C THS10064IDA

functional block diagram

PACKAGED DEVICE

TSSOP

(DA)

REFP

REFM

REFIN

AINP

AINM

BINP

BINM

CONV_CLK (CONVST

CS0 CS1

WR (R/W)

3.5 V

1.5 V

ADC

Control

REFM

S/H

REFP

S/H

)

Logic

and

Control

Single Ended and/or

Differential

MUX

–

10 Bit

Pipeline

FIFO

16 × 10

1.225 V

REF

Buffers

2.5 V

REFOUT

DATA_AV

D0 D1

D2 D3 D4 D5

D6 D7 D8 D9 RA0 RA1

BGND

AGND DGND

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I/O

DESCRIPTION

THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

Terminal Functions

TERMINAL

NAME NO.

AINP 32 I Analog input, single-ended or positive input of differential channel A AINM 31 I Analog input, single-ended or negative input of differential channel A BINP 30 I Analog input, single-ended or positive input of differential channel B BINM 29 I Analog input, single-ended or negative input of differential channel B AV

AGND 24 I Analog ground BV

BGND 8 I Digital ground for buffer CONV_CLK (CONVST) 15 I Digital input. This input is used to apply an external conversion clock in continuous conversion

CS0 22 I Chip select input (active low) CS1 21 I Chip select input (active high) DATA_AV 16 O Data available signal, which can be used to generate an interrupt for processors and as a level

DGND 17 I Digital ground. Ground reference for digital circuitry. DV

D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB RA0 13 I Digital input. RA0 is used as an address line for the control register . This is required for writing

RA1 14 I Digital input. RA1 is used as an address line for the control register . This is required for writing

REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin

REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal

REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal

REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The

†

WR (R/W)

†

The start-conditions of RD

†

23 I Analog supply voltage

7 I Digital supply voltage for buffer

mode. In single conversion mode, this input functions as the conversion start (CONVST A high to low transition on this input holds simultaneously the selected analog input channels and initiates a single conversion of all selected analog inputs.

information of the internal FIFO. This signal can be configured to be active low or high and can be configured as a static level or pulse output. See Table 14.

18 I Digital supply voltage

to the control register 0 and control register 1. See Table 8.

to control register 0 and control register 1. See Table 8.

be connected to the reference output REFOUT.

reference voltage. An external reference voltage at this input can be applied. This option can be programmed through control register 0. See Table 9.

reference output requires a capacitor of 10 µF to AGND for filtering and stability .

19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a

20 I This input is programmable. It functions as a read-write input R/W and can also be configured

and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.

digital input, active low as a data read select from the processor. See timing section.

as a write-only input WR In this case, the RD

, which is active low and used as data write select from the processor.

input is used as a read input from the processor. See timing section.

) input.

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THS10064

High-level input voltage, V

Low-level input voltage, V

Operating free-air temperature, T

°C

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, DGND to DVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BGND to BVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to AV

–0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range AGND – 0.3 V to AVDD + 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage –0.3 + AGND to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range,T

THS10064C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

THS10064I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supply

MIN NOM MAX UNIT

Supply voltage

AV DV BV

DD DD DD

4.75 5 5.25 3 3.3 5.25 3 3.3 5.25

analog and reference inputs

MIN NOM MAX UNIT

Analog input voltage in single-ended configuration V Common-mode input voltage VCM in differential configuration 1 2.5 4 V External reference voltage,V External reference voltage, V Input voltage difference, REFP – REFM 2 V

(optional) 3.5 AVDD–1.2 V

REFP

(optional) 1.4 1.5 V

REFM

REFP

digital inputs

MIN NOM MAX UNIT

Input CONV_CLK frequency DVDD = 3 V to 5.25 V 0.1 6 MHz CONV_CLK pulse duration, clock high, t

CONV_CLK pulse duration, clock low, t

w(CONV_CLKH)

w(CONV_CLKL)

BVDD = 3.3 V 2 V BVDD = 5.25 V 2.6 V BVDD = 3.3 V 0.6 V BVDD = 5.25 V 0.6 V

DVDD = 3 V to 5.25 V 80 83 5000 ns DVDD = 3 V to 5.25 V 80 83 5000 ns THS10064CDA 0 70 THS10064IDA –40 85

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THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

electrical characteristics over recommended operating conditions, DVDD = 3.3 V , A VDD = 5 V , V = internal (unless otherwise noted)

digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Digital inputs

I I C

Digital outputs

V V I C C

High-level input current DVDD = digital inputs –50 50 µA

Low-level input current Digital input = 0 V –50 50 µA

Input capacitance 5 pF

High-level output voltage I

Low-level output voltage I

High-impedance-state output current CS1 = DGND, CS0 = DV

Output capacitance 5 pF

Load capacitance at databus D0 – D11 30 pF

= –50 µA, BVDD = 3.3 V, 5 V BVDD–0.5 V

= 50 µA, BVDD = 3.3 V, 5 V 0.4 V

–10 10 µA

REF

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THS10064

Offset error

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

electrical characteristics over recommended operating conditions, AVDD = 5 V, DV

= BVDD = 3.3 V, fs = 6 MSPS, V

dc specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 Bits

Accuracy

Integral nonlinearity, INL ±1 LSB Differential nonlinearity , DNL ±1 LSB

Gain error 1% FSR

Analog input

Input capacitance 15 pF Input leakage current V

Internal voltage reference

Accuracy, V Accuracy, V Temperature coefficient 50 PPM/°C Reference noise 100 µV Accuracy, REFOUT 2.475 2.5 2.525 V

Power supply

DDA

DDD

DDB

DD_P

Analog supply current AVDD =5 V, BVDD = DVDD = 3.3 V 36 40 mA Digital supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 0.5 1 mA Buffer supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 1.5 4 mA Supply current in power-down mode AVDD = 5 V, BVDD = DVDD = 3.3 V 7 mA Power dissipation AVDD = 5 V, DVDD = BVDD = 3.3 V 186 216 mW Power dissipation in power down AVDD = 5 V, DVDD = BVDD = 3.3 V 30 mW

REFP REFM

= internal (unless otherwise noted) (continued)

REF

After calibration in single-ended mode –15 15 mV After calibration in differential mode –5 5 mV

AIN

= V

REFM

to V

REFP

3.33 3.5 3.67 V

1.42 1.5 1.58 V

±10 µA

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THD

T otal harmonic distortion

ENOB SFDR

Spurious free dynamic range

THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

electrical characteristics over recommended operating conditions, V f

= 2 MHz at –1dBFS (unless otherwise noted) (continued)

= internal, fs = 6 MHz,

REF

ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Differential mode 56 59 dB

SINAD Signal-to-noise ratio + distortion

SNR Signal-to-noise ratio

(SNR)

Analog Input

NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the

Effective number of bits

Full-power bandwidth with a source impedance of 150 Ω in differential configuration.

Full-power bandwidth with a source impedance of 150 Ω in single-ended configuration.

Small-signal bandwidth with a source impedance of 150 Ω in differential configuration.

Small-signal bandwidth with a source impedance of 150 Ω in single-ended configuration.

sampling clock.

Single-ended mode (see Note 1)

Differential mode 59 61 dB Single-ended mode

(see Note 1) Differential mode –67 –61 dB Single-ended mode –67 dB Differential mode 9 9.6 Bits Single-ended mode

(see Note 1) Differential mode 61 68 dB Single-ended mode 68 dB

Full scale sinewave, –3 dB 96 MHz

Full scale sinewave, –3 dB 54 MHz

100 mVpp sinewave, –3 dB 96 MHz

100 mVpp sinewave, –3 dB 54 MHz

59 dB

60 dB

9.5 Bits

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THS10064

t2Time between consecutive start of single conversion

y, _ gg

(

)

level condition: TRIG0 = 1, TRIG1 = 1

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

timing specifications, AV

d(DATA_AV)

d(o)

pipe

Delay time 5 ns Delay time 5 ns

Latency 5

= 5 V, BVDD = DVDD = 3.3 V, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

timing specification of the single conversion mode

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(DATA_AV)

†

Timing parameters are ensured by design but are not tested.

Clock cycle of the internal clock oscillator 159 167 175 ns Pulse width, CONVST 1.5×t Aperture time 1 ns

Delay time, DATA_AV becomes active for the trigger level condition: TRIG0 = 0, TRIG1 = 0

Delay time, DATA_AV becomes active for the trigger level condition: TRIG0 = 1, TRIG1 = 0

Delay time, DATA_AV becomes active for the trigger level condition: TRIG0 = 0, TRIG1 = 1

Delay time, DATA_AV becomes active for the trigger

= internal, CL < 30 pF

REF

†

1 analog input 2×t 2 analog inputs 3×t 3 analog inputs 4×t 4 analog inputs 5×t 1 analog input, TL = 1 6×t 2 analog inputs, TL = 2 7×t 3 analog inputs, TL = 3 8×t 4 analog inputs, TL = 4 9×t 1 analog input, TL = 4 3×t2 +6×t 2 analog inputs, TL = 4 t2 +7×t 3 analog inputs, TL = 6 t2 +8×t 4 analog inputs, TL = 8 t2 +9×t 1 analog input, TL = 8 7×t2 +6×t 2 analog inputs, TL = 8 3×t2 +7×t 3 analog inputs, TL = 9 2×t2 +8×t 4 analog inputs, TL = 12 2×t2 +9×t 1 analog input, TL = 14 13×t2 +6×t 2 analog inputs, TL = 12 5×t2 +7×t 3 analog inputs, TL = 12 3×t2 +8×t

c c c c

c c c c c c c c c c c c c c c

CONV

CLK

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10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

detailed description

reference voltage

The THS10064 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to

3.5 V and VREFM is set to 1.5 V . An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.

analog inputs

The THS10064 consists of 4 analog inputs, which are sampled simultaneously . These inputs can be selected individually and configured as single-ended or differential inputs. The desired analog input channel can be programmed.

analog-to-digital converter

The THS10064 uses a 10-bit pipelined multistaged architecture with 4 1-bit stages followed by 4 2-bit stages, which achieves a high sample rate with low power consumption. The THS10064 distributes the conversion over several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while the second through the eighth stages operate on the seven preceding samples.

THS10064

conversion modes

The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling edge of the applied clock signal.

sampling rate

The maximum possible conversion rate per channel is dependent on the selected analog input channels. T able 1 shows the maximum conversion rate in the continuous conversion mode for different combinations.

Table 1. Maximum Conversion Rate in Continuous Conversion Mode

CHANNEL CONFIGURATION

1 single-ended channel 1 6 MSPS 2 single-ended channels 2 3 MSPS 3 single-ended channels 3 2 MSPS 4 single-ended channels 4 1.5 MSPS 1 differential channel 1 6 MSPS 2 differential channels 2 3 MSPS 1 single-ended and 1 differential channel 2 3 MSPS 2 single-ended and 1 differential channels 3 2 MSPS

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:

6 MSPS

# channels

Table 2 shows the maximum conversion rate in the single conversion mode.

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THS10064 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

sampling rate (continued)

Table 2. Maximum Conversion Rate in Single Conversion Mode

CHANNEL CONFIGURATION

1 single-ended channel 1 3 MSPS 2 single-ended channels 2 2 MSPS 3 single-ended channels 3 1.5 MSPS 4 single-ended channels 4 1.2 MSPS 1 differential channel 1 3 MSPS 2 differential channels 2 2 MSPS 1 single-ended and 1 differential channel 2 1.5 MSPS 2 single-ended and 1 differential channels 3 1.2 MSPS

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

single conversion mode

In single conversion mode, a single conversion of the selected analog input channels is performed. The single conversion mode is selected by setting bit 1 of control register 0 to 1.

A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started.

The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode can be selected according to Table 13.

Figure 1 shows the timing of the single conversion mode. In this mode, up to four analog input channels can be selected to be sampled simultaneously (see Table 2).

CONVST

AIN

Sample N

DATA_AV,

Trigger Level = 1

d(A)

DATA_AV

Figure 1. Timing of Single Conversion Mode

The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog input channels. The time t

DA TA_AV

, until DA TA_AV becomes active is given by: t

DA TA_AV

= t

pipe

+ n × tc. This equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all other trigger level conditions refer to the timing specifications of single conversion mode.

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10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

continuous conversion mode

The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO. The first conversion value is written into the FIFO with a latency of 8 + TL (trigger level) clock cycles after the FIFO reset.

Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The maximum throughput rate is 6 MSPS in this mode. The timing of the DA T A_A V signal is shown here in the case of a trigger level set to 1 or 4.

AIN

w(CONV_CLKH)

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 1

DATA_AV,

Trigger Level = 4

Sample N Channel 1

Sample N+1

Channel 1

d(A)

50% 50%

Data N–5

Channel 1

Sample N+2

Channel 1

d(pipe)

w(CONV_CLKL)

Data N–4

Channel 1

Sample N+3

Data N–3

Channel 1

Sample N+4

Channel 1

Data N–2

Channel 1

d(O)

Data N–1

Channel 1

Sample N+5

Channel 1

Data N

Sample N+6

Channel 1

Data N+1

Channel 1

Sample N+7

Channel 1

Data N+2

Channel 1

d(DATA_AV)

Sample N+8

Channel 1

Data N+3 Channel 1

d(DATA_AV)

THS10064

Figure 2. Timing of Continuous Conversion Mode (1-channel operation)

Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data is written into the FIFO. The timing of the DA TA_A V signal shown here is for a trigger level set to 2 or 4.

AIN

w(CONV_CLKH)

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 2

DATA_AV,

Trigger Level = 4

Sample N

Channel 1,2

d(A)

50% 50%

Data N–3

Channel 2

Sample N+1

Channel 1,2

d(Pipe)

w(CONV_CLKL)

Data N–2

Channel 1

Data N–2

Channel 2

Sample N+2 Channel 1,2

Data N–1

Channel 1

d(O)

Data N–1

Channel 2

Sample N+3 Channel 1,2

Data N

Channel 1

Data N

Channel 2

Sample N+4 Channel 1,2

Data N+1

Channel 1

Data N+1

Channel 2

d(DATA_AV)

Figure 3. Timing of Continuous Conversion Mode (2-channel operation)

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THS10064 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

continuous conversion mode (continued)

Figure 4 shows the timing of continuous conversion mode when three analog input channels are selected. The maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DA TA_AV signal shown here is for a trigger level set to 3.

AIN

w(CONV_CLKH)

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 3

Sample N

Channel 1,2,3

d(A)

50% 50%

Data N–2 Channel 2

d(Pipe)

w(CONV_CLKL)

Data N–2

Channel 3

Sample N+1

Channel 1,2,3

Data N–1

Channel 1

Data N–1

Channel 2

d(O)

Data N–1

Channel 3

Channel 1,2,3

Data N

Channel 1

Sample N+2

Channel 2

Data N

d(DATA_AV)

Data N

Channel 3

Figure 4. Timing of Continuous Conversion Mode (3-channel operation)

Figure 5 shows the timing of continuous conversion mode when four analog input channels are selected. The maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DA TA_AV signal shown here is for a trigger level of 4.

AIN

w(CONV_CLKH)

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 4

Sample N

Channel 1,2,3,4

d(A)

50% 50%

Data N–2

Channel 4

d(Pipe)

w(CONV_CLKL)

Data N–1

Channel 1

Data N–1 Channel 2

Sample N+1

Channel 1,2,3,4

Data N–1

Channel 3

d(O)

Data N–1

Channel 4

Data N

Channel 1

Data N

Channel 2

Sample N+2

Channel 1,2,3,4

Data N

Channel 3

d(DATA_AV)

Data N

Channel 4

Figure 5. Timing of Continuous Conversion Mode (4-channel operation)

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10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

digital output data format

The digital output data format of the THS10064 can either be in binary format or in two’s complement format. The following tables list the digital outputs for the analog input voltages.

Table 3. Binary Output Format for Single-Ended Configuration

SINGLE-ENDED, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

AIN = V

REFP

AIN = (V AIN = V

REFP

REFM

+ V

)/2 200h

REFM

Table 4. Two’s Complement Output Format for Single-Ended Configuration

SINGLE-ENDED, TWOS COMPLEMENT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

AIN = V

REFP

AIN = (V AIN = V

REFP

REFM

+ V

)/2 000h

REFM

3FFh

000h

1FFh

200h

THS10064

Table 5. Binary Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

Vin = AINP – AINM

= V

REF

Vin = V

REF

Vin = 0 200h Vin = –V

REF

REFP

– V

REFM

3FFh

000h

Table 6. Two’s Complement Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

Vin = AINP – AINM

= V

REF

Vin = V

REF

Vin = 0 000h Vin = –V

REF

REFP

– V

REFM

1FFh

200h

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FIFO description

In order to facilitate an efficient connection to today’s processors, the THS10064 is supplied with a FIFO. This integrated FIFO enables a problem-free processing of data with today’s processors. The FIFO is provided as a flexible circular buffer . The circular buf fer integrated in the THS10064 can store up to 16 conversion values. Therefore, the amount of interrupts to be served by a processor can be reduced significantly.

Read Pointer

Trigger Pointer

Write Pointer

Data in FIFO Free

Figure 6. Circular Buffer

The converted data of the THS10064 is automatically written into the FIFO. To control the writing and reading process, a write pointer, a read pointer and a trigger pointer are used. The read pointer always shows the location which will be read next. The write pointer indicates the location which contains the last written sample. With a selection of multiple analog input channels, the converted values are written in a predefined sequence to the circular buffer (autoscan mode). In this way, the channel information for the reading processor is continually maintained.

The FIFO can be programmed through the control register of the ADC. The user has the ability to select a specific trigger level according to Table 13 in order to choose the configuration which best fits the application. The FIFO provides the signal DATA_AV, which signals the processor to read the amount of data equal to the trigger level selected in Table 13. The signal DAT A_AV becomes active when the trigger condition is satisfied. The trigger condition is satisfied when as many values as selected for the trigger level where written into the FIFO.

The signal DA T A_AV could be connected to an interrupt input of a processor. In every interrupt service routine call, the processor must read the amount of data equal to the trigger level from the ADC. The first data represents the first channel according to the autoscan mode, which is shown in Table 10. The channel information is therefore always maintained.

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Reading data from the FIFO

The THS10064 informs the connected processor via the digital output DATA_AV (data available) that a block of conversion values are ready to be read. The block size to be read is always equal to the setting of the trigger level. The selectable trigger levels depend on the number of selected analog input channels. For example, when choosing one analog input, a trigger level of 1, 4, 8, and 14 can be selected. The following figures demonstrate the principle of reading the data (the READ

In Figure 7, a trigger level of 1 is selected. The control signal DA TA_AV is set to an active low pulse. This means that the connected processor has the task to read 1 value from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 7. Trigger Level 1 Selected

In Figure 8, a trigger level of 4 is selected. The control signal DA TA_AV is set to an active low pulse. This means that the connected processor has the task to read 4 values from the ADC after every DATA_AV low pulse.

signal is asynchronous to CONV_CLK).

THS10064

CONV_CLK

DATA_AV

READ

Figure 8. Trigger Level 4 Selected

In Figure 9, a trigger level of 8 is selected. The control signal DA TA_AV is set to an active low pulse. This means that the connected processor has the task to read 8 values from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 9. Trigger Level 8 Selected

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In Figure 10, a trigger level of 14 is selected. The control signal DATA_AV is set to an active low pulse. This means that the connected processor has the task to read 14 values from the ADC after every DATA_AV low pulse.

CONV_CLK

DATA_AV

READ

Figure 10. Trigger Level 14 Selected

READ is always the logical combination of CS0

, CS1 and RD.

ADC Control Register

The THS10064 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 7.

Table 7. Bit Definitions of Control Register CR0 and CR1

BIT BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

CR0 DIFF0 CHSEL1 CHSEL0 PD MODE VREF CR1 DATA_P DATA_T TRIG1 TRIG0 OVFL/FRST RESET

BIT BIT 9 BIT 8 BIT 7 BIT 6

CR0 TEST1 TEST0 SCAN DIFF1 CR1 RESERVED OFFSET BIN/2’s R/W

Writing to control register 0 and control register 1

The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control register and writing the register value to the ADC. The addressing is performed with the upper bits RA0 and RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 8 shows the addressing of each control register.

Table 8. Control Register Addressing

D0 – D9 RA0 RA1 Addressed Control Register

Desired register value 0 0 Control register 0 Desired register value 1 0 Control register 1 Desired register value 0 1 Reserved for future Desired register value 1 1 Reserved for future

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initialization of the THS10064

The initialization of the THS10064 should be done according to the configuration flow shown in Figure 11.

Start

THS10064

Use Default

Values?

Yes

Write 0x401 to

THS10064

(Set Reset Bit in CR1)

Write 0x401 to

THS10064

(Set Reset Bit in

CR1)

Clear RESET By Writing 0x400 to

CR1

Write The User

Configuration to

CR0

Write The User

Configuration to

CR1 (Can Include

FIFO Reset, Must

Exclude RESET)

Continue

Figure 11. THS10064 Configuration Flow

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ADC control registers

control register 0 (see Table 8)

– – BIT 9 BIT 8 BIT 7 BIT 6

– – TEST1 TEST0 SCAN DIFF1

BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DIFF0 CHSEL1 CHSEL0 PD MODE VREF

Table 9. Control Register 0 Bit Functions

BITS

RESET VALUE

0 0 VREF Vref select:

1 0 MODE Continuous conversion mode/single conversion mode

2 0 PD Power down.

3, 4 0,0 CHSEL0,

5,6 1,0 DIFF0, DIFF1 Number of differential channels

7 0 SCAN Autoscan enable

8,9 0,0 TEST0,

NAME FUNCTION

Bit 0 = 0 → The internal reference is selected Bit 0 = 1 → The external reference voltage is selected

Bit 1 = 0 → Continuous conversion mode is selected An external clock signal is applied to the CONV_CLK input in this mode. With every falling edge of the

CONV_CLK signal a new converted value is written into the FIFO. Bit 1 = 1 → Single conversion mode is selected In this mode, the CONV_CLK input functions as a CONVST

CHSEL1

TEST1

THS10064 by pulsing the CONVST the selected analog inputs are placed into hold simultaneously, and the conversion sequence for the selected channels is started. The signal DATA_AV (data available) becomes active when the trigger condition is satisfied.

Bit 2 = 0 → The ADC is active Bit 2 = 1 → Power down

The reading and writing to and from the digital outputs is possible during power down. It is also possible to read out the FIFO.

Channel select Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 10.

Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to T able 10.

Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 10. Test input enable

Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This feedback allows the check of all hardware connections and the ADC operation.

Refer to Table 1 1 for selection of the three different test voltages.

input. On the falling edge of CONVST , the sample and hold stages of

input. A single conversion is initiated on the

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analog input channel selection

The analog input channels of the THS10064 can be selected via bits 3 to 7 of control register 0. One single channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 10 shows the possible selections.

Table 10. Analog Input Channel Configurations

THS10064

BIT 7

SCAN

BIT 6

DIFF1

0 0 0 0 0 Analog input AINP (single ended) 0 0 0 0 1 Analog input AINM (single ended) 0 0 0 1 0 Analog input BINP (single ended) 0 0 0 1 1 Analog input BINM (single ended) 0 0 1 0 0 Differential channel (AINP–AINM) 0 0 1 0 1 Differential channel (BINP–BINM) 1 0 0 0 1 Autoscan two single ended channels: AINP, AINM, AINP, … 1 0 0 1 0 Autoscan three single ended channels: AINP, AINM, BINP, AINP, … 1 0 0 1 1 Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, …

1 0 1 0 1

1 0 1 1 0

1 1 0 0 1 0 0 1 1 0 Reserved

0 0 1 1 1 Reserved 1 0 0 0 0 Reserved 1 0 1 0 0 Reserved 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1 1 0 1 0 Reserved 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 Reserved 1 1 1 1 1 Reserved

BIT 5

DIFF0

BIT 4

CHSEL1

BIT 3

CHSEL0

DESCRIPTION OF THE SELECTED INPUTS

Autoscan one differential channel and one single ended channel AINP, (BINP–BINM), AINP, (BINP–BINM), …

Autoscan one differential channel and two single ended channel AINP, AINM, (BINP–BINM), AINP, …

Autoscan two differential channels (AINP–AINM), (BINP–BINM), (AINP–AINM), …

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analog input channel selection (continued)

test mode

The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 11.

Table 11. Test Mode

BIT 9

TEST1

BIT 8

TEST0

0 0 Normal mode 0 1 V 1 0 ((V 1 1 V

OUTPUT RESULT

REFP )+(V

REFM

REFP

REFM

))/2

Three different options can be selected. This feature allows support testing of hardware connections between the ADC and the processor.

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analog input channel selection (continued)

control register 1 (see Table 8)

– – BIT 9 BIT 8 BIT 7 BIT 6

– – RESERVED OFFSET BIN/2s R/W

BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

DATA_P DATA_T TRIG1 TRIG0 OVFL/FRST RESET

Table 12. Control Register 1 Bit Functions

RESET

BITS

VALUE

0 0 RESET Reset

1 0 OVFL

2, 3 0,0 F0, F1 FIFO trigger level

4 1 DATA_T DATA_AV type

5 1 DATA_P DA TA_AV polarity

6 0 R/W R/W, RD/WR selection

7 0 BIN/2s Complement select

8 0 OFFSET Offset cancellation mode

9 0 RESERVED Always write 0.

NAME FUNCTION

Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values. In addition the FIFO pointer and of fset register is reset. After reset, it takes 5 clock cycles until the first value is converted and written into the FIFO.

(read only)

FRST

(write only)

Overflow flag (read only) Bit 1 of control register 1 indicates an overflow in the FIFO. Bit 1 = 0 → no overflow occurred. Bit 1 = 1 → an overflow occurred. This bit is reset to 0, after this control register is read from the processor.

FRST: FIFO reset (write only) By writing a 1 into this bit, the FIFO is reset.

Bit 2 and bit 3 of control register 1 are used to set the trigger level for the FIFO. If the trigger level is reached, the signal DAT A_AV (data available) becomes active according to the settings of DAT A_T and DA T A_P. This indicates to the processor that the ADC values can be read. Refer to Table 13.

Bit 4 of control register 1 controls whether the DATA_AV signal is a pulse or static (e.g for edge or level sensitive interrupt inputs). If it is set to 0, the DAT A_AV signal is static. If it is set to 1, the DAT A_A V signal is a pulse. Refer to Table 14.

Bit 5 of control register 1 controls the polarity of DAT A_AV . If it is set to 1, DA TA_A V is active high. If it is set to 0, DATA_AV is active low. Refer to Table 14.

Bit 6 of control register 1 controls the function of the inputs RD to 1, WR with R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD WR

If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of control register 1 is set to 1, the output value of the ADC is in binary format. Refer to T able 3 through Table 6.

Bit 8 = 0 → normal conversion mode Bit 8 = 1 → offset calibration mode

If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conversion. The conversion result is stored in an offset register and subtracted from all conversions in order to reduce the offset error.

becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write

becomes a write input.

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and WR. When bit 6 in control register 1 is set

becomes a read input and the input

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FIFO trigger level

Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger level is reached, the DA TA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to indicate to the processor that the ADC values can be read.

T able 13 shows four different programmable trigger levels for each configuration. The FIFO trigger level, which can be selected, is dependent on the number of input channels. Both, a differential or a single-ended input is considered as one channel. The processor therefore always reads the data from the FIFO in the same order and is able to distinguish between the channels.

Table 13. FIFO Trigger Level

BIT 3

TRIG1

0 0 01 02 03 04 0 1 04 04 06 08 1 0 08 08 09 12 1 1 14 12 12 Reserved

BIT 2

TRIG0

TRIGGER LEVEL FOR 1 CHANNEL

(ADC values)

TRIGGER LEVEL

FOR 2 CHANNELS

(ADC values)

TRIGGER LEVEL FOR 3 CHANNEL

(ADC values)

TRIGGER LEVEL

FOR 4 CHANNELS

(ADC values)

Timing and Signal Description of the THS10064

The reading from the THS10064 and writing to the THS10064 is perfomed by using the chip select inputs (CS0, CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W

). This is desired in cases where the connected processor consists of a combined read/write ouput signal

(R/W). The two chip select inputs can be used to interface easily to a processor. Reading from the THS10064 takes place by an internal RD

combination of the external signals CS0

, CS1 and RD (see Figure 12). This signal is then used to strobe the words out of the FIFO and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid will make RD to its inactive state will then deactivate RD

Writing to the THS10064 takes place by an internal WR

active while the write input (WR) is inactive. The first of those external signals going

int

again.

int

signal, which is generated from the logical combination

int

of the external signals CS0, CS1 and WR. This signal is then used to strobe the control words into the control registers 0 and 1. The last external signal (either CS0

, CS1 or WR) to become valid will make WR the read input (RD) is inactive. The first of those external signals going to its inactive state will then deactivate WR

again.

int

signal, which is generated from the logical

int

active while

CS0 CS1

Data Bits

Read Enable

Write Enable

Control/Data

Registers

Figure 12. Logical Combination of CS0, CS1, RD, and WR

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DATA_AV type

Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of DATA_AV. This is shown in Table 14.

Table 14. DATA_AV Type

THS10064

BIT 5

DATA_P

0 0 Active low level 0 1 Active low pulse 1 0 Active high level 1 1 Active high pulse

BIT 4

DATA_T

DATA_AV TYPE

The signal DA TA_AV is set to active when the trigger condition is satisified. It is set back inactive independent of the DATA_T selection (pulse or level).

If level mode is chosen, DA TA_A V is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge of READ). The trigger condition is checked again after TL reads.

If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous conversion mode and one half of a clock cycle of the internal oscillator in single conversion mode. The next DA TA_AV pulse (when the trigger condition is satisfied) is sent out the earliest, when the TL values, written into the FIFO before, were read out by the processor.

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timing and signal description of the THS10064

read timing (using R/W, CS0-controlled)

Figure 13 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid.

w(CS)

CS0

CS1

10%

90%

R/W

D(0–9)

DATA_AV

90%

Figure 13. Read Timing Diagram Using R/W (CS0-controlled)

read timing parameter (CS0-controlled)

PARAMETER MIN TYP MAX UNIT

su(R/W)

d(CSDAV)

h(R/W)

w(CS)

†

CS = CS0

Setup time, R/W high to last CS valid 0 ns Access time, last CS valid to data valid 0 10 ns Delay time, last CS valid to DATA_AV inactive 12 ns Hold time, first CS invalid to data invalid 0 5 ns Hold time, first external CS invalid to R/W change 5 ns Pulse duration, CS active 10 ns

su(R/W

†

)

d(CSDAV)

90%

h(R/W)

90%

90%90%

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timing and signal description of the THS10064 (continued)

write timing (using R/W, CS0-controlled)

Figure 14 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid.

w(CS)

THS10064

CS0

CS1

D(0–9)

DATA_AV

Figure 14. Write Timing Diagram Using R/W (CS0-controlled)

read timing parameter (CS0-controlled)

PARAMETER MIN TYP MAX UNIT

su(R/W

h(R/W)

w(CS)

†

CS = CS0

Setup time, R/W stable to last CS valid 0 ns

)

Setup time, data valid to first CS invalid 5 ns Hold time, first CS invalid to data invalid 5 ns Hold time, first CS invalid to R/W change 5 ns Pulse duration, CS active 10 ns

10%

†

su(R/W

90%

10%

)

90%

h(R/W)

90%

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interfacing the THS10064 to the TMS320C30/31/33 DSP

The following application circuit shows an interface of the THS10064 to the TMS320C30/31/33 DSPs. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface.

interfacing the THS10064 to the TMS320C54x using I/O strobe

The following application circuit shows an interface of the THS10064 to the TMS320C54x. The read and write timings (using R/W

, CS0-controlled) shown before are valid for this specific interface.

THS10064 TMS320C30/31/33

CS0 CS1

CONV_CLK

THS10064 TMS320C54x

CONV_CLK

DATA_AV

DATA

CS0 CS1 R/W

DATA_AV

DATA

STRB A23 R/W INTX TOUT DATA

I/O STRB A15 R/W INTX BCLK DATA

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timing and signal description of the THS10064 (continued)

read timing (using RD, RD-controlled)

Figure 15 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only . The input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0, CS1, and RD which becomes valid.

CS0

CS1

THS10064

D(0–9)

DATA_AV

Figure 15. Read Timing Diagram Using RD (RD-controlled)

read timing parameter (RD-controlled)

PARAMETER MIN TYP MAX UNIT

su(CS)

d(CSDAV)

h(CS)

w(RD)

Setup time, RD low to last CS valid 0 ns Access time, last CS valid to data valid 0 10 ns Delay time, last CS valid to DATA_AV inactive 12 ns Hold time, first CS invalid to data invalid 0 5 ns Hold time, RD change to first CS invalid 5 ns Pulse duration, RD active 10 ns

10%

su(CS)

d(CSDAV)

w(RD

90%

h(CS)

)

10%

90%90%

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THS10064

МММММММММММММММММММММ

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timing and signal description of the THS10064 (continued)

write timing (using WR, WR-controlled)

Figure 16 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only . The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal of CS0, CS1, and WR which becomes valid.

CS0

CS1

su(CS)

w(WR)

h(CS)

D(0–9)

DATA_AV

10%

Figure 16. Write Timing Diagram Using WR (WR-controlled)

write timing parameter using WR (WR-controlled)

PARAMETER MIN TYP MAX UNIT

su(CS)

h(CS)

w(WR)

Setup time, CS stable to last WR valid 0 ns Setup time, data valid to first WR invalid 5 ns Hold time, WR invalid to data invalid 5 ns Hold time, WR invalid to CS change 5 ns Pulse duration, WR active 10 ns

10%

90%90%

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interfacing the THS10064 to the TMS320C6201 DSP

The following application circuit shows an interface of the THS10064 to the TMS320C6201. The read (using RD, RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific interface.

THS10064–1

TMS320C6201

THS10064

CS0 CS1

DATA_AV

DATA

CONV_CLK

THS10064–2

CS0 CS1

DATA_AV

DATA

CONV_CLK

CE1 EA20 ARE AWE EXT_INT6 DATA TOUT1 TOUT2 EA21 EXT_INT7

analog input configuration and reference voltage

The THS10064 features four analog input channels. These can be configured for either single-ended or differential operation. Best performance is achieved in differential mode. Figure 17 shows a simplified model, where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are V to V the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage V by:

and V

REFP

REFM

. This means that V

of 1.5 V and the voltage V

(either internal or exteral reference voltage). The analog input voltage range goes from V

defines the minimum voltage, which can be applied to the ADC. V

REFM

of 3.5 V . The resulting analog input voltage swing of 2 V can be expressed

REFP

REFM

defines

REFM

AINPvV

REFP

AINP

10-Bit

ADC

REFM

Figure 17. Single-Ended Input Stage

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analog input configuration and reference voltage (continued)

A differential operation is desired for many applications. Figure 18 shows a simplified model for the analog inputs AINM and AINP , which are configured for dif ferential operation. This configuration has a few advantages, which are discussed in the following paragraphs.

AINP

AINM

ADC

–

Figure 18. Differential Input Stage

REFP

10-Bit

ADC

REFM

In comparison to the single-ended configuration it can be seen that the voltage, V input of the ADC is the difference between the input AINP and AINM. This means that V minimum voltage (V can be applied to the ADC. The voltage V

The voltage V

ADC

REFM

) which can be applied to the ADC. V

ADC

ABS(AINP–AINM

)

can be calculated as follows:

ADC

has to satisfy the following condition:

ADC

REFP

defines the maximum voltage (V ADC) which

REFP

, which is applied at the

ADC

REFM

An advantage to single-ended operation is that the common-mode voltage

VCM+

AINM)AINP

can be rejected in the differential configuration, if the following condition for the analog input voltages is true:

AGNDvAINM, AINPvAV 1VvVCMv

In addition to the common-mode voltage rejection, the differential operation allows a dc-offset rejection which is common to both analog inputs. See also Figure 20.

single-ended mode of operation

The THS10064 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the THS10064 must be driven from an operational amplifier that does not degrade the ADC performance. Because the THS10064 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with its input requirements. This can be achieved with dc and ac coupling. An application example is shown for dc-coupled level shifting in the following section, dc coupling.

defines the

(2)

(3)

(4)

(5) (6)

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dc coupling

An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS10064. The analog input voltage range of the THS10064 goes from 1.5 V to 3.5 V. An op-amp specified for 5-V single supply can be used as shown in Figure 19.

Figure 19 shows an application example where the analog input signal in the range from –1 V up to 1 V is shifted by an op-amp to the analog input range of the THS10064 (1.5 V to 3.5 V). The op-amp is configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the noninverting input is derived from the 2.5-V output reference REFOUT of the THS10064 by using a resistor divider. Therefore, the op-amp output voltage is centered at 2.5 V. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors.

1 V 0 V

–1 V

1.25 V

5 V

_ +

3.5 V

2.5 V

1.5 V R

THS10064 AINP

REFOUT

THS10064

Figure 19. Level-Shift for DC-Coupled Input

differential mode of operation

For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is achieved in differential mode.

Mini Circuits

49.9 Ω

T4–1

200 Ω

THS10064

AINP

AINM

REFOUT

Figure 20. Transformer Coupled Input

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS10064 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

SAMPLING FREQUENCY (SINGLE-ENDED)

THD – Total Harmonic Distortion – dB

01234567

AVDD = 5 V, DVDD = BVDD = 3 V,

fIN = 500 kHz, AIN = –0.5 dB FS

fs – Sampling Frequency – MHz

Figure 21

SIGNAL-TO-NOISE AND DISTORTION

SAMPLING FREQUENCY (SINGLE-ENDED)

AVDD = 5 V, DVDD = BVDD = 3 V,

fIN = 500 kHz, AIN = –0.5 dB FS

SINAD – Signal-to-Noise and Distortion – dB

01234567

fs – Sampling Frequency – MHz

Figure 22

SPURIOUS FREE DYNAMIC RANGE

SAMPLING FREQUENCY (SINGLE-ENDED)

SFDR – Spurious Free Dynamic Range – dB

01234567

AVDD = 5 V, DVDD = BVDD = 3 V,

fIN = 500 kHz, AIN = –0.5 dB FS

fs – Sampling Frequency – MHz

Figure 23

SIGNAL-TO-NOISE

SAMPLING FREQUENCY (SINGLE-ENDED)

AVDD = 5 V, DVDD = BVDD = 3 V,

fIN = 500 kHz, AIN = –0.5 dB FS

SNR – Signal-to-Noise – dB

01234567

fs – Sampling Frequency – MHz

Figure 24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

SAMPLING FREQUENCY (DIFFERENTIAL)

THD – Total Harmonic Distortion – dB

01234567

AVDD = 5 V, DVDD = BVDD = 3 V,

fIN = 500 kHz, AIN = –0.5 dB FS

fs – Sampling Frequency – MHz

Figure 25

SIGNAL-TO-NOISE AND DISTORTION

SAMPLING FREQUENCY (DIFFERENTIAL)

AVDD = 5 V, DVDD = BVDD = 3 V,

SINAD – Signal-to-Noise and Distortion – dB

fIN = 500 kHz, AIN = –0.5 dB FS

01234567

fs – Sampling Frequency – MHz

Figure 26

SPURIOUS FREE DYNAMIC RANGE

SAMPLING FREQUENCY (DIFFERENTIAL)

100

AVDD = 5 V, DVDD = BVDD = 3 V,

fIN = 500 kHz, AIN = –0.5 dB FS

SFDR – Spurious Free Dynamic Range – dB

01234567

fs – Sampling Frequency – MHz

Figure 27

SIGNAL-TO-NOISE

SAMPLING FREQUENCY (DIFFERENTIAL)

AVDD = 5 V, DVDD = BVDD = 3 V,

fIN = 500 kHz, AIN = –0.5 dB FS

SNR – Signal-to-Noise – dB

01234567

fs – Sampling Frequency – MHz

Figure 28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS10064 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

INPUT FREQUENCY (SINGLE-ENDED)

AVDD = 5 V, DVDD = BVDD = 3 V,

THD – Total Harmonic Distortion – dB

fs = 6 MSPS, AIN = –1 dB FS

01234

fi – Input Frequency – MHz

Figure 29

SIGNAL-TO-NOISE AND DISTORTION

INPUT FREQUENCY (SINGLE-ENDED)

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –1 dB FS

SINAD – Signal-to-Noise and Distortion – dB

01234

fi – Input Frequency – MHz

Figure 30

SPURIOUS FREE DYNAMIC RANGE

INPUT FREQUENCY (SINGLE-ENDED)

AVDD = 5 V, DVDD = BVDD = 3 V,

SFDR – Spurious Free Dynamic Range – dB

fs = 6 MSPS, AIN = –1 dB FS

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

fi – Input Frequency – MHz

Figure 31

SIGNAL-TO-NOISE

INPUT FREQUENCY (SINGLE-ENDED)

AVDD = 5 V, DVDD = BVDD = 3 V,

75 70 65 60 55 50 45 40 35

SNR – Signal-to-Noise – dB

30 25 20

fs = 6 MSPS, AIN = –1 dB FS

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

fi – Input Frequency – MHz

Figure 32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

INPUT FREQUENCY (DIFFERENTIAL)

AVDD = 5 V, DVDD = BVDD = 3 V,

THD – Total Harmonic Distortion – dB

fs = 6 MSPS, AIN = –0.5 dB FS

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

fi – Input Frequency – MHz

Figure 33

SPURIOUS FREE DYNAMIC RANGE

INPUT FREQUENCY (DIFFERENTIAL)

SIGNAL-TO-NOISE AND DISTORTION

INPUT FREQUENCY (DIFFERENTIAL)

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –0.5 dB FS

SINAD – Signal-to-Noise and Distortion – dB

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

fi – Input Frequency – MHz

Figure 34

SIGNAL-TO-NOISE

INPUT FREQUENCY (DIFFERENTIAL)

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –0.5 dB FS

SFDR – Spurious Free Dynamic Range – dB

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –0.5 dB FS

fi – Input Frequency – MHz

Figure 35

SNR – Signal-to-Noise – dB

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

fi – Input Frequency – MHz

Figure 36

THS10064 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

SAMPLING FREQUENCY (SINGLE-ENDED)

AVDD = 5 V, DVDD = BVDD = 3 V,

fin = 500 kHz, AIN = –0.5 dB FS

ENOB – Effective Number of Bits – Bits

01234567

fs – Sampling Frequency – MHz

Figure 37

EFFECTIVE NUMBER OF BITS

SAMPLING FREQUENCY (DIFFERENTIAL)

AVDD = 5 V, DVDD = BVDD = 3 V,

fin = 500 kHz, AIN = –0.5 dB FS

ENOB – Effective Number of Bits – Bits

01234567

fs – Sampling Frequency – MHz

Figure 38

EFFECTIVE NUMBER OF BITS

INPUT FREQUENCY (SINGLE-ENDED)

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –1 dB FS

ENOB – Effective Number of Bits – Bits

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

fi – Input Frequency – MHz

Figure 39

EFFECTIVE NUMBER OF BITS

INPUT FREQUENCY (DIFFERENTIAL)

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –0.5 dB FS

ENOB – Effective Number of Bits – Bits

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

fi – Input Frequency – MHz

Figure 40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

TYPICAL CHARACTERISTICS

INTEGRAL NONLINEARITY

TEMPERATURE

0.70

0.68

0.66

0.64

0.62

0.60

0.58

0.56

0.54

INL – Integral Nonlinearity – LSB

0.52

AVDD = 5 V, BVDD = DVDD = 3.3 V, Differential Mode, Internal Reference, Internal Oscillator

0.5 –40 –15 10 35 60 85

TA – Temperature – °C

Figure 41

INPUT FREQUENCY (SINGLE-ENDED)

DIFFERENTIAL NONLINEARITY

0.70

0.68

0.66

0.64

0.62

0.60 AVDD = 5 V,

0.58 BVDD = DVDD = 3.3 V,

Differential Mode,

0.56 Internal Reference,

Internal Oscillator

0.54

DNL – Differential Nonlinearity – LSB

0.52

0.5 –40 –15 10 35 60 85

GAIN

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –0.5 dB FS

TEMPERATURE

TA – Temperature – °C

Figure 42

–5

–10

–15

G – Gain – dB

–20

–25

–30

0 102030405060708090100110120

fi – Input Frequency – MHz

Figure 43

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS10064 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM (4096 POINTS)

(SINGLE-ENDED)

0 –20 –40 –60 –80

–100

Magnitude – dB

–120 –140

0 0.5 1.0 1.5 2.0 2.5 3.0

FREQUENCY

f – Frequency – MHz

Figure 44

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –0.5 dB FS, fin = 1 MHz

0 –20 –40 –60 –80

Magnitude – dB

–100 –120 –140

0 0.5 1.0 1.5 2.0 2.5 3.0

FAST FOURIER TRANSFORM (4096 POINTS)

(DIFFERENTIAL)

FREQUENCY

AVDD = 5 V, DVDD = BVDD = 3 V,

fs = 6 MSPS, AIN = –0.5 dB FS, fin = 1 MHz

f – Frequency – MHz

Figure 45

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10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

definitions of specifications and terminology

integral nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points.

differential nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

zero offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point.

gain error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.

THS10064

signal-to-noise ratio + distortion (SINAD)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels.

effective number of bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

(

SINAD*1.76

it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD.

total harmonic distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.

spurious free dynamic range (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

6.02

)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

THS10064 10-BIT 6 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

MECHANICAL DATA

DA (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

38 PINS SHOWN

0,65

1,20 MAX

0,30 0,19

0,15 0,05

0,13

6,20 NOM

8,40 7,80

0,15 NOM

Gage Plane

0,25

0°–8°

0,75 0,50

Seating Plane

0,10

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. D. Falls within JEDEC MO-153

9,80

9,60

11,10

10,9010,90

12,60

12,40

4040066/D 11/98

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IMPORTANT NOTICE

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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

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TEXAS INSTRUMENTS THS10064 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual