TEXAS INSTRUMENTS THS10064 Technical data

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THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

features

D

Simultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both

D

Integrated 16-Word FIFO

D

Signal-to-Noise and Distortion Ratio: 59 dB
at f

= 2 MHz

I

D

Differential Nonlinearity Error: ±1 LSB

D

Integral Nonlinearity Error: ±1 LSB

D

Auto-Scan Mode for 2, 3, or 4 Inputs

D

3-V or 5-V Digital Interface Compatible

D

Low Power: 216 mW Max

D

5-V Analog Single Supply Operation

D

Internal Voltage References . . . 50 PPM/°C
and ±5% Accuracy

D

Parallel µC/DSP Interface

description

The THS10064 is a CMOS, low-power, 10-bit,
6 MSPS analog-to-digital converter (ADC). The
speed, resolution, bandwidth, and single-supply
operation are suited for applications in radar,
imaging, high-speed acquisition, and
communications. A multistage pipelined

applications

D

Radar Applications

D

Communications

D

Control Applications

D

High-Speed DSP Front-End

D

Automotive Applications

DA (TSSOP) PACKAGE

D0
D1
D2
D3
D4
D5

BV

DD

BGND

D6
D7
D8

D9
RA0
RA1

CONV_CLK (CONVST

DATA_AV

)

(TOP VIEW)

1

32

2

31

3

30

4

29

5

28

6

27

7

26

8

25

9

24

10

23

11

22

12

21

13

20

14

19

15

18

16

17

AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AV

DD

CS0
CS1
WR

(R/W)
RD
DV

DD

DGND

architecture with output error correction logic
provides for no missing codes over the full
operating temperature range. Internal control
registers are used to program the ADC into the desired mode. The THS10064 consists of four analog inputs,
which are sampled simultaneously . These inputs can be selected individually and configured to single-ended
or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to improve data
transfers to the processor. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.

An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the
application. Two different conversion modes can be selected. In single conversion mode, a single and
simultaneous conversion of up to four inputs can be initiated by using the single conversion start signal
(CONVST

). The conversion clock in single conversion mode is generated internally using a clock oscillator
circuit. In continuous conversion mode, an external clock signal is applied to the CONV_CLK input of the
THS10064. The internal clock oscillator is switched off in continuous conversion mode.

The THS10064C is characterized for operation from 0°C to 70°C, and the THS10064I is characterized for
operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

AVAILABLE OPTIONS

T

A

0°C to 70°C THS10064CDA

–40°C to 85°C THS10064IDA

functional block diagram

PACKAGED DEVICE

TSSOP

(DA)

REFP

REFM

REFIN

AINP

AINM

BINP

BINM

CONV_CLK (CONVST

CS0
CS1

RD

WR (R/W)

AV

DD

3.5 V

1.5 V

ADC

Control

V

REFM

10

S/H

V

REFP

S/H

S/H

S/H

)

Logic

and

Control

Single
Ended
and/or

Differential

MUX

+

–

10 Bit

Pipeline

Register

FIFO

16 × 10

DV

DD

1.225 V

10

REF

Buffers

2.5 V

REFOUT

DATA_AV

BV

DD

D0
D1

D2
D3
D4
D5

D6
D7
D8
D9
RA0
RA1

BGND

AGND DGND

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

Terminal Functions

TERMINAL

NAME NO.

AINP 32 I Analog input, single-ended or positive input of differential channel A
AINM 31 I Analog input, single-ended or negative input of differential channel A
BINP 30 I Analog input, single-ended or positive input of differential channel B
BINM 29 I Analog input, single-ended or negative input of differential channel B
AV

DD

AGND 24 I Analog ground
BV

DD

BGND 8 I Digital ground for buffer
CONV_CLK (CONVST) 15 I Digital input. This input is used to apply an external conversion clock in continuous conversion

CS0 22 I Chip select input (active low)
CS1 21 I Chip select input (active high)
DATA_AV 16 O Data available signal, which can be used to generate an interrupt for processors and as a level

DGND 17 I Digital ground. Ground reference for digital circuitry.
DV

DD

D0 – D9 1–6, 9–12 I/O/Z Digital input, output; D0 = LSB
RA0 13 I Digital input. RA0 is used as an address line for the control register . This is required for writing

RA1 14 I Digital input. RA1 is used as an address line for the control register . This is required for writing

REFIN 28 I Common-mode reference input for the analog input channels. It is recommended that this pin

REFP 26 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal

REFM 25 I Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal

REFOUT 27 O Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The

†

RD

WR (R/W)

†

The start-conditions of RD

†

23 I Analog supply voltage

7 I Digital supply voltage for buffer

mode. In single conversion mode, this input functions as the conversion start (CONVST
A high to low transition on this input holds simultaneously the selected analog input channels
and initiates a single conversion of all selected analog inputs.

information of the internal FIFO. This signal can be configured to be active low or high and can
be configured as a static level or pulse output. See Table 14.

18 I Digital supply voltage

to the control register 0 and control register 1. See Table 8.

to control register 0 and control register 1. See Table 8.

be connected to the reference output REFOUT.

reference voltage. An external reference voltage at this input can be applied. This option can
be programmed through control register 0. See Table 9.

reference voltage. An external reference voltage at this input can be applied. This option can
be programmed through control register 0. See Table 9.

reference output requires a capacitor of 10 µF to AGND for filtering and stability .

19 I The RD input is used only if the WR input is configured as a write only input. In this case, it is a

20 I This input is programmable. It functions as a read-write input R/W and can also be configured

and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.

digital input, active low as a data read select from the processor. See timing section.

as a write-only input WR
In this case, the RD

, which is active low and used as data write select from the processor.

input is used as a read input from the processor. See timing section.

) input.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

THS10064

High-level input voltage, V

Low-level input voltage, V

Operating free-air temperature, T

°C

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, DGND to DVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BGND to BVDD –0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AGND to AV

–0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

Analog input voltage range AGND – 0.3 V to AVDD + 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference input voltage –0.3 + AGND to AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range –0.3 V to BVDD/DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range,T

THS10064C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

THS10064I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

power supply

MIN NOM MAX UNIT

Supply voltage

AV
DV
BV

DD
DD
DD

4.75 5 5.25
3 3.3 5.25
3 3.3 5.25

V

analog and reference inputs

MIN NOM MAX UNIT

Analog input voltage in single-ended configuration V
Common-mode input voltage VCM in differential configuration 1 2.5 4 V
External reference voltage,V
External reference voltage, V
Input voltage difference, REFP – REFM 2 V

(optional) 3.5 AVDD–1.2 V

REFP

(optional) 1.4 1.5 V

REFM

REFM

V

REFP

digital inputs

MIN NOM MAX UNIT

p

p

Input CONV_CLK frequency DVDD = 3 V to 5.25 V 0.1 6 MHz
CONV_CLK pulse duration, clock high, t

CONV_CLK pulse duration, clock low, t

p

IH

IL

w(CONV_CLKH)

w(CONV_CLKL)

p

A

BVDD = 3.3 V 2 V
BVDD = 5.25 V 2.6 V
BVDD = 3.3 V 0.6 V
BVDD = 5.25 V 0.6 V

DVDD = 3 V to 5.25 V 80 83 5000 ns
DVDD = 3 V to 5.25 V 80 83 5000 ns
THS10064CDA 0 70
THS10064IDA –40 85

V

°

4

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THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

electrical characteristics over recommended operating conditions, DVDD = 3.3 V , A VDD = 5 V , V
= internal (unless otherwise noted)

digital specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Digital inputs

I
I
C

Digital outputs

V
V
I
C
C

High-level input current DVDD = digital inputs –50 50 µA

IH

Low-level input current Digital input = 0 V –50 50 µA

IL

Input capacitance 5 pF

i

High-level output voltage I

OH

Low-level output voltage I

OL

High-impedance-state output current CS1 = DGND, CS0 = DV

OZ

Output capacitance 5 pF

O

Load capacitance at databus D0 – D11 30 pF

L

= –50 µA, BVDD = 3.3 V, 5 V BVDD–0.5 V

OH

= 50 µA, BVDD = 3.3 V, 5 V 0.4 V

OL

DD

–10 10 µA

REF

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5

THS10064

Offset error

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

electrical characteristics over recommended operating conditions, AVDD = 5 V,
DV

= BVDD = 3.3 V, fs = 6 MSPS, V

DD

dc specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 Bits

Accuracy

Integral nonlinearity, INL ±1 LSB
Differential nonlinearity , DNL ±1 LSB

Gain error 1% FSR

Analog input

Input capacitance 15 pF
Input leakage current V

Internal voltage reference

Accuracy, V
Accuracy, V
Temperature coefficient 50 PPM/°C
Reference noise 100 µV
Accuracy, REFOUT 2.475 2.5 2.525 V

Power supply

I

DDA

I

DDD

I

DDB

I

DD_P

Analog supply current AVDD =5 V, BVDD = DVDD = 3.3 V 36 40 mA
Digital supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 0.5 1 mA
Buffer supply voltage AVDD = 5 V, BVDD = DVDD = 3.3 V 1.5 4 mA
Supply current in power-down mode AVDD = 5 V, BVDD = DVDD = 3.3 V 7 mA
Power dissipation AVDD = 5 V, DVDD = BVDD = 3.3 V 186 216 mW
Power dissipation in power down AVDD = 5 V, DVDD = BVDD = 3.3 V 30 mW

REFP
REFM

= internal (unless otherwise noted) (continued)

REF

After calibration in single-ended mode –15 15 mV
After calibration in differential mode –5 5 mV

AIN

= V

REFM

to V

REFP

3.33 3.5 3.67 V

1.42 1.5 1.58 V

±10 µA

6

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THD

T otal harmonic distortion

ENOB
SFDR

Spurious free dynamic range

THS10064

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

electrical characteristics over recommended operating conditions, V
f

= 2 MHz at –1dBFS (unless otherwise noted) (continued)

I

= internal, fs = 6 MHz,

REF

ac specifications, AVDD = 5 V, BVDD = DVDD = 3.3 V, CL < 30 pF

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Differential mode 56 59 dB

SINAD Signal-to-noise ratio + distortion

SNR Signal-to-noise ratio

(SNR)

Analog Input

NOTE 1: The SNR (ENOB) and SINAD is degraded typically by 2 dB in single-ended mode when the reading of data is asynchronous to the

Effective number of bits

p

Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.

Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.

Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.

Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.

sampling clock.

Single-ended mode
(see Note 1)

Differential mode 59 61 dB
Single-ended mode

(see Note 1)
Differential mode –67 –61 dB
Single-ended mode –67 dB
Differential mode 9 9.6 Bits
Single-ended mode

(see Note 1)
Differential mode 61 68 dB
Single-ended mode 68 dB

Full scale sinewave, –3 dB 96 MHz

Full scale sinewave, –3 dB 54 MHz

100 mVpp sinewave, –3 dB 96 MHz

100 mVpp sinewave, –3 dB 54 MHz

59 dB

60 dB

9.5 Bits

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7

THS10064

ns

t2Time between consecutive start of single conversion

ns

ns

y, _ gg

ns

ns

t

y, _ gg

ns

ns

y, _ gg

ns

ns

(

)

level condition: TRIG0 = 1, TRIG1 = 1

10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

timing specifications, AV

t

d(DATA_AV)

t

d(o)

t

pipe

Delay time 5 ns
Delay time 5 ns

Latency 5

= 5 V, BVDD = DVDD = 3.3 V, V

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

timing specification of the single conversion mode

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

c

t

w1

t

dA

d(DATA_AV)

t

d(DATA_AV)

_

†

Timing parameters are ensured by design but are not tested.

Clock cycle of the internal clock oscillator 159 167 175 ns
Pulse width, CONVST 1.5×t
Aperture time 1 ns

Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 0

Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 1, TRIG1 = 0

Delay time, DATA_AV becomes active for the trigger
level condition: TRIG0 = 0, TRIG1 = 1

Delay time, DATA_AV becomes active for the trigger

= internal, CL < 30 pF

REF

†

c

1 analog input 2×t
2 analog inputs 3×t
3 analog inputs 4×t
4 analog inputs 5×t
1 analog input, TL = 1 6×t
2 analog inputs, TL = 2 7×t
3 analog inputs, TL = 3 8×t
4 analog inputs, TL = 4 9×t
1 analog input, TL = 4 3×t2 +6×t
2 analog inputs, TL = 4 t2 +7×t
3 analog inputs, TL = 6 t2 +8×t
4 analog inputs, TL = 8 t2 +9×t
1 analog input, TL = 8 7×t2 +6×t
2 analog inputs, TL = 8 3×t2 +7×t
3 analog inputs, TL = 9 2×t2 +8×t
4 analog inputs, TL = 12 2×t2 +9×t
1 analog input, TL = 14 13×t2 +6×t
2 analog inputs, TL = 12 5×t2 +7×t
3 analog inputs, TL = 12 3×t2 +8×t

c
c
c
c

c
c
c
c
c
c
c
c
c
c
c
c
c
c
c

CONV

CLK

ns

ns

8

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10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

detailed description

reference voltage

The THS10064 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to

3.5 V and VREFM is set to 1.5 V . An external reference can also be used through two reference input pins, REFP
and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish
the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.

analog inputs

The THS10064 consists of 4 analog inputs, which are sampled simultaneously . These inputs can be selected
individually and configured as single-ended or differential inputs. The desired analog input channel can be
programmed.

analog-to-digital converter

The THS10064 uses a 10-bit pipelined multistaged architecture with 4 1-bit stages followed by 4 2-bit stages,
which achieves a high sample rate with low power consumption. The THS10064 distributes the conversion over
several smaller ADC sub-blocks, refining the conversion with progressively higher accuracy as the device
passes the results from stage to stage. This distributed conversion requires a small fraction of the number of
comparators used in a traditional flash ADC. A sample-and-hold amplifier (SHA) within each of the stages
permits the first stage to operate on a new input sample while the second through the eighth stages operate
on the seven preceding samples.

THS10064

conversion modes

The conversion can be performed in two different conversion modes. In the single conversion mode, the
conversion is initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In
the continuous conversion mode, an external clock signal is applied to the clock input (CONV_CLK). A new
conversion is started with every falling edge of the applied clock signal.

sampling rate

The maximum possible conversion rate per channel is dependent on the selected analog input channels. T able
1 shows the maximum conversion rate in the continuous conversion mode for different combinations.

Table 1. Maximum Conversion Rate in Continuous Conversion Mode

CHANNEL CONFIGURATION

1 single-ended channel 1 6 MSPS
2 single-ended channels 2 3 MSPS
3 single-ended channels 3 2 MSPS
4 single-ended channels 4 1.5 MSPS
1 differential channel 1 6 MSPS
2 differential channels 2 3 MSPS
1 single-ended and 1 differential channel 2 3 MSPS
2 single-ended and 1 differential channels 3 2 MSPS

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:

6 MSPS

fc

+

# channels

Table 2 shows the maximum conversion rate in the single conversion mode.

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9

THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

sampling rate (continued)

Table 2. Maximum Conversion Rate in Single Conversion Mode

CHANNEL CONFIGURATION

1 single-ended channel 1 3 MSPS
2 single-ended channels 2 2 MSPS
3 single-ended channels 3 1.5 MSPS
4 single-ended channels 4 1.2 MSPS
1 differential channel 1 3 MSPS
2 differential channels 2 2 MSPS
1 single-ended and 1 differential channel 2 1.5 MSPS
2 single-ended and 1 differential channels 3 1.2 MSPS

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

single conversion mode

In single conversion mode, a single conversion of the selected analog input channels is performed. The single
conversion mode is selected by setting bit 1 of control register 0 to 1.

A single conversion is initiated by pulsing the CONVST input. On the falling edge of CONVST, the sample and
hold stages of the selected analog inputs are placed into hold simultaneously, and the conversion sequence
for the selected channels is started.

The conversion clock in single conversion mode is generated internally using a clock oscillator circuit. The signal
DATA_AV (data available) becomes active when the trigger level is reached and indicates that the converted
sample(s) is (are) written into the FIFO and can be read out. The trigger level in the single conversion mode
can be selected according to Table 13.

Figure 1 shows the timing of the single conversion mode. In this mode, up to four analog input channels can
be selected to be sampled simultaneously (see Table 2).

t

2

CONVST

AIN

Sample N

DATA_AV,

Trigger Level = 1

t

d(A)

t

1

t

DATA_AV

t

1

Figure 1. Timing of Single Conversion Mode

The time (t2) between consecutive starts of single conversions is dependent on the number of selected analog
input channels. The time t

DA TA_AV

, until DA TA_AV becomes active is given by: t

DA TA_AV

= t

pipe

+ n × tc. This
equation is valid for a trigger level which is equivalent to the number of selected analog input channels. For all
other trigger level conditions refer to the timing specifications of single conversion mode.

10

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10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

continuous conversion mode

The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode.
In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running
external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is
written into the FIFO. The first conversion value is written into the FIFO with a latency of 8 + TL (trigger level)
clock cycles after the FIFO reset.

Figure 2 shows the timing of continuous conversion mode when one analog input channel is selected. The
maximum throughput rate is 6 MSPS in this mode. The timing of the DA T A_A V signal is shown here in the case
of a trigger level set to 1 or 4.

AIN

t

w(CONV_CLKH)

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 1

DATA_AV,

Trigger Level = 4

Sample N
Channel 1

Sample N+1

Channel 1

t

d(A)

t

50% 50%

t

c

Data N–5

Channel 1

Sample N+2

Channel 1

t

d(pipe)

w(CONV_CLKL)

Data N–4

Channel 1

Channel 1

Sample N+3

Data N–3

Channel 1

Sample N+4

Channel 1

Data N–2

Channel 1

t

d(O)

Data N–1

Channel 1

Sample N+5

Channel 1

Channel 1

Data N

Sample N+6

Channel 1

Data N+1

Channel 1

Sample N+7

Channel 1

Data N+2

Channel 1

t

d(DATA_AV)

Sample N+8

Channel 1

Data N+3
Channel 1

t

d(DATA_AV)

THS10064

Figure 2. Timing of Continuous Conversion Mode (1-channel operation)

Figure 3 shows the timing of continuous conversion mode when two analog input channels are selected. The
maximum throughput rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows
the order the converted data is written into the FIFO. The timing of the DA TA_A V signal shown here is for a trigger
level set to 2 or 4.

AIN

t

w(CONV_CLKH)

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 2

DATA_AV,

Trigger Level = 4

Sample N

Channel 1,2

t

d(A)

50% 50%

t

c

Data N–3

Channel 2

Sample N+1

Channel 1,2

t

d(Pipe)

t

w(CONV_CLKL)

Data N–2

Channel 1

Data N–2

Channel 2

Sample N+2
Channel 1,2

Data N–1

Channel 1

t

d(O)

Data N–1

Channel 2

Sample N+3
Channel 1,2

Data N

Channel 1

Data N

Channel 2

Sample N+4
Channel 1,2

Data N+1

Channel 1

t

t

Data N+1

Channel 2

d(DATA_AV)

d(DATA_AV)

Figure 3. Timing of Continuous Conversion Mode (2-channel operation)

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THS10064
10-BIT 6 MSPS, SIMULTANEOUS SAMPLING
ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

continuous conversion mode (continued)

Figure 4 shows the timing of continuous conversion mode when three analog input channels are selected. The
maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows
in which order the converted data is written into the FIFO. The timing of the DA TA_AV signal shown here is for
a trigger level set to 3.

AIN

t

w(CONV_CLKH)

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 3

Sample N

Channel 1,2,3

t

d(A)

50% 50%

t

c

Data N–2
Channel 2

t

d(Pipe)

t

w(CONV_CLKL)

Data N–2

Channel 3

Sample N+1

Channel 1,2,3

Data N–1

Channel 1

Data N–1

Channel 2

t

d(O)

Data N–1

Channel 3

Channel 1,2,3

Data N

Channel 1

Sample N+2

Channel 2

Data N

t

d(DATA_AV)

Data N

Channel 3

Figure 4. Timing of Continuous Conversion Mode (3-channel operation)

Figure 5 shows the timing of continuous conversion mode when four analog input channels are selected. The
maximum throughput rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows
in which order the converted data is written into the FIFO. The timing of the DA TA_AV signal shown here is for
a trigger level of 4.

AIN

t

w(CONV_CLKH)

CONV_CLK

Data Into

FIFO

DATA_AV,

Trigger Level = 4

Sample N

Channel 1,2,3,4

t

d(A)

50% 50%

t

c

Data N–2

Channel 4

t

t

d(Pipe)

w(CONV_CLKL)

Data N–1

Channel 1

Data N–1
Channel 2

Sample N+1

Channel 1,2,3,4

Data N–1

Channel 3

t

d(O)

Data N–1

Channel 4

Data N

Channel 1

Data N

Channel 2

Sample N+2

Channel 1,2,3,4

Data N

Channel 3

t

d(DATA_AV)

Data N

Channel 4

Figure 5. Timing of Continuous Conversion Mode (4-channel operation)

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10-BIT 6 MSPS, SIMULTANEOUS SAMPLING

ANALOG-TO-DIGITAL CONVERTER

SLAS255 – DECEMBER 1999

digital output data format

The digital output data format of the THS10064 can either be in binary format or in two’s complement format.
The following tables list the digital outputs for the analog input voltages.

Table 3. Binary Output Format for Single-Ended Configuration

SINGLE-ENDED, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

AIN = V

REFP

AIN = (V
AIN = V

REFP

REFM

+ V

)/2 200h

REFM

Table 4. Two’s Complement Output Format for Single-Ended Configuration

SINGLE-ENDED, TWOS COMPLEMENT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

AIN = V

REFP

AIN = (V
AIN = V

REFP

REFM

+ V

)/2 000h

REFM

3FFh

000h

1FFh

200h

THS10064

Table 5. Binary Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

Vin = AINP – AINM

V

= V

REF

Vin = V

REF

Vin = 0 200h
Vin = –V

REF

REFP

– V

REFM

3FFh

000h

Table 6. Two’s Complement Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE

Vin = AINP – AINM

V

= V

REF

Vin = V

REF

Vin = 0 000h
Vin = –V

REF

REFP

– V

REFM

1FFh

200h

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