Texas Instruments THS0842IPFB, THS0842EVM Datasheet

THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

features

D

Dual Simultaneous Sample and Hold Inputs

D

Differential or Single-Ended Analog Inputs

D

8-Bit Resolution 40 MSPS Sampling
Analog-to-Digital Converter (ADC)

D

Single or Dual Parallel Bus Output

D

Low Power Consumption: 275 mW Typ
Using External References

D

Wide Analog Input Bandwidth: 600 MHz Typ

D

3.3 V Single-Supply Operation

D

3.3 V TTL/CMOS-Compatible Digital I/O

D

Internal or External Bottom and Top
Reference V oltages

D

Adjustable Reference Input Range

D

Power-Down (Standby) Mode

D

48-Pin Thin Quad Flat Pack (TQFP)
Package

applications

D

Digital Communications (Baseband
Sampling)

D

Cable Modems

D

Set Top Boxes

D

Test Instruments

description

The THS0842 is a dual 8-bit 40 MSPS high-speed A/D converter. It alternately converts each analog input signal
into 8-bit binary-coded digital words up to a maximum sampling rate of 40 MSPS with an 80 MHz clock. All digital
inputs and outputs are 3.3 V TTL/CMOS-compatible.

Thanks to an innovative single-pipeline architecture implemented in a CMOS process and the 3.3 V supply, the
device consumes very little power. In order to provide maximum flexibility, both bottom and top voltage
references can be set from user supplied voltages. Alternately , if no external references are available, on-chip
references can be used which are also made available externally . The full-scale range is 1 Vpp, depending on
the analog supply voltage. If external references are available, the internal references can be powered down
independently from the rest of the chip, resulting in an even greater power saving.

The device is specifically suited for the baseband sampling of wireless local loop (WLL) communication, cable
modems, set top boxes (STBs), and test instruments.

AVAILABLE OPTIONS

PACKAGED DEVICES

T

A

TQFP-48

–40°C to 85°C THS0842IPFB

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

23

DRV

SS

DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
NC
NC
DRV

DD

24
23
22
21
20
19
18
17
16
15
14
13

4

37
38
39
40
41
42
43
44
45
46
47
48

AV

DD

I+

I–

AV

SS

AV

DD

STBY
DV

SS

SELB

DV

DD

AV

SS

CLK

OE

5678

BGAVAV

C

35 34 33 32 3136 30

AVQ–Q+

PWDN_REF

CML

DB1

DB0

SS

NC

DB6

DB5

DB4

DB3

DB2

28 27 2629

9

10 11 12

25

1

C

REFT

REFB

NC

DD

DB7

PFB PACKAGE

(TOP VIEW)

DRV

DRV

SS

DD

OUT

SS

OUT

Copyright  1999, Texas Instruments Incorporated

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

MUX

Sample

& Hold

Sample

& Hold

BUS
MUX

8 BIT

ADC

3-State
Output
Buffers

Configuration

Control

Circuit

OE

DA(7–0)

I +

I –

Q +

Q –

STBY

CLK

CM

Internal

Reference

Circuit

REFT REFB CML

PWDN

REF

SELB DRV

SS

DV

SS

DRV

DD

DV

DD

Timing Circuitry

AV

SS

AV

DD

C

OUT

C

OUT

BG

DB(7–0)

THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ADC pipeline block diagram

SHA

DACADC

+

–

ADC

Correction Logic

Output Buffers

2222 2

D0(LSB)–D7(MSB)

2

2

SHA SHA SHA SHA SHA

The single-pipeline architecture uses 6 ADC/DAC stages and one final flash ADC. Each stage produces a
resolution of 2 bits. Digital correction logic generates its result using the 2-bit result from the first stage, 1 bit from
each of the 5 succeeding stages, and 1 bit from the final stage in order to arrive at an 8-bit result. The correction
logic ensures no missing codes over the full operating temperature range.

circuit diagrams of inputs and outputs

DV

DD

AV

DD

AV

DD

0.5 pF

Internal
Reference
Generator

REFTO
or
REFBO

AV

DD

REFBI

or

REFTI

OE

ALL DIGITAL INPUT CIRCUITS AIN INPUT CIRCUIT

REFERENCE INPUT CIRCUIT D0–D7 OUTPUT CIRCUIT

DRV

DD

DRV

SS

D_Out

D

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AV

DD

27, 37, 41 I Analog supply voltage

AV

SS

28, 36, 40,46I Analog ground

BG 29 O Band gap reference voltage. A 1-µF capacitor with a 0.1-µF capacitor in parallel should be connected

between this terminal and A VSS for external filtering.
CLK 47 I Clock input. The input is sampled on each rising edge of CLK.
CML 32 O Common mode level. This voltage is equal to (A VDD – AVSS)/2. An external 1-µF capacitor with a 0.1-µF

capacitor in parallel should be connected between this terminal and AVSS.
C

OUT

26 O Latch clock for the data outputs

C

OUT

25 O Inverted latch clock for the data outputs

DB7 – DB0 4 – 11 O Data outputs. D7 is the MSB. This is the second bus. Data is output from the Q channel when dual bus

output mode is selected. Pin SELB selects the output mode.
DRV

DD

1, 13 I Supply voltage for output drivers

DRV

SS

12, 24 I Ground for digital output drivers

DA7 – DA0 16 – 23 I Data outputs for bus A. D7 is MSB. This is the primary bus. Data from both input channels can be output

on this bus or data from the I channel only. Pin SELB selects the output mode.
DV

DD

45 I Digital supply voltage

DV

SS

43 I Digital ground
I– 39 I Negative input for analog channel 0.
I+ 38 I Positive input for analog channel 0.
NC 2,3,14,15 No connect. Reserved for future use
OE 48 I Output enable. A high on this terminal will disable the output bus.
PWDN_REF 33 I Power down for internal reference voltages. A high on this terminal will disable the internal reference

circuit.
Q– 35 I Negative input for analog channel 1
Q+ 34 I Positive input for analog channel 1
REFB 30 I/O Reference voltage bottom. The voltage at this terminal defines the bottom reference voltage for the ADC.

Sufficient filtering should be applied to this input. A 1-µF capacitor with a 0.1-µF capacitor in parallel should

be connected between REFB and AVSS. Additionally , a 0.1-µF capacitor can be connected between REFT

and REFB.
REFT 31 I/O Reference voltage top. The voltage at this terminal defines the top reference voltage for the ADC. Sufficient

filtering should be applied to this input. A 1-µF capacitor with a 0.1-µF capacitor in parallel should be

connected between REFT and AVSS. Additionally , a 0.1-µF capacitor can be connected between REFT

and REFB.
SELB 44 I Selects either single bus or data output or dual bus output data output. A low selects dual bus data output.
STBY 42 I Standby input. A high level on this terminal will power down the device.

THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage: AVDD to AGND, DVDD to DGND –0.5 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage: AVDD to DVDD, AGND to DGND –0.5 V to 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital input voltage range to DGND –0.5 V to DV

DD

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog input voltage range to AGND –0.5 V to AVDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital output voltage applied from external source to DGND –0.5 V to DVDD + 0.5 V. . . . . . . . . . . . . . . . . . .

Reference voltage input range to AGND: V

(REFT)

, V

(REFB)

–0.5 V to AVDD + 0.5 V. . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA: –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–55°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions over operating free-air temperature range

power supply

MIN NOM MAX UNIT

AV

DD

Supply voltage

DV

DD

3 3.3 3.6 V

DRV

DD

analog and reference inputs

MIN NOM MAX UNIT

Reference input voltage (top), V

(REFT)

(NOM) – 0.2 AVDD – 1 (NOM) + 0.2 V

Reference input voltage (bottom), V

(REFB)

0.8 1 1.2 V

Reference voltage differential, V

(REFT)

– V

(REFB)

AVDD – 2 V

Analog input voltage, V

(IN)

V

(REFB)

V

(REFT)

V

digital inputs

MIN NOM MAX UNIT

High-level input voltage, V

IH

2.0 DV

DD

V

Low-level input voltage, V

IL

DGND 0.2xDV

DD

V

Clock period, t

c

12.5 ns

Pulse duration, clock high, t

w(CLKH)

5.25 ns

Pulse duration, clock low, t

w(CLKL)

5.25 ns

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions with f

CLK

= 80 MSPS and use

of internal voltage references, AV

DD

= DVDD = DRVDD = 3 V , TA = –40°C to 80°C, dual output bus mode

(unless otherwise noted)

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

AV

DD

73 95

I

DD

Operating supply current

DV

DD

AVDD = DVDD = DRVDD = 3.3 V,

p

–

3 3.8

mA

DRV

DD

C

L

= 15 F,

V

I

= 1

MHz

, –1

dBFS

17 22

p

PWDN_REF = L 320 393

PDPower dissipation

PWDN_REF = H 275 335

mW

P

D(STBY)

Standby power STBY = H, CLK held high or low 11 15

logic inputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level input current on CLK

†

AVDD = DVDD = DRVDD = CLK = 3.6 V 10 µA

I

IL

Low-level input current on digital inputs
(OE

, STDBY, PWDN_REF, CLK)

AVDD = DVDD = DRVDD = 3.6 V,
Digital inputs at 0 V

10 µA

CIInput capacitance 5 pF

†

IIH leakage current on other digital inputs (OE

, STDBY , PWDN_REF) is not measured since these inputs have an internal pull-down resistor of

4 KΩ to DGND.

logic outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

OH

High-level output voltage

AVDD = DVDD = DRVDD = 3 V at IOH = 50 µA,
Digital output forced high

2.8 V

V

OL

Low-level output voltage

AVDD = DVDD = DRVDD = 3.6 V at IOL = 50 µA,
Digital output forced low

0.1 V

C

O

Output capacitance 5 pF

I

OZH

High-impedance state output current to
high level

10 µA

I

OZL

High-impedance state output current to
low level

AV

DD

=

DV

DD

=

DRV

DD

= 3.6

V

10 µA

THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions with f

CLK

= 80 MSPS and use

of internal voltage references, AV

DD

= DVDD = DRVDD = 3 V , TA = –40°C to 80°C, dual output bus mode

(unless otherwise noted) (continued)

dc accuracy

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Integral nonlinearity (INL), best-fit See Note 1 TA = –40°C to 85°C –2.2 ±1.5 2.2 LSB
Differential nonlinearity (DNL) See Note 2 TA = –40°C to 85°C –1 ±0.7 2 LSB
Offset error

°

°

±0.1 5 %FS

Gain error

T

A

= –

40°C to 85°C, (see Note 3)

±7.1 %FS
Offset match TA = –40°C to 85°C, (see Note 4) –1 ±0.1 1 LSB
Gain match TA = –40°C to 85°C, (see Note 5) –5 1 LSB
Missing codes – no missing codes assured

NOTES: 1. Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero to full scale. The point used as zero

occurs 1/2 LSB before the first code transition. The full–scale point is defined as a level 1/2 LSB beyond the last code transition.

The deviation is measured from the center of each particular code to the best fit line between these two endpoints.

2. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore this measure
indicates how uniform the transfer function step sizes are. The ideal step size is defined here as the step size for the device under
test (i.e., (last transition level – first transition level) ÷ (2n – 2)). Using this definition for DNL separates the effects of gain and offset
error. A minimum DNL better than –1 LSB ensures no missing codes.

3. Offset error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 0 to code 1. The ideal voltage level is determined by adding the voltage corresponding to 1/2 LSB to the
bottom reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (256).

Gain error is defined as the difference in analog input voltage – between the ideal voltage and the actual voltage – that will switch
the ADC output from code 254 to code 255. The ideal voltage level is determined by subtracting the voltage corresponding to 1.5
LSB from the top reference level. The voltage corresponding to 1 LSB is found from the difference of top and bottom references
divided by the number of ADC output levels (256).

4. Offset match is the change in offset error between I and Q channels.

5. Gain match is the change in gain error between I and Q channels.

analog input

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

C

I

Input capacitance 4 pF

reference input (AVDD = DVDD = DRVDD = 3.6 V)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R

ref

Reference input resistance 200 Ω

I

ref

Reference input current 5 mA

reference outputs

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(REFT)

Reference top voltage

2 + [(AVDD – 3)/2]

V

(REFB)

Reference bottom voltage

AV

DD

=

3 V

1 + [(AVDD – 3)/2]

V

V

REFB–VREFB

Absolute min/max values valid
and tested for AVDD = 3 V

0.9 1 1.3 V

THS0842
DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER
WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating conditions with f

CLK

= 80 MSPS and use

of internal voltage references, AV

DD

= DVDD = DRVDD = 3 V , TA = –40°C to 80°C, dual output bus mode

(unless otherwise noted) (continued)

dynamic performance

†

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

fin = 1 MHz 6.6 6.9

Effective number of bits, ENOB

fin = 15 MHz 6.4 6.8

Bits
fin = 20 MHz 6.4 6.8
fin = 1 MHz 41.5 43.5

Signal-to-total harmonic distortion + noise, S/(THD+N)

fin = 15 MHz 40 42.5

dB
fin = 20 MHz 40 42.5
fin = 1 MHz –51 –46

Total harmonic distortion (THD)

fin = 15 MHz –48.5 –44

dB
fin = 20 MHz –48.5 –44
fin = 1 MHz 48 53

Spurious free dynamic range (SFDR)

fin = 15 MHz 47 52.2

dB
fin = 20 MHz 46 52

Analog input full-power bandwidth, BW See Note 6 600 MHz
Intermodulation distortion f1 = 1 MHz, f2 = 1.02 MHz 50 dBc
I/Q channel crosstalk AVDD = DVDD = DRVDD = 3.3 V –52 dBc

†

Based on analog input voltage of –1 dBFS referenced to a 1.3 Vpp full-scale input range.

NOTE 6: The analog input bandwidth is defined as the maximum frequency of a –1 dBFS input sine that can be applied to the device for which

an extra 3 dB attenuation is observed in the reconstructed output signal.

timing requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Maximum clock rate (see Note 7) 80 MHz

f

clk

Minimum clock rate 10 kHz

t

d(O)

Output delay time (see timing diagram) CL = 10 pF 9 ns

t

h(O)

Output hold time from C

OUT

or C

OUT

to data invalid 2 ns

p

I data 5.5 5.5 5.5

CLK

t

d(pipe)

Pipeline delay (latency)

Q data 6.5 6.5 6.5

cycles

t

d(a)

Aperture delay time 3 ns

t

j(a)

Aperture jitter 1.5 ps, rms

t

dis

Disable time, OE rising to Hi-Z 5 ns

t

en

Enable time, OE falling to valid data 5 ns

t

su(O)

Output setup time from data to C

OUT

or C

OUT

8 7 ns

NOTE 7: Conversion rate is 1/2 the clock rate, f

clk

.

THS0842

DUAL-INPUT, 8-BIT, 40 MSPS LOW-POWER ANALOG-TO-DIGITAL CONVERTER

WITH SINGLE OR DUAL PARALLEL BUS OUTPUT

SLAS246 – DECEMBER 1999

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

C

OUT

01234567 910118 12131415

I5Q4I4Q3I3Q2I2Q1I1Q–1I–1Q–2I–2Q–3I–3 Q5

DA(7–0)

CLK

Q

I

t

h(O)

t

su(O)

t

d(O)

t

d(pipe-I)

N

N

N+1

N+1

N+2

N+2

N+3

N+3

N+4

N+4

t

d(A)

t

J(A)

t

d(pipe-Q)

t

d(O)

C

OUT

NOTE A: The relationship between CLK and C

OUT/COUT

is not fixed and depends on the power-on conditions. Data out should be referenced

to C

OUT

and C

OUT

.

Figure 1. Timing Diagram, Single Bus Output