TEXAS INSTRUMENTS TFP9431 Technical data

PanelBus DVI RECEIVER WITH TRIPLE DAC

SLDS122A – MARCH 2000 – REVISED JUNE 2000

D

Supports VGA to UXGA Resolutions (Pixel
Rates up to 165 MHz)

D

Digital Visual Interface (DVI) 1.0
Specification Compliant

D

Integrated 165 MHz Triple 8-Bit Video DAC

1

Provides VGA Outputs

D

True-Color, 24 Bits/Pixel, 16.7 M Colors

D

Skew Tolerant Up to One Full Input Clock
Cycle

D

4x Over-Sampling

description

The TFP9431 is a PanelBust digital display product, part of a comprehensive family of end-to-end DVI 1.0
compliant solutions. Targeted at premium digital CRT monitors, the TFP9431 finds applications in designs
requiring a high-speed digital interface with analog output.

The TFP9431 integrates a 165 MHz PanelBust receiver core with a 165 MHz triple 8-bit video DAC to provide
a single chip solution for enabling next generation CRT monitors requiring digital connectivity and enhanced
display quality . The TFP9431 supports display resolutions up to UXGA (1600 x 1200) at 60 Hz and a 24-bit color
depth (16.7 M colors).

D

Laser Trimmed Input Stage for Optimum
Fixed Impedance Matching

D

Reduced Power Consumption - 1.8 V Core
Operation With 3.3 V I/Os and Supplies

D

Lowest Noise and Best Power Dissipation
Using PowerP ADt Packaging

D

Advanced Technology Using Texas
Instruments 0.18 µm EPIC-5t CMOS
Process

D

HSYNC Regeneration Circuitry

3

TFP9431

2

PowerPAD advanced packaging technology results in best in class power dissipation, footprint, and ultra-low
ground inductance.

The TFP9431 combines PanelBust circuit innovation with TI’s advanced 0.18 µm EPIC-5t CMOS process
technology along with PowerP ADt package technology to provide a reliable, low-power, low-noise, high-speed
digital interface solution.

AVAILABLE OPTIONS

PACKAGED DEVICE

T

A

0°C to 70°C TFP9431CPAP

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1. The Digital Visual Interface (DVI) specification is an industry standard developed by the Digital Display Working Group (DDWG) for
high-speed digital connection to digital displays.

2. The TFP9431 has an internal voltage regulator that provides the 1.8V core power supply from the externally supplied 3.3V supplies.

3. The TFP9431 incorporates additional circuitry to create a stable HSYNC from DVI transmitters that introduce undesirable jitter on the
transmitted HSYNC signal.

64-TQFP

(PAP)

PRODUCT PREVIEW

EPIC-5, PowerPAD, and PanelBus are trademarks of Texas Instruments.
Other trademarks are property of their respective owners.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  2000, Texas Instruments Incorporated

1

TFP9431
PanelBus DVI RECEIVER WITH TRIPLE DAC

SLDS122A – MARCH 2000 – REVISED JUNE 2000

100-PIN PACKAGE

(TOP VIEW)

CC

AV

RXC–

RXC+

AGND

RX0–

RX0+

AGNDAVAGND

CC

RX1–

RX1+

CC

AV

CC

AV

AGND

RX2+

RX2–

AGND

EXT_RES

PV

CC

PGND

TESTB

OCK_INV

DFO

PD

ST

NC

GND

V

CC

NC

SCDT

PDO

V

CC

63 62 61 60 5964 58

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1718 19

GND

NC

20

CC

DACV

TFP9431

21 22 23 24

COMP

FSADJ

BLUDAC

56 55 5457

25 26 27 28 29

REDDAC

DACGND

GRNDAC

NC

53 52

DE

CC

DACV

51 50 49

30 31 32

VS

HS

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

CTL1

CTL2

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A0
OGND
ODCK
OV

CC

CTL3

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

functional block diagram

3.3 V

Internal 50-Ω

Termination

TFP9431

PanelBus DVI RECEIVER WITH TRIPLE DAC

SLDS122A – MARCH 2000 – REVISED JUNE 2000

3.3 V

1.8 V

Regulator

Rx2+

Rx2-

Rx1+

Rx1-

Rx0+

Rx0-

RxC+

RxC-

TERMINAL

NAME NO.

AGND 1,52,56,5

8,61

AV

CC

51,53,57,64V

+
_

+
_

+
_

+
_

Latch

Latch

Latch

PLL

Channel 2

Channel 1

Channel 0

Data Recovery

and

Synchronization

CH2[9:0]

CH1[9:0]

CH0[9:0]

TMDS

Decoder

Bandgap

Reference

Comp

RED[7:0]

GRN[7:0]

BLU[7:0]

VREF

FSADJ

Terminal Functions

GND Analog Ground – Ground reference and current return for analog circuitry .

Analog VCC – Power supply for analog circuitry. Nominally 3.3 V

CC

DAC

DAC

DAC

ARPr

AGY

ABPb

CTL[3:1]
ODCK
DE
HS

VS

A0 37 DI The A0 configuration bit controls the HSYNC jitter fix mode of the chip.

1 : Normal mode with HSYNC fix

0 : Normal mode without HSYNC fix
BLUDAC 22 A Analog blue output
COMP 20 A Compensation for the internal reference amplifier . A 0.1 µF capacitor should be connected between this pin

and DACVCC.
CTL[3:1] 31,32,33 DO General-purpose control signals – Used for user defined control. In normal mode CTL1 is not powered-down

via PDO

.
DACGND 24 GND DAC ground – Ground reference and current return for the DACs.
DACV

CC

19,27 VCC DAC VCC – Power supply for the DACs. Nominally 3.3 V

DE 28 DO Output data enable – Used to indicate time of active video display versus non-active display or blank time.

During blank, only HSYNC, VSYNC, and CTL1-3 are transmitted. During times of active display, or non-blank,
only video data, GRNDAC, REDDAC, BLUDAC is transmitted.

High : Active display time
Low: Blank time

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TFP9431

I/O

DESCRIPTION

PanelBus DVI RECEIVER WITH TRIPLE DAC

SLDS122A – MARCH 2000 – REVISED JUNE 2000

Terminal Functions (continued)

TERMINAL

NAME NO.

DFO 7 DI Output clock data format – Controls the output clock (ODCK) format for either TFT or DSTN panel support. For

EXT_RES 2 AI Internal impedance matching – The TFP9431 is internally optimized for impedance matching at 50 Ω.. An

FSADJ 21 A Full scale adjust control – A 2 kΩ resistor should be connected between this pin and DACGND to control the

GND 11,17 GND Digital ground – Ground reference and current return for digital core
GRNDAC 25 A Analog green output
HS 30 DO Horizontal sync output
NC 10,13,

NC 18,26 DI Reserved
NC 41–48 DO Reserved
OCK_INV 6 DI ODCK Polarity – Selects ODCK edge on which pixel data and control signals (HSYNC, VSYNC, DE, CTL1-3 )

ODCK 35 DO Output data clock - Pixel clock. All pixel outputs GRNDAC,REDDAC, BLUDAC, and Q[7:0] along with DE,

OGND 36 GND Output driver ground – Ground reference and current return for digital output drivers
OV

CC

PD 8 DI Power down – An active low signal that controls the TFP9431 power-down state. During power down all output

PDO 15 DI Output drive power down – An active low signal that controls the power-down state of the output drivers.

PGND 4 GND PLL ground – Ground reference and current return for internal PLL
PV

CC

REDDAC 23 A Analog red output
RSVD 99 DI Reserved. Must be tied high for normal operation.
RxC+ 62 AI Clock positive receiver input – Positive side of reference clock. TMDS low voltage signal differential input pair
RxC– 63 AI Clock negative receiver input – Negative side of reference clock. TMDS low voltage signal differential input

Rx0+ 59 AI Channel-0 positive receiver input – Positive side of channel-0. TMDS low voltage signal differential input pair.

38–40

34 V

3 V

TFT support ODCK clock runs continuously. For DSTN support ODCK only clocks when DE is high, otherwise
ODCK is held low when DE is low.

High : DSTN support/ODCK held low when DE = low
Low: TFT support/ODCK runs continuously.

external resistor tied to this pin an A VCC will have no effect on device performance.

full scale output current on the analog outputs.

DI Reserved

are latched
Normal Mode:

High : Latches output data on rising ODCK edge
Low : Latches output data on falling ODCK edge

HSYNC, VSYNC and CTL[3:1] are synchronized to this clock.

Output driver VCC – Power supply for output drivers. Nominally 3.3 V

CC

buffers are switched to a high impedance state and brought low through a weak pulldown. All analog circuits
are powered down and all inputs are disabled, except for PD

is left unconnected an internal pullup will default the TFP9431 to normal operation.

If PD
High : Normal operation

Low: Power down

During output drive power down, the output drivers (except SCDT and CTL1) are driven to a high impedance
state and the DACs are switched off.. A weak pulldown will slowly pull these outputs to a low level. When PDO
is left unconnected, an internal pullup defaults the TFP9431 to normal operation.

High : Normal operation/output drivers on
Low: Output drive power down.

PLL VCC – Power supply for internal PLL

CC

pair.

Channel-0 receives blue pixel data in active display and HSYNC, VSYNC control signals in blank.

.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

TFP9431

PanelBus DVI RECEIVER WITH TRIPLE DAC

SLDS122A – MARCH 2000 – REVISED JUNE 2000

Terminal Functions (continued)

TERMINAL

NAME NO.

Rx0– 60 AI Channel-0 negative receiver input – Negative side of channel-0. TMDS low voltage signal differential input

Rx1+ 54 AI Channel-1 positive receiver input – Positive side of channel-1 TMDS low voltage signal differential input pair.

Rx1– 55 AI Channel-1 negative receiver input – Negative side of channel-1 TMDS low voltage signal differential input pair
Rx2+ 49 AI Channel-2 positive receiver input – Positive side of channel-2 TMDS low voltage signal differential input pair.

Rx2- 50 AI Channel-2 negative receiver input – Negative side of channel-2 TMDS low voltage signal differential input pair.
SCDT 14 DO Sync detect – Output to signal when the link is active or inactive. The link is considered to be active when DE is

ST 9 DI Output drive strength select – Selects output drive strength for high or low current drive for digital outputs. (See

TESTB 5 I T est mode enable – This pin must be tied low for normal mode of operation. Connecting this pin to high puts

V

CC

VS 29 DO Vertical sync output

12, 16 VCC Digital VCC – Power supply for digital core. Nominally 3.3 V

pair.

Channel-1 receives green pixel data in active display and CTL1 control signals in blank.

Channel-2 receives red pixel data in active display and CTL2, CTL3 control signals in blank.

actively switching. The TFP9431 monitors the state DE to determine link activity. SCDT can be tied externally
to PDO to power down the out put drivers when the link is inactive.

High: Active link
Low: Inactive link

dc specifications for IOH and IOL vs ST state.)
High : High drive strength

Low : Low drive strength

TFP9431 in test mode.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TFP9431
PanelBus DVI RECEIVER WITH TRIPLE DAC

SLDS122A – MARCH 2000 – REVISED JUNE 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

†

Supply voltage range, VCC, AVCC, OVCC, PVCC, DACVCC -0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, logic/analog signals -0.3 V to 4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating ambient temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range -65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package power dissipation/PowerPAD:Soldered (see Note 1) 4.3 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Not soldered (see Note 2) 2.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ESD Protection, all pins 2 KV Human Body Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JEDEC latchup (EIA/JESD78) 100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Specified with PowerPAD bond pad on the backside of the package soldered to a 2 oz. Cu plate PCB thermal plane. Specified

at maximum allowed operating temperature, 70°C.

2. PowerPAD bond pad on the backside of the package is not soldered to a thermal plane. Specified at maximum allowed operating
temperature, 70°C.

recommended operating conditions

MIN TYP MAX UNIT

Supply voltage, V
Pixel time, t
Single ended analog input termination resistance, R
Operating free-air temperature, T

†

t

pix

and 2t

pix

is the pixel time defined as the period of the RxC clock input. The period of the output clock, ODCK is equal to t

when in 2-pixel/clock mode.

pix

, AVCC, PVCC, OVCC, DACV

CC

†

A

CC

3 3.3 3.6 V

8.9 40 ns

t

50 Ω

0 25 70 °C

when in 1-pixel/clock mode

pix

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265