Texas Instruments SN74ABT651DBLE, SN74ABT651DBR, SN74ABT651DW, SN74ABT651DWR, SN74ABT651NT Datasheet

SN54ABT651, SN74ABT651

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS083E – JANUARY 1991 – REVISED APRIL 1998

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 500 mA Per
JESD 17

D

T ypical V
at V

D

High-Drive Outputs (–32-mA IOH,

= 5 V, TA = 25°C

CC

64-mA I

D

Multiplexed Real-Time and Stored Data

D

Inverting Data Paths

D

Package Options Include Plastic

(Output Ground Bounce) < 1 V

OLP

)

OL

Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, Ceramic Chip Carriers (FK), and
Plastic (NT) and Ceramic (JT) DIPs

description

These devices consist of bus-transceiver circuits,
D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the
data bus or from the internal storage registers.
Output-enable (OEAB and OEBA
provided to control the transceiver functions. The
select-control (SAB and SBA) inputs are provided
to select whether real-time or stored data is
transferred. A low input level selects real-time
data, and a high input level selects stored data.
Figure 1 illustrates the four fundamental
bus-management functions that can be
performed with the ’ABT651 devices.

) inputs are

SN74ABT651 . . . DB, DW, NT, OR PW PACKAGE

SN54ABT651 . . . JT PACKAGE

(TOP VIEW)

CLKAB

OEAB

GND

SN54ABT651 . . . FK PACKAGE

A1
A2
A3

NC

A4
A5
A6

NC – No internal connection

SAB

A1
A2
A3
A4
A5
A6
A7
A8

4

5
6
7
8
9
10
11

12

A7

1
2
3
4
5
6
7
8
9
10
11
12

(TOP VIEW)

OEAB

SAB

CLKAB

321

13 14

A8

GND

24
23
22
21
20
19
18
17
16
15
14
13

CC

NC

V

28 27 26

15 16 17

B8B7B6

NC

V

CC

CLKBA
SBA
OEBA
B1
B2
B3
B4
B5
B6
B7
B8

CLKBA

SAB

25
24
23
22
21
20
19

18

OEBA
B1
B2
NC
B3
B4
B5

Data on the A or B bus, or both, can be stored in the internal D flip-flops by low-to-high transitions at the
appropriate clock (CLKAB or CLKBA) inputs, regardless of the select- or enable-control pins. When SAB and
SBA are in the real-time transfer mode, it also is possible to store data without using the internal D-type flip-flops
by simultaneously enabling OEAB and OEBA

. In this configuration, each output reinforces its input. When all

the other data sources to the two sets of bus lines are at high impedance, each set remains at its last state.
To ensure the high-impedance state during power up or power down, OEBA

should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
(B to A). OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is
determined by the current-sourcing capability of the driver (A to B).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

SN54ABT651, SN74ABT651

OPERATION OR FUNCTION

OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS

SCBS083E – JANUARY 1991 – REVISED APRIL 1998

description (continued)

The SN54ABT651 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT651 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

INPUTS

OEAB OEBA CLKAB CLKBA SAB SBA A1–A8 B1–B8

L H H or L H or L X X Input Input Isolation
L H ↑↑X X Input Input Store A and B data
X H ↑ H or L X X Input Unspecified

H H ↑↑X

L X H or L ↑ X X Unspecified
L L ↑↑XX
L L X X X L Output Input Real-time B data to A bus

L L X H or L X H Output Input Stored B data to A bus
H H X X L X Input Output Real-time A data to B bus
H H H or L X H X Input Output Stored A data to B bus

H L H or L H or L H H Output Output

†

The data output functions may be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data input functions are always
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

‡

When select control is low, clocks can occur simultaneously if allowances are made for propagation delays from A to B (B to A) plus setup and
hold times. When select control is high, clocks must be staggered to load both registers.

‡

X Input Output Store A in both registers

‡

Output Input Store B in both registers

DATA I/O

†

†

Input Hold A, store B

Store A, hold B

Stored A data to B bus and

stored B

data to A bus

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SN54ABT651, SN74ABT651

OCTAL BUS TRANSCEIVERS AND REGISTERS

WITH 3-STATE OUTPUTS

SCBS083E – JANUARY 1991 – REVISED APRIL 1998

BUS A

3 21 1 23 2 22 1 23 2 22321

OEAB

OEBA

LL

CLKABXCLKBAXSABXSBA

REAL-TIME TRANSFER

BUS B TO BUS A

BUS B

OEAB OEBA

L

BUS A

HH

BUS B

CLKABXCLKBAXSABLSBA

X

REAL-TIME TRANSFER

BUS A TO BUS B

BUS A

3 21 23 2 22 3 21 1 2 22

OEAB

Pin numbers are for the DB, DW, JT, NT, and PW packages.

OEBA
X
L
L

H
X
H

STORAGE FROM A, B, OR A AND B

1

CLKAB CLKBAXSABXSBA

↑

XX

↑
↑↑

BUS B

X
X

X

X

Figure 1. Bus-Management Functions

BUS A

23

OEAB OEBA

H L H or L H H

TRANSFER STORED DATA TO A AND/OR B

CLKAB CLKBA SAB SBA

H or L

BUS B

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3