TEXAS INSTRUMENTS SN65LBC171, SN75LBC171 Technical data
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
D
Three Differential Transceivers in One
Package
D
Signaling Rates1 Up to 30 Mbps
D
Low Power and High Speed
D
Designed for TIA/EIA-485, TIA/EIA-422, ISO
8482, and ANSI X3.277 (HVD SCSI Fast–20)
Applications
D
Common-Mode Bus Voltage Range
–7 V to 12 V
D
ESD Protection on Bus Terminals
Exceeds 12 kV
D
Driver Output Current up to ±60 mA
D
Thermal Shutdown Protection
D
Driver Positive and Negative Current
Limiting
D
Power-Up, Power-Down Glitch-Free
Operation
D
Pin-Compatible With the SN75ALS171
D
Available in Shrink Small-Outline Package
description
The SN65LBC171 and SN75LBC171 are
monolithic integrated circuits designed for
bidirectional data communication on multipoint
bus-transmission lines. Potential applications
include serial or parallel data transmission, cabled
peripheral buses with twin axial, ribbon, or
twisted-pair cabling. These devices are suitable
for FAST–20 SCSI and can transmit or receive
data pulses as short as 25 ns, with skew less than
3 ns.
These devices combine three 3-state differential
line drivers and three differential input line
receivers, all of which operate from a single 5-V
power supply.
SN65LBC171DB (Marked as BL171)
SN75LBC171DB (Marked as LB171)
SN65LBC171DW (Marked as 65LBC171)
SN75LBC171DW (Marked as 75LBC171)
logic diagram
CDE
1DE
1D
RE
1R
2DE
2D
2R
3DE
3D
3R
1R
1DE
1D
GND
GND
2R
2DE
2D
3R
3DE
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1B
1A
RE
CDE
V
CC
2B
2A
3B
3A
3D
1A
1B
2A
2B
3A
3B
The driver differential outputs and the receiver differential inputs are connected internally to form three
differential input/output (I/O) bus ports that are designed to offer minimum loading to the bus whenever the driver
is disabled or V
= 0. These ports feature a wide common-mode voltage range making the device suitable for
CC
party-line applications over long cable runs.
The SN75LBC171 is characterized for operation over the temperature range of 0°C to 70°C. The SN65LBC171
is characterized for operation over the temperature range of –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2001, Texas Instruments Incorporated
1
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
AVAILABLE OPTIONS
T
A
PLASTIC SMALL-OUTLINE
(JEDEC MS-013)
0°C to 70°C SN75LBC171DW SN75LBC171DB
–40°C to 85°C SN65LBC171DW SN65LBC171DB
†
Add R suffix for taped and reel
Function Tables
EACH DRIVER
INPUT
D
H
L
OPEN
X
X
X
X
ENABLE
DE CDE
H
H
H
L
X
OPEN
X
OPEN
H
H
H
X
L
X
OUTPUTS
A
B
H
L
L
H
L
H
Z
Z
Z
Z
Z
Z
Z
Z
equivalent input and output schematic diagrams
D, DE,CDE INPUTS
V
CC
RE INPUT
{
PACKAGE
PLASTIC SHRINK SMALL-OUTLINE
(JEDEC MO-150)
EACH RECEIVER
DIFFERENTIAL INPUT
(VA–VB)
ENABLE
OUTPUT
RE
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ –0.2 V L L
XHZ
OPEN
LH
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), ? = indeterminate
V
CC
R OUTPUT
R
Input
Input
8 V
16 V
1 kΩ
100 kΩ
16 V
A INPUT
100 kΩ
18 kΩ
4 kΩ
4 kΩ
V
CC
100 kΩ
40 Ω
16 V
Output
Output
16 V
16 V
1 kΩ
8 V
B INPUT
18 kΩ
100 kΩ
4 kΩ
4 kΩ
A AND B OUTPUT
V
V
CC
CC
4 kΩ
18 kΩ
4 kΩ
Input
V
CC
16 V
Input
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DE, CDE, RE
V
Output current
mA
Operating free-air temperature, T
°C
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
absolute maximum ratings
Supply voltage, V
CC
†
(see Note 1) –0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any bus I/O terminal (steady state) –10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage input range, A and B, (transient pulse through 100 Ω, see Figure 12) –30 V to 30 V. . . . . . . . . . . . . .
Voltage range at any DE, RE
, or CDE terminal – 0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: Human body model (A, B, GND) (see Note 2) 12 kV. . . . . . . . . . . . . . . . . . . . . . . . . .
All pins 5 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged-device model (all pins) (see Note 3) 1 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Power Dissipation Rating Table
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114–A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
POWER DISSIPATION RATING TABLE
PACKAGE
DB 995 mW 8.0 mW/°C 635 mW 515 mW
DW 1480 mW 11.8 mW/°C 950 mW 770 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
‡
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
Voltage at any bus I/O terminal A, B –7 12 V
High-level input voltage, V
Low-level input voltage, V
Differential input voltage, V
p
p
CC
IH
IL
ID
p
A
A with respect to B –12 12 V
Driver –60 60
Receiver –8 8
SN75LBC171 0 70
SN65LBC171 –40 85
4.75 5 5.25 V
2 V
0 0.8
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN65LBC171, SN75LBC171
(SS)
‡
()
magnitude
‡
C
L
F
R
54 Ω
C
50 pF
See Figure 3
S
(HVD SCSI double-terminated load)
See Figure 5
ns
See Figure 6
ns
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
DRIVER SECTION
electrical characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
V
O
|V
OD
∆V
OD
V
OC(SS)
∆V
OC(SS)
I
I
I
O
I
OS
I
CC
†
All typical values are at VCC = 5 V and TA = 25°C.
‡
The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly
lower output signal into account in determining the maximum signal-transmission distance.
Input clamp voltage D, DE, CDE II = 18 mA –1.5 –0.7 V
Open-circuit output voltage (single-ended) A or B, No load 0 V
Steady-state differential output voltage
|
Change in differential output voltage
magnitude, | V
Steady-state common-mode output voltage
Change in steady-state common-mode
output voltage (V
Input current D, DE, CDE –100 100 µA
Output current with power off VCC = 0 V, VO = –7 V to 12 V –700 900 µA
Short-circuit output current VO = –7 V to 12 V, See Figure 7 –250 250 mA
Supply current (driver enabled) D at 0 V or VCC,
OD(H)
OC(H)
| – |V
– V
OD(L)
OC(L)
|
)
No load 3.8 4.3 V
RL = 54 Ω, See Figure 1 1 1.6 2.4 V
With common-mode loading, See Figure 2 1 1.6 2.4 V
–0.2 0.2 V
RL = 54 Ω,
= 50
p
See Figure 1
CDE, DE, RE at
VCC, No load
2 2.4 2.8 V
–0.2 0.2 V
14 20 mA
CC
CC
V
V
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
t
PHL
t
r
t
f
t
sk(p)
t
sk(o)
t
sk(pp)
t
PLH
t
PHL
t
r
t
f
t
sk(p)
t
sk(o)
t
sk(pp)
t
PZH
t
PHZ
t
PZL
t
PLZ
§
Output skew (t
¶
Part-to-part skew (t
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
Differential output propagation delay, low-to high 4 8.5 12
Differential output propagation delay, high-to-low 4 8.5 11
Differential output rise time
Differential output fall time
Pulse skew | (t
Output skew
Part-to-part skew
Differential output propagation delay, low-to high 3 7 10
Differential output propagation delay, high-to-low 3 7.5 10
Differential output rise time
Differential output fall time
Pulse skew | (t
Output skew
Part-to-part skew
Output enable time to high level
Output disable time from high level
Output enable time to low level
Output disable time from low level
) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
sk(o)
sk(pp)
– t
– t
PHL
PHL
) |
) |
PLH
§
¶
PLH
§
¶
) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
L
ee Figure 4,
=
,
L
-
=
,
3 7.5 11
3
7.5 11
1.5
3 7.5 12
3 7.5 12
1.5
2.5
15 25
18 25
10 25
17 25
ns
2
2
ns
3
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
IILine input current
Other input
V
mA
V
3 V to 3 V, See Figure 9
See Figure 10
ns
See Figure 11
ns
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
RECEIVER SECTION
electrical characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IT+
V
IT–
V
hys
V
OH
V
OL
I
I
R
I
I
CC
†
All typical values are at VCC = 5 V and TA = 25°C.
switching characteristics over recommended operating conditions
Positive-going differential input voltage threshold 0.2
Negative-going differential input voltage threshold –0.2
Hysteresis voltage (V
High-level output voltage VID = 200 mV, IOH = –8 mA, see Figure 10 4 4.7 V
Low-level output voltage VID = –200 mV , IOL = –8 mA, see Figure 10 0 0.2 0.4
p
Input current RE –100 100 µA
Input resistance A, B 12 kΩ
Supply current (receiver enabled) A, B, D open, RE, DE, and CDE at 0 V 16 mA
IT+
– V
) 40 mV
IT–
p
= 0
VI = 12 V 0.9
VI = –7 V –0.7
SN65LBC171, SN75LBC171
CC
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
PLH
t
PHL
t
r
t
f
t
PZH
t
PHZ
t
PZL
t
PLZ
t
sk(p)
t
sk(o)
t
sk(pp)
‡
Output skew (t
§
Part-to-part skew (t
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
Propagation delay time, low-to-high level output 7 16 ns
Propagation delay time, high-to-low level output
Receiver output rise time
Receiver output fall time 1.3 3 ns
Receiver output enable time to high level
Receiver output disable time from high level
Receiver output enable time to low level
Receiver output enable time to high level
Pulse skew (| ( t
Output skew
Part-to-part skew
) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
sk(o)
sk(pp)
– t
PLH
}
w
) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
|) 2 ns
PHL
= –
ID
7 16 ns
1.3 3 ns
26 40
40
29 40
40
1.5 ns
3 ns
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5
SN65LBC171, SN75LBC171
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS460A – NOVEMBER 2000 – REVISED FEBRUARY 2001
PARAMETER MEASUREMENT INFORMATION
I
I
0 V or 3 V
†
Includes probe and jig capacitance
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
I
O
27 Ω
V
I
O
V
O
OD
V
O
375 Ω
50 pF
{
27 Ω
V
OC
Input
V
OD
60 Ω
375 Ω
V
TEST
V
TEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
RL = 54 Ω
Signal
Generator
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes Probe and Jig Capacitance
Input
Output
{
t
PLH
50 Ω
1.5 V
10%
t
r
90%
1.5 V
90%
t
PHL
10%
t
f
CL = 50 pF
3 V
0 V
V
OD(H)
0 V
V
OD(L)
}
= –7 V to 12 V
V
OD
Figure 3. Driver Switching Test Circuit and Waveforms, 485-Loading
6
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