TEXAS INSTRUMENTS SN65HVD50, SN65HVD55, SN65HVD56, SN65HVD59 Technical data

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SN65HVD54

SN65HVD52

0.1

1

10

100

10 100 1000

Cable Length (meters)

Signalling Rate (Mbps)

SN65HVD56

SN65HVD58

SN65HVD50

SN65HVD53

SN65HVD51

SN65HVD55

SN65HVD57

SN65HVD59

HIGH OUTPUT FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS

SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59

SLLS666 – SEPTEMBER 2005

FEATURES

• 1/8 Unit-Load Option Available (Up to 256

Nodes on the Bus)

• Bus-Pin ESD Protection Exceeds 15 kV HBM

• Optional Driver Output Transition Times for

Signaling Rates

(1)

of 1 Mbps, 5 Mbps and 25

Mbps

• Low-Current Standby Mode < 1 µ A

• Glitch-Free Power-Up and Power-Down Bus

I/Os

• Bus Idle, Open, and Short Circuit Failsafe

• Meets or exceeds the requirements of ANSI

TIA/EIA-485-A and RS-422 Compatible

• 3.3-V Devices available, SN65HVD30-39

APPLICATIONS

• Utility Meters

• Chassis-to-Chassis Interconnects

• DTE/DCE Interfaces

• Industrial, Process, and Building Automation

• Point-of-Sale (POS) Terminals and Networks

The SN65HVD50, SN65HVD51, SN65HVD52,
SN65HVD56 and SN65HVD57 are fully enabled with
no external enabling pins. The SN65HVD56 and
SN65HVD57 implement receiver equalization
technology for improved performance in long distance
applications.

The SN65HVD53, SN65HVD54, SN65HVD55,
SN65HVD58, and SN65HVD59 have active-high
driver enables and active-low receiver enables. A
very low, less than 1 uA, standby current can be
achieved by disabling both the driver and receiver.
The SN65HVD58 and SN65HVD59 implement
receiver equalization technology for improved
performance in long distance applications.

All devices are characterized for operation from -40°
C to +85°.

DESCRIPTION

The SN65HVD5X devices are 3-state differential line
drivers and differential-input line receivers that
operate with a 5-V power supply. Each driver and
receiver has separate input and output pins for
full-duplex bus communication designs. They are
designed for balanced transmission lines and
interoperation with ANSI TIA/EIA-485A,
TIA/EIA-422-B, ITU-T v.11 and ISO 8482:1993
standard-compliant devices.

(1) The signaling rate of a line is the number of voltage

transitions that are made per second expressed in the units
bps (bits per second). to 1000 meters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

The SN65HVD56 and SN65HVD58 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates up to 20 Mbps at cable lengths up to 160
meters.

The SN65HVD57 and SN65HVD59 implement
receiver equalization technology for improved jitter
performance on differential bus applications with data
rates in the range of 1 to 5 Mbps at cable lengths up

Copyright © 2005, Texas Instruments Incorporated

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R

D

B

A

Z

Y

7

8

6

5

2

3

D P (TOP VIEW)ACKAGE

1

2

3

4

8

7

6

5

R

D

V

CC

B

A

Z

Y

GND

1

2

3

4

5

6

7

14

13

12

11

10

9

8

NC

R

RE

DE

D

GND

GND

V

CC

V

CC

A

B

Z

Y

NC

NC - No internal connection

SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59

SLLS666 – SEPTEMBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

SN65HVD50, SN65HVD51, SN65HVD52, SN65HVD56, SN65HVD53, SN65HVD54, SN65HVD55, SN65HVD58,

SN65HVD57 SN65HVD59

AVAILABLE OPTIONS

SIGNALING RECEIVER BASE

RATE EQUALIZATION PART NUMBER

25 Mbps 1/2 No No SN65HVD50 PREVIEW

5 Mbps 1/8 No No SN65HVD51 PREVIEW
1 Mbps 1/8 No No SN65HVD52 PREVIEW

25 Mbps 1/2 No Yes SN65HVD53 65HVD53

5 Mbps 1/8 No Yes SN65HVD54 65HVD54
1 Mbps 1/8 No Yes SN65HVD55 65HVD55

25 Mbps 1/2 Yes No SN65HVD56 PREVIEW

5 Mbps 1/8 Yes No SN65HVD57 PREVIEW

25 Mbps 1/2 Yes Yes SN65HVD58 PREVIEW

5 Mbps 1/8 Yes Yes SN65HVD59 PREVIEW

UNIT LOADS ENABLES SOIC MARKING

2

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SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59

SLLS666 – SEPTEMBER 2005

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

CC

V

I

I

O

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
(3) This tests survivability only and the output state of the receiver is not specified.

Supply voltage range –0.3 V to 6 V
Voltage range at any bus terminal (A, B, Y, Z) –9 V to 14 V
Voltage input, transient pulse through 100 Ω . See Figure 12 (A, B, Y, Z)
Voltage input range (D, DE, RE) -0.5 V to 7 V
Continuous total power dissipation Internally limited
Output current (receiver output only, R) 11 mA

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

PARAMETER MIN NOM MAX UNIT

V
VIor Voltage at any bus terminal (separately or common mode) –7

V
1/t

R
V
V
V

I

I

T

(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information regarding this specification.

Supply voltage 4.5 5.5

CC

IC

UI

SN65HVD50, SN65HVD53, SN65HVD56, SN65HVD58 25

Signaling rate SN65HVD51, SN65HVD54, SN65HVD57, SN65HVD59 5 Mbps

SN65HVD52, SN65HVD55 1

Differential load resistance 54 60 Ω

L

High-level input voltage D, DE, RE 2 V

IH

Low-level input voltage D, DE, RE 0 0.8 V

IL

Differential input voltage -12 12

ID

High-level output current mA

OH

Low-level output current mA

OL

(2)

Junction temperature –40 150 ° C

J

(1) (2)

(3)

(1)

Driver -60
Receiver –8
Driver 60
Receiver 8

UNIT

–50 to 50 V

V

12

CC

ELECTROSTATIC DISCHARGE PROTECTION

PARAMETER TEST CONDITIONS MIN TYP

Human body model Bus terminals and GND ± 16
Human body model
Charged-device-model

(1) All typical values at 25°C and with a 5-V supply.
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.

(2)

(3)

All pins ± 4 kV
All pins ± 1

(1)

MAX UNIT

3

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SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59

SLLS666 – SEPTEMBER 2005

DRIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

V

I(K)

|V

OD(SS)

∆ |V

OD(SS)

V

OD(RING)

V

OC(PP)

V

OC(SS)

∆ V

OC(SS)

I

or I

Z(Z)

I

or I

Z(S)

I

I

C

(OD)

(1) All typical values are at 25 ° C and with a 5-V supply.

Input clamp voltage II= –18 mA –1.5

| Steady-state differential output voltage

Change in magnitude of steady-state RL= 54 Ω , See Figure 1 and

| –0.2 0.2

differential output voltage between states Figure 2
Differential Output Voltage overshoot

and undershoot

HVD50, HVD53,

Peak-to-peak

HVD56, HVD58

common-mode HVD51, HVD54, See Figure 4
output voltage HVD57, HVD59

HVD52, HVD55 0.4

Steady-state common-mode
output voltage

Change in steady-state common-mode
output voltage

High-impedance state

Y(Z)

output current

HVD53, HVD54,
HVD55, HVD58,
HVD59

Short Circuit output Current mA

Y(S)

Input current D, DE 0 100 µA
Differential output capacitance 16 pF

(1)

IO= 0 4 V
RL= 54 Ω , See Figure 1 (RS-485) 1.7 2.6
RL= 100 Ω , See Figure 1 (RS-422) 2.4 3.2
V

= –7 V to 12 V, See Figure 2 1.6

test

RL= 54 Ω , CL= 50 pF, See

Figure 5 0.05 |V

See Figure 3 for definition

0.5

0.4

2.2 3.3

See Figure 4

–0.1 0.1

V

= 0 V, VZor VY= 12 V,

CC

Other input at 0 V
V

= 0 V, VZor VY= –7 V,

CC

Other input at 0 V
V

= 5 V or 0 V,

CC

DE = 0 V 90
VZor VY= 12 V

V

= 5 V or 0 V,

CC

DE = 0 V –10

Other input
at 0 V

–10

VZor VY= –7 V
VZor VY= –7 V –250 250
VZor VY= 12 V –250 250

V

= 0.4 sin (4E6 π t) + 0.5 V,

OD

DE at 0 V

Other input
at 0 V

MAX UNIT

CC

|

OD(SS)

V

90

µ A

4

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DRIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

t

PLH

t

PHL

t

r

t

f

t

sk(p)

t

sk(pp)

Propagation delay time,
low-to-high-level output

Propagation delay time,
high-to-low-level output

Differential output signal
rise time

Differential output signal fall
time

Pulse skew (|t

(2)

Part-to-part skew HVD51, HVD54, HVD57, HVD59 4 ns

- t

PHL

PLH

Propagation delay time,

t

PZH1

high-impedance-to-high- HVD54, HVD59 180 ns
level output

Propagation delay time,

t

PHZ

high-level-to-high- HVD54, HVD59 40 ns
impedance output

Propagation delay time,

t

PZL1

high-impedance-to-low-level HVD54, HVD59 200 ns
output

Propagation delay time,

t

PLZ

t

PZH2

t

PZL2

low-level-to-high-impedance HVD54, HVD59 70 ns
output

Propagation delay time, standby-to-high-level output 3300 ns

Propagation delay time, standby-to-low-level output 3300 ns

(1) All typical values are at 25°C and with a 5-V supply.
(2) t

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

sk(pp)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

HVD50, HVD53, HVD56, HVD58 4 8 12
HVD51, HVD54, HVD57, HVD59 20 29 46 ns
HVD52, HVD55 90 143 230
HVD50, HVD53, HVD56, HVD58 4 8 12
HVD51, HVD54, HVD57, HVD59 20 30 46 ns
HVD52, HVD55 90 143 230
HVD50, HVD53, HVD56, HVD58 3 6 12
HVD51, HVD54, HVD57, HVD59 25 34 60 ns
HVD52, HVD55 130 197 300
HVD50, HVD53, HVD56, HVD58 3 6 11

RL= 54 Ω , CL= 50 pF,
See Figure 5

HVD51, HVD54, HVD57, HVD59 25 33 60 ns
HVD52, HVD55 130 192 300
HVD50, HVD53, HVD56, HVD58 2

|) HVD51, HVD54, HVD57, HVD59 2 ns

HVD52, HVD55 8
HVD50, HVD53, HVD56, HVD58 1

HVD52, HVD55 22
HVD53, HVD58 30

HVD55 380
HVD53, HVD58 16

RL= 110 Ω , RE at 0 V,
See Figure 6
D = 3 V and S1 = Y,
D = 0 V and S1 = Z

HVD55 110
HVD53, HVD58 23

HVD55 420
HVD53, HVD58 19

RL= 110 Ω , RE at 0 V,
See Figure 7
D = 3 V and S1 = Z,
D = 0 V and S1 = Y

HVD55 160

RL= 110 Ω , RE at 3 V,
See Figure 6
D = 3 V and S1 = Y,
D = 0 V and S1 = Z

RL= 110 Ω , RE at 3 V,
See Figure 7
D = 3 V and S1 = Z,
D = 0 V and S1 = Y

SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59

SLLS666 – SEPTEMBER 2005

(1)

MAX UNIT

5

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SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59

SLLS666 – SEPTEMBER 2005

RECEIVER ELECTRICAL CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

V

IT+

V

IT-

V

hys

V

IK

V

O

I

O(Z)

IAor I

I

IH

C

ID

I

CC

(1) All typical values are at 25°C and with a 5-V supply.

Positive-going differential input
threshold voltage

Negative-going differential input
threshold voltage

Hysteresis voltage (V

- V

IT+

IT-

IO= –8 mA –0.02

IO= 8 mA –0.20

) 50 mV

Enable-input clamp voltage II= –18 mA –1.5 V

Output voltage V

High-impedance-state output
current

HVD50,
HVD53, Other input
HVD56, at 0 V
HVD58

Bus input current

B

HVD51, VAor VB= 12 V 0.05 0.10
HVD52,
HVD54, Other input
HVD55, at 0 V
HVD57,
HVD59

Input current, RE

VID= 200 mV, IO= –8 mA, See Figure 8 4.0
VID= –200 mV, IO= 8 mA, See Figure 8 0.3

VO= 0 or VCCRE at V
VAor VB= 12 V 0.19 0.3

VAor VB= 12 V, V
VAor VB= -7 V –0.35 –0.19
VAor VB= -7 V, V

VAor VB= 12 V, V
VAor VB= -7 V –0.10 –0.05

VAor VB= -7 V, V
VIH= 2 V –60 µA

VIL= 0.8 V –60 µA

Differential input capacitance VID= 0.4 sin (4E6 π t) + 0.5 V, DE at 0 V 16 pF

HVD50,
HVD51, 8.0
HVD52

D at 0 V or V

HVD56,
HVD57

HVD53 2.3
HVD54, RE at 0 V, D at 0 V or VCC, DE at 0 V,

HVD55 No load (Receiver enabled and
HVD58,

driver disabled)
HVD59
HVD53,

HVD54, RE at VCC, D at VCC, DE at 0 V,

Supply current

HVD55, No load (Receiver disabled and 0.08 1 µA
HVD58, driver disabled)
HVD59

HVD53 2.7
HVD54,

HVD55
HVD58 4.3

RE at 0 V, D at 0 V or VCC, DE at VCC,

No load (Receiver enabled and

driver enabled)
HVD59 9.7

HVD53 2.3
HVD54,

HVD55
HVD58 3.2

RE at VCC, D at 0 V or VCC, DE at V

No load (Receiver disabled and

driver enabled)
HVD59 8.5

CC

= 0 V 0.24 0.4

CC

= 0 V –0.25 –0.14

CC

= 0 V 0.06 0.10

CC

= 0 V –0.10 –0.03

CC

and No Load

CC

CC

(1)

MAX UNIT

–1 1 µA

9.5

2.9

4.5

8.0

7.7

V

mA

mA

mA

mA

6

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RECEIVER SWITCHING CHARACTERISTICS

over recommended operating conditions unless otherwise noted

PARAMETER TEST CONDITIONS MIN TYP

t

PLH

t

PHL

t

sk(p)

t

sk(pp)

t

r

t

f

t

PHZ

t

PZH1

t

PZH2

t

PLZ

t

PZL1

t

PZL2

Propagation delay time,
low-to-high-level output

Propagation delay time,
high-to-low-level output

Pulse skew (|t

(2)

Part-to-part skew HVD51, HVD54, HVD57, HVD59 6

- t

PHL

|)

PLH

Output signal rise time 2.3 4
Output signal fall time 2.4 4
Output disable time from high level 17
Output enable time to high level 10

Propagation delay time, standby-to-high-level output 3300
Output disable time from low level 13

Output enable time to low level 10
Propagation delay time, standby-to-low-level output 3300

(1) All typical values are at 25°C and with a 5-V supply
(2) .t

is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices

sk(pp)

operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

HVD50, HVD53, HVD56, HVD58 24 40
HVD51, HVD52, HVD54, HVD55,

HVD57, HVD59
HVD50, HVD53, HVD56, HVD58 26 35
HVD51, HVD52, HVD54, HVD55,

HVD57, HVD59
HVD50, HVD53, HVD56, HVD57,

HVD58, HVD59
HVD51, HVD54, HVD52, HVD55 7

VID= -1.5 V to 1.5 V,
CL= 15 pF,
See Figure 9

HVD50, HVD53, HVD56, HVD58 5

HVD52, HVD55 6

DE at 3 V, CL= 15 pF
See Figure 10

DE at 0 V, CL= 15 pF
See Figure 10

DE at 3 V, CL= 15 pF
See Figure 11

DE at 0 V, CL= 15 pF
See Figure 11

SN65HVD50-SN65HVD55
SN65HVD56-SN65HVD59

SLLS666 – SEPTEMBER 2005

(1)

MAX UNIT

43 55

47 60

5

ns

7