Texas Instruments PCI2060ZHK, PCI2060 Datasheet
PCI2060 Asynchronous PCI-to-PCI
Bridge
Data Manual
Literature Number: SCPS096A
April 2005
Printed on Recycled Pape
r
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Copyright 2005, Texas Instruments Incorporated
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April 2005 SCPS096A
Contents
Section Page
1 PCI2060 Features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Description 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Related Documents 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Trademarks 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Document Conventions 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Ordering Information 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Terminal Assignments 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Terminal Descriptions 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Principles of Operation 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Types of Transactions 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Decoding Options 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Configuration Cycles 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.1 Type 0 Configuration Transaction 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.2 Type 1 to Type 0 Translation 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.3 Type 1 to Type 1 Forwarding 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3.4 Special Cycle 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Write Transaction 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 Posted Write Transaction 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 Delayed Write Transaction 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 Discard Timer 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.4 Write Transaction Address Boundaries 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.5 Fast Back-to-Back Write Transactions 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.6 Write Combining 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Read Transactions 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 Prefetchable Read Transactions 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Prefetch Optimization 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3 Nonprefetchable Read Transactions 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Delayed Read Transaction 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 Discard Timer 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Transaction Termination 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Termination Initiated by the Master 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Termination Initiated by the Target 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Bus Arbitrations 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 Primary Bus Arbitration 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.2 Internal Secondary Bus Arbitration 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 External Secondary Bus Arbitration 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Parity Error Handling 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Address Parity Error 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Data Parity Error 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 System Error Handling 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Clocks 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10.1 Secondary Bus Clock Behavior 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Interrupt Routing 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Mode Selection 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.1 CompactPCI Hot-Swap Support 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12.2 PCI Power Management 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
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3.13 JTAG Support 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.1 Test Port Instructions 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.2 Instruction Register 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.3 1-Bit Bypass Register 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.4 Boundary Scan Register 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 GPIO Interface 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1 Secondary Clock Mask 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.2 Transaction Forwarding Control 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Configuration Header Space 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Vendor ID Register (00h) 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Device ID Register (02h) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Primary Command Register (04h) 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Primary Status Register (06h) 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Revision ID Register (08h) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Programming Interface Register (09h) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Subclass Code Register (0Ah) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Base Class Code Register (0Bh) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Cache Line Size Register (0Ch) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Primary Latency Timer Register (0Dh) 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 Header Type Register (0Eh) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 BIST Register (0Fh) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Primary Bus Number Register (18h) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Bus Number Register (19h) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Subordinate Bus Number Register (1Ah) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Secondary Latency Timer Register (1Bh) 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 I/O Base Address Register (1Ch) 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 I/O Limit Address Register (1Dh) 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Secondary Status Register (1Eh) 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Base Address Register (20h) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 Memory Limit Address Register (22h) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 Prefetchable Memory Base Address Register (24h) 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Prefetchable Memory Limit Address Register (26h) 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Prefetchable Memory Base Address Upper 32-Bit Register (28h) 45 . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Prefetchable Memory Limit Address Upper 32-Bit Register (2Ch) 45 . . . . . . . . . . . . . . . . . . . . . . . .
4.26 I/O Base-Address Upper 16-Bit Register (30h) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 I/O Limit-Address Upper 16-Bit Register (32h) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 Capabilities Pointer Register (34h) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.29 Interrupt Line Register (3Ch) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 Interrupt Pin Register (3Dh) 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Bridge Control Register (3Eh) 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Extension Registers 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Chip Control Register (40h) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Extended Diagnostic Register (41h) 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Arbiter Control Register (42h) 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 P_SERR Event Disable Register (64h) 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 GPIO Output Data Register (65h) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 GPIO Output Enable Register (66h) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 GPIO Input Data Register (67h) 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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5.8 Secondary Clock Control Register (68h) 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 P_SERR Status Register (6Ah) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 Capability ID Register (DCh) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 Next Item Pointer Register (DDh) 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Power-Management Capabilities Register (DEh) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13 Power-Management Control/Status Register (E0h) 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.14 Power-Management Bridge-Support Extension Register (E2h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15 Power-Management Data Register (E3h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16 Hot-Swap Capability ID Register (E4h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.17 Hot-Swap Next-Item Pointer Register (E5h) 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.18 Hot-Swap Control and Status Register (E6h) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.19 TI Diagnostic Register (F0h) 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Electrical Characteristics 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Absolute Maximum Ratings Over Operating Temperature Ranges † 59 . . . . . . . . . . . . . . . . . . . . .
6.2 Recommended Operating Conditions (see Note 3) 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Electrical Characteristics Over Recommended Operating Conditions 61 . . . . . . . . . . . . . . . . . . . .
6.4 66-MHz PCI Clock Signal AC Parameters 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 66-MHz PCI Signal Timing 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Parameter Measurement Information 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7 PCI Bus Parameter Measurement Information 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Mechanical Data 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
vi
April 2005SCPS096A
List of Figures
Figure Page
2−1 PCI2060 GHK-Package Terminal Diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 System Block Diagram 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 Secondary Clock Block Diagram 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Clock Mask Read Timing After Reset 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 PCI Clock Signal AC Parameter Measurements 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 Load Circuit and Voltage Waveforms 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 RSTIN Timing Waveforms 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
April 2005 SCPS096A
List of Tables
Table Page
2−1 257-Terminal GHK Signal Names Sorted by Terminal Number 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 257-Terminal GHK Signal Names Sorted Alphabetically 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−3 PCI Primary Bus Terminals 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−4 PCI Primary Bus Address and Data Terminals 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 PCI Primary Bus Control Terminals 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 PCI Secondary Bus System Terminals 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 PCI Secondary Bus Address and Data Terminals 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 PCI Secondary Bus Control Terminals 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Miscellaneous Terminals 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 JTAG Terminals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 Power Supply Terminals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 No Connect Terminals 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 PCI2060 PCI Transactions 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 PCI AD31−AD0 During Address Phase of a Type 0 Configuration Type 17 . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 PCI AD31−AD0 During Address Phase of a Type 1 Configuration Type 17 . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Device Number to IDSEL S_AD Pin Mapping 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Write Transaction Forwarding 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Write Transaction Disconnect Address Boundaries 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Read Behavior 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 Read Connect Threshold Level 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 CONFIG66, P_M66ENA, and S_M66ENA Configuration 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 SEC_ASYNC_SEL and SEC_ASYNC_RATE Configuration 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 CONFIG66, P_M66ENA, S_M66ENA, SEC_ASYNC_SEL, and SEC_ASYNC_RATE Configuration 28
3−12 Interrupt Routing Scheme 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 Mode Selections 29 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 JTAG Instructions and Op Codes 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Boundary Scan Terminal Order 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 Clock Mask Data Format 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 PCI Configuration Header Space 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Primary Command Register 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Primary Status Register 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 I/O Base Register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 I/O Limit Address Register 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Secondary Status Register 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 Memory Base Address Register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Memory Limit Address Register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 Prefetchable Memory Base Address Register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 Prefetchable Memory Limit Address Register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Prefetchable Memory Base Address Upper 32-Bit Register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 Prefetchable Memory Limit Address Upper 32-Bit Register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 I/O Base-Address Upper 16-Bit Register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 I/O Limit-Address Upper 16-Bit Register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 Bridge Control Register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 Chip Control Register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Extended Diagnostic Register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3 Arbiter Control Register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 P_SERR Event Disable Register 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
viii
April 2005SCPS096A
Table Page
5−5 GPIO Output Data Register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−6 GPIO Output Enable Register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7 GPIO Input Data Register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8 Secondary Clock Control Register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−9 P_SERR Status Register 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10 Power-Management Capabilities Register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 Power-Management Control/Status Register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−12 Power-Management Bridge-Support Extension Register 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−13 Hot-Swap Control and Status Register (E6h) 57 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−14 TI Diagnostic Register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Features
1
April 2005 SCPS096A
1 PCI2060 Features
D Fully Supports PCI Local Bus Specification,
Revision 2.3
D Fully Supports PCI-to-PCI Bridge
Specification, Revision 1.1
D Fully Supports Advanced Configuration
Power Interface (ACPI) Specification
D Architecture Configurable for PCI Bus
Power Management Interface Specification,
Revision 1.0 and Revision 1.1
D Two 32-Bit, 66-MHz Asynchronous PCI
Buses
D 1.8-V Core Logic with Universal PCI
Interface Compatible with 3.3-V and 5-V PCI
Signaling Environments
D Provides Concurrent Primary and
Secondary Bus Operations
D Independent Read and Write Buffers for
Each Direction
D Burst Data Transfers With Pipeline
Architecture To Maximize Data Throughput
In Both Directions
D Up To Three Delayed Transactions For All
PCI Configuration, I/O, and Memory Read
Commands In Both Directions
D Provides 10 Secondary PCI Bus Clock
Outputs
D Provides Internal Two-Tier Arbitration For
Up To Nine Secondary Bus Masters
D Provides External Arbitration Option
D Provides CompactPCI
TM
Hot-Swap
Functionality
D Provides a 4-Terminal General-Purpose I/O
Interface
D Provides an IEEE Standard 1149.1 Joint
Test Action Group (JTAG) Interface
D Packaged in 257-Terminal PBGA Package
T able 1−1.
Figure 1−1.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
Introduction
2
April 2005SCPS096A
2 Introduction
2.1 Description
The Texas Instruments PCI2060 is a 32-bit, asynchronous, PCI-to-PCI bridge that is fully compliant with the
PCI Local Bus Specification, Revision 2.3 and the PCI-to-PCI Bridge Specification, Revision 1.1. The PCI2060
bridge makes it possible for the primary and secondary bus clocks to be completely asynchronous and
supports the PCI clock frequency up to 66 MHz.
The PCI2060 bridge is architecture-configurable for the PCI Bus Power Interface Specification. It can be
configured to support either revision 1.0 or revision 1.1. Power conservation is made possible by using 1.8-V
core logic with a universal PCI interface compatible with 3.3-V and 5-V PCI signaling environments.
The PCI2060 bridge allows the primary and secondary buses to operate concurrently. It provides independent
read and write buffers for each direction and utilizes pipeline architecture for burst data transfer.
The PCI2060 bridge makes it possible to overcome the electrical loading limit of ten devices per PCI bus and
one PCI device per expansion slot by creating hierarchical buses. Each PCI2060 bridge that is added to the
system creates a new PCI bus. The PCI2060 bridge provides a two-tier internal arbitration for up to nine
secondary bus masters and may be implemented with an external arbiter.
The PCI2060 bridge provides CompactPCI hot-swap support that is compliant with the PICMG CompactPCI
Hot-Swap Specification, Revision 1.0.
2.2 Related Documents
• Advanced Configuration and Power Interface (ACPI) Specification, Revision 2.0
• PCI Local Bus Specification, Revision 2.3
• PCI-to-PCI Bridge Specification, Revision 1.1
• PCI Bus Power Management Interface Specification, Revision 1.1
• PICMG CompactPCI Hot-Swap Specification, Revision 1.0
• IEEE Standard Test Access Port and Boundary-Scan Architecture
2.3 Trademarks
• CompactPCI is a trademark of PICMG – PCI Industrial Computer Manufacturers Group, Inc.
• Intel is a trademark of Intel Corporation.
• TI and MicroStar BGA are trademarks of Texas Instruments
• Other trademarks are the property of their respective owners
2.4 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are
listed below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary
field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a
12-bit hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number are
assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, P_RST
), then this indicates the
logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. RSVD indicates that the referenced item is reserved.
Introduction
3
April 2005 SCPS096A
2.5 Ordering Information
ORDERING NUMBER VOLTAGE TEMPERATURE PACKAGE
PCI2060 3.3-V, 5-V tolerant I/Os 00C to 700C 257-terminal GHK
PCI2060I 3.3-V, 5-V tolerant I/Os −400C to 850C 257-terminal GHK
2.6 Terminal Assignments
The PCI2060 bridge is packaged in a 257-terminal GHK MicroStar BGATM. Figure 2−1 is a GHK-package
terminal diagram.
Table 2−1 lists the terminal assignments in terminal-number order with corresponding signal names for the
GHK package. Table 2−2 lists the terminal assignments arranged in alphanumerical order by signal name with
corresponding terminal numbers for the GHK package.
Terminal E5 on the GHK package is an identification ball used for device orientation.
7
J
B
A
1
D
C
E
G
F
H
2436
5
T
K
M
L
P
N
R
W
U
V
128910
11
15
1413161718
19
Bottom View
Figure 2−1. PCI2060 GHK-Package Terminal Diagram
Introduction
4
April 2005SCPS096A
Table 2−1. 257-Terminal GHK Signal Names Sorted by Terminal Number
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
A2 NC C8 V
CC
F11 S_FRAME K14 TMS
A3 V
CC
C9 S_AD18 F12 S_C/BE1 K15 V
CC
A4 S_AD31 C10 NC F13 GND K17 TDO
A5 S_AD28 C11 S_IRDY F14 S_AD9 K18 TDI
A6 S_AD25 C12 S_LOCK F15 S_AD10 K19 NC
A7 GND C13 S_PAR F17 S_AD8 L1 S_CLKOUT0
A8 S_AD20 C14 V
CC
F18 GND L2 S_CLKOUT1
A9 V
CC
C15 GND F19 S_AD7 L3 NC
A10 S_C/BE2 C16 NC G1 S_GNT3 L5 S_CLKOUT2
A11 S_DEVSEL C17 NC G2 S_GNT2 L6 GND
A12 GND C18 NC G3 GND L14 HSLED
A13 V
CC
C19 NC G5 S_REQ8 L15 HSENUM
A14 GND D1 NC G6 S_REQ3 L17 MASK_IN
A15 S_AD13 D2 V
CC
G14 S_AD6 L18 CONFIG66
A16 V
CC
D3 NC G15 S_C/BE0 L19 P_VIO
A17 NC D17 NC G17 V
CC
M1 S_CLKOUT3
A18 NC D18 SEC_ASYNC_RATE G18 S_AD5 M2 V
CC
B1 NC D19 GND G19 S_AD4 M3 S_CLKOUT4
B2 NC E1 S_REQ5 H1 S_GNT7 M5 GND
B3 NC E2 S_REQ4 H2 S_GNT6 M6 S_CLKOUT5
B4 S_REQ0 E3 S_REQ1 H3 S_GNT5 M14 P_AD4
B5 S_AD29 E5 NC H5 S_GNT4 M15 V
CC
B6 S_AD26 E6 S_AD30 H6 S_GNT1 M17 P_AD1
B7 S_C/BE3 E7 GND H14 S_AD3 M18 P_AD0
B8 S_AD21 E8 S_AD23 H15 GND M19 GND
B9 NC E9 GND H17 S_AD2 N1 S_CLKOUT6
B10 GND E10 S_AD16 H18 V
CC
N2 S_CLKOUT7
B11 S_TRDY E11 V
CC
H19 S_AD1 N3 V
CC
B12 S_STOP E12 S_PERR J1 S_GNT8 N5 BPCCE
B13 S_SERR E13 S_AD15 J2 GND N6 S_CLKOUT8
B14 S_AD14 E14 S_AD11 J3 S_CLK N14 P_AD8
B15 S_AD12 E17 MS0 J5 S_RST N15 V
CC
B16 NC E18 S_M66ENA J6 S_CFN N17 GND
B17 NC E19 V
CC
J14 GND N18 P_AD3
B18 NC F1 S_GNT0 J15 S_AD0 N19 P_AD2
B19 NC F2 S_REQ7 J17 S_VIO P1 S_CLKOUT9
C1 SEC_ASYNC_CLK F3 S_REQ6 J18 TRST P2 P_RST
C2 NC F5 S_REQ2 J19 TCK P3 P_CLK
C3 NC F6 V
CC
K1 GPIO3/HSSWITCH P5 GND
C4 SEC_ASYNC_SEL F7 V
CC
K2 GPIO2 P6 P_REQ
C5 GND F8 S_AD22 K3 V
CC
P7 V
CC
C6 S_AD27 F9 S_AD19 K5 GPIO1 P8 V
CC
C7 S_AD24 F10 S_AD17 K6 GPIO0 P9 P_AD18
Introduction
5
April 2005 SCPS096A
Table 2−1. 257-Terminal GHK Signal Names Sorted by Terminal Number (Continued)
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
P10 P_C/BE2 R18 P_C/BE0 U15 P_AD10 V18 NC
P11 P_TRDY R19 GND U16 NC V19 NC
P12 P_LOCK T1 P_AD30 U17 NC W2 NC
P13 P_C/BE1 T2 V
CC
U18 NC W3 NC
P14 P_AD12 T3 NC U19 NC W4 V
CC
P15 V
CC
T17 NC V1 NC W5 P_AD28
P17 P_AD7 T18 V
CC
V2 NC W6 P_AD25
P18 P_AD6 T19 MS1 V3 NC W7 P_IDSEL
P19 P_AD5 U1 GND V4 NC W8 V
CC
R1 P_GNT U2 NC V5 NC W9 P_AD21
R2 NC U3 NC V6 GND W10 V
CC
R3 P_AD31 U4 NC V7 P_C/BE3 W11 P_FRAME
R6 P_AD29 U5 GND V8 P_AD22 W12 P_STOP
R7 P_AD26 U6 P_AD27 V9 P_AD20 W13 P_SERR
R8 GND U7 P_AD24 V10 P_AD17 W14 P_AD15
R9 P_AD19 U8 P_AD23 V11 V
CC
W15 V
CC
R10 GND U9 GND V12 NC W16 P_M66ENA
R11 P_DEVSEL U10 P_AD16 V13 P_PAR W17 GND
R12 P_PERR U11 P_IRDY V14 GND W18 NC
R13 P_AD14 U12 GND V15 P_AD11
R14 GND U13 V
CC
V16 V
CC
R17 P_AD9 U14 P_AD13 V17 NC
Introduction
6
April 2005SCPS096A
Table 2−2. 257-Terminal GHK Signal Names Sorted Alphabetically
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
BPCCE N5 NC A17 NC W18 P_IRDY U11
CONFIG66 L18 NC A18 NC W3 P_LOCK P12
GND A7 NC B1 P_AD0 M18 P_M66ENA W16
GND A12 NC B2 P_AD1 M17 P_PAR V13
GND A14 NC B3 P_AD2 N19 P_PERR R12
GND B10 NC B9 P_AD3 N18 P_REQ P6
GND C5 NC B16 P_AD4 M14 P_RST P2
GND C15 NC B17 P_AD5 P19 P_SERR W13
GND D19 NC B18 P_AD6 P18 P_STOP W12
GND E7 NC B19 P_AD7 P17 P_TRDY P11
GND E9 NC C2 P_AD8 N14 P_VIO L19
GND F13 NC C3 P_AD9 R17 S_AD0 J15
GND F18 NC C10 P_AD10 U15 S_AD1 H19
GND G3 NC C16 P_AD11 V15 S_AD2 H17
GND H15 NC C17 P_AD12 P14 S_AD3 H14
GND J2 NC C18 P_AD13 U14 S_AD4 G19
GND J14 NC C19 P_AD14 R13 S_AD5 G18
GND L6 NC D1 P_AD15 W14 S_AD6 G14
GND M5 NC D3 P_AD16 U10 S_AD7 F19
GND M19 NC D17 P_AD17 V10 S_AD8 F17
GND N17 NC E5 P_AD18 P9 S_AD9 F14
GND P5 NC K19 P_AD19 R9 S_AD10 F15
GND R8 NC L3 P_AD20 V9 S_AD11 E14
GND R10 NC R2 P_AD21 W9 S_AD12 B15
GND R14 NC T3 P_AD22 V8 S_AD13 A15
GND R19 NC T17 P_AD23 U8 S_AD14 B14
GND U1 NC U2 P_AD24 U7 S_AD15 E13
GND U5 NC U3 P_AD25 W6 S_AD16 E10
GND U9 NC U4 P_AD26 R7 S_AD17 F10
GND U12 NC U16 P_AD27 U6 S_AD18 C9
GND V6 NC U17 P_AD28 W5 S_AD19 F9
GND V14 NC U18 P_AD29 R6 S_AD20 A8
GND W17 NC U19 P_AD30 T1 S_AD21 B8
GPIO0 K6 NC V1 P_AD31 R3 S_AD22 F8
GPIO1 K5 NC V2 P_CLK P3 S_AD23 E8
GPIO2 K2 NC V3 P_C/BE0 R18 S_AD24 C7
GPIO3/HSSWITCH K1 NC V4 P_C/BE1 P13 S_AD25 A6
HSENUM L15 NC V5 P_C/BE2 P10 S_AD26 B6
HSLED L14 NC V12 P_C/BE3 V7 S_AD27 C6
MASK_IN L17 NC V17 P_DEVSEL R11 S_AD28 A5
MS0 E17 NC V18 P_FRAME W11 S_AD29 B5
MS1 T19 NC V19 P_GNT R1 S_AD30 E6
NC A2 NC W2 P_IDSEL W7 S_AD31 A4
Introduction
7
April 2005 SCPS096A
Table 2−2. 257-Terminal GHK Signal Names Sorted Alphabetically (Continued)
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
SIGNAL NAME
GHK
NUMBER
S_CFN J6 S_GNT1 H6 S_RST J5 V
CC
H18
S_CLK J3 S_GNT2 G2 S_SERR B13 V
CC
K3
S_CLKOUT0 L1 S_GNT3 G1 S_STOP B12 V
CC
K15
S_CLKOUT1 L2 S_GNT4 H5 S_TRDY B11 V
CC
M2
S_CLKOUT2 L5 S_GNT5 H3 S_VIO J17 V
CC
M15
S_CLKOUT3 M1 S_GNT6 H2 TCK J19 V
CC
N3
S_CLKOUT4 M3 S_GNT7 H1 TDI K18 V
CC
N15
S_CLKOUT5 M6 S_GNT8 J1 TDO K17 V
CC
P7
S_CLKOUT6 N1 S_IRDY C11 TMS K14 V
CC
P8
S_CLKOUT7 N2 S_LOCK C12 TRST J18 V
CC
P15
S_CLKOUT8 N6 S_M66ENA E18 V
CC
A3 V
CC
T2
S_CLKOUT9 P1 S_PAR C13 V
CC
A9 V
CC
T18
S_C/BE0 G15 S_PERR E12 V
CC
A13 V
CC
U13
S_C/BE1 F12 S_REQ0 B4 V
CC
A16 V
CC
V11
S_C/BE2 A10 S_REQ1 E3 V
CC
C8 V
CC
V16
S_C/BE3 B7 S_REQ2 F5 V
CC
C14 V
CC
W4
SEC_ASYNC_CLK C1 S_REQ3 G6 V
CC
D2 V
CC
W8
SEC_ASYNC_RATE D18 S_REQ4 E2 V
CC
E11 V
CC
W10
SEC_ASYNC_SEL C4 S_REQ5 E1 V
CC
E19 V
CC
W15
S_DEVSEL A11 S_REQ6 F3 V
CC
F6
S_FRAME F11 S_REQ7 F2 V
CC
F7
S_GNT0 F1 S_REQ8 G5 V
CC
G17
2.7 Terminal Descriptions
Table 2−3 through Table 2−12 give a description of the terminals. These terminals are grouped in tables by
functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.
Table 2−3. PCI Primary Bus Terminals
TERMINAL
NAME
GHK
NUMBER
I/O DESCRIPTION
P_CLK P3 I
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI
signals are sampled at the rising edge of P_CLK.
P_RST P2 I
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to place all output buffers
in a high-impedance state and to reset all internal registers. When asserted, the secondary interface is driven
low and the device is completely nonfunctional. After P_RST is deasserted, the bridge is in its default state.
Introduction
8
April 2005SCPS096A
Table 2−4. PCI Primary Bus Address and Data Terminals
TERMINAL
NAME
GHK
NUMBER
I/O DESCRIPTION
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
P_AD8
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
R3
T1
R6
W5
U6
R7
W6
U7
U8
V8
W9
V9
R9
P9
V10
U10
W14
R13
U14
P14
V15
U15
R17
N14
P17
P18
P19
M14
N18
N19
M17
M18
I/O
Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, P_AD31 through P_AD0 contain
a 32-bit address or other destination information. During the data phase, P_AD31 through P_AD0 contain
data.
P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
V7
P10
P13
R18
I/O
Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, P_C/BE3
through P_C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable determines
which byte paths of the full 32-bit data bus carry meaningful data. P_C/BE0 applies to byte 0 (P_AD7
through P_AD0), P_C/BE1
applies to byte 1 (P_AD15 through P_AD8), P_C/BE2 applies to byte 2
(P_AD23 through P_AD16), and P_C/BE3
applies to byte 3 (P_AD31 through P_AD24).
Introduction
9
April 2005 SCPS096A
Table 2−5. PCI Primary Bus Control Terminals
TERMINAL
NAME
GHK
NUMBER
I/O DESCRIPTION
P_DEVSEL R11 I/O
Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As a
PCI master on the primary bus, the bridge monitors P_DEVSEL
until a target responds. If no target
responds before the time-out occurs, then the bridge terminates the cycle with a master abort.
P_FRAME W11 I/O
Primary cycle frame. P_FRAME is driven by the master of a primary bus cycle. P_FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When P_FRAME
is deasserted, the primary bus transaction is in the final data phase.
P_GNT R1 I
Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access
to the primary PCI bus after the current data transaction has completed. P_GNT
may or may not follow a
primary bus request, depending on the primary bus-arbitration algorithm.
P_IDSEL W7 I
Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses.
P_IDSEL can be connected to 1 of the upper 24 PCI address lines on the primary PCI bus.
Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space
of the bridge can only be accessed from the primary bus.
P_IRDY U11 I/O
Primary initiator ready. P_IRDY indicates the ability of the primary bus master to complete the current
data phase of the transaction. A data phase is completed on a rising edge of P_CLK where both
P_IRDY and P_TRDY are asserted. Until both P_IRDY and P_TRDY are sample-asserted, wait states
are inserted.
P_LOCK P12 I/O Primary PCI bus lock. P_LOCK locks the primary bus and gains exclusive access as a bus master.
P_PAR V13 I/O
Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the
P_AD and P_C/BE
buses. As a bus master during PCI write cycles, the bridge outputs this parity
indicator with a one P_CLK delay. As a target during PCI read cycles, the calculated parity is compared
to the parity indicator of the master; a miscompare can result in a parity error assertion (P_PERR
).
P_PERR R12 I/O
Primary parity error indicator. P_PERR is driven by a primary-bus PCI device to indicate the calculated
parity does not match P_PAR when P_PERR
is enabled through the primary command register (offset
04h).
P_REQ P6 O Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as a master.
P_SERR W13 O
Primary system error. Output pulsed from the bridge when enabled through the primary command
register (offset 04h) indicating a system error has occurred. The bridge need not be the target of the
primary PCI cycle to assert this signal. When S_SERR is enabled in the bridge control register (offset
3Eh), this signal also pulses, indicating that a system error has occurred on one of the subordinate
buses downstream from the bridge.
P_STOP W12 I/O
Primary cycle stop signal. This signal is driven by a PCI target to request that the master stop the
current primary bus transaction. This signal is used for target disconnects and is commonly asserted by
target devices which do not support burst data transfers.
P_TRDY P11 I/O
Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current data
phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both P_IRDY
and P_TRDY are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are inserted.
Introduction
10
April 2005SCPS096A
Table 2−6. PCI Secondary Bus System Terminals
TERMINAL
NAME
GHK
NUMBER
I/O DESCRIPTION
S_CLKOUT9
S_CLKOUT8
S_CLKOUT7
S_CLKOUT6
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
P1
N6
N2
N1
M6
M3
M1
L5
L2
L1
O
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each
secondary bus device samples all secondary PCI signals at the rising edge of the corresponding
S_CLKOUT input.
S_CLK J3 I
Secondary PCI bus clock input. This input synchronizes the PCI2060 bridge to the secondary bus
clocks.
S_CFN J6 I
Secondary external arbiter enable. When this signal is low, the secondary internal arbiter is enabled.
When this signal is high, the secondary external arbiter is enabled. When the external arbiter is
enabled, the S_REQ0 terminal is reconfigured as a secondary bus grant input to the bridge and
S_GNT0
is reconfigured as a secondary bus master request to the external arbiter on the secondary
bus.
S_RST J5 O
Secondary PCI reset. S_RST is the logical OR of P_RST and the state of the secondary bus reset bit
(bit 6) of the bridge-control register (offset 3Eh). S_RST
is asynchronous with respect to the state of
the secondary interface CLK signal.
Introduction
11
April 2005 SCPS096A
Table 2−7. PCI Secondary Bus Address and Data Terminals
TERMINAL
NAME
GHK
NUMBER
I/O DESCRIPTION
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
A4
E6
B5
A5
C6
B6
A6
C7
E8
F8
B8
A8
F9
C9
F10
E10
E13
B14
A15
B15
E14
F15
F14
F17
F19
G14
G18
G19
H14
H17
H19
J15
I/O
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on the
secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31 through S_AD0
contain a 32-bit address or other destination information. During the data phase, S_AD31 through S_AD0
contain data.
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
B7
A10
F12
G15
I/O
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a secondary bus PCI cycle, S_C/BE3
through S_C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as a byte enable. The byte enable determines
which byte paths of the full 32-bit data bus carry meaningful data. S_C/BE0 applies to byte 0 (S_AD7
through S_AD0), S_C/BE1
applies to byte 1 (S_AD15 through S_AD8), S_C/BE2 applies to byte 2
(S_AD23 through S_AD16), and S_C/BE3
applies to byte 3 (S_AD31 through S_AD24).
Introduction
12
April 2005SCPS096A
Table 2−8. PCI Secondary Bus Control Terminals
TERMINAL
NAME
GHK
NUMBER
I/O DESCRIPTION
S_DEVSEL A11 I/O
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As a
PCI master on the secondary bus, the bridge monitors S_DEVSEL
until a target responds. If no target
responds before time-out occurs, then the bridge terminates the cycle with a master abort.
S_FRAME F11 I/O
Secondary cycle frame. S_FRAME is driven by the master of a secondary bus cycle. S_FRAME is
asserted to indicate that a bus transaction is beginning and data transfers continue while S_FRAME
is
asserted. When S_FRAME
is deasserted, the secondary bus transaction is in the final data phase.
S_GNT8
S_GNT7
S_GNT6
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
J1
H1
H2
H3
H5
G1
G2
H6
F1
O
Secondary bus grant. The bridge provides internal arbitration and these signals grant potential secondary
PCI bus masters access to the bus. Ten potential masters (including the bridge) can be located on the
secondary PCI bus. When the internal arbiter is disabled, S_GNT0
is reconfigured as an external
secondary bus request signal for the bridge.
S_IRDY C11 I/O
Secondary initiator ready. S_IRDY indicates the ability of the secondary bus master to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
S_IRDY and S_TRDY are asserted. Until S_IRDY and S_TRDY are asserted, wait states are inserted.
S_LOCK C12 I/O Secondary PCI bus lock. S_LOCK locks the secondary bus and gains exclusive access as a master.
S_PAR C13 I/O
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across the
S_AD and S_C/BE
buses. As a master during PCI write cycles, the bridge outputs this parity indicator
with a one S_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the
master parity indicator. A miscompare can result in a parity error assertion (S_PERR).
S_PERR E12 I/O
Secondary parity error indicator. S_PERR is asserted when a data parity error is detected for data
received on the secondary interface.
S_REQ8
S_REQ7
S_REQ6
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
G5
F2
F3
E1
E2
G6
F5
E3
B4
I
Secondary PCI request signals. The bridge provides internal arbitration, and these signals are used as
inputs from secondary PCI bus masters requesting the bus. Ten potential masters (including the bridge)
can be located on the secondary PCI bus.
When the internal arbiter is disabled, the S_REQ0
signal is reconfigured as an external secondary bus
grant for the bridge.
S_SERR B13 I
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled
through the bridge control register (offset 3Eh). S_SERR
is never asserted by the bridge.
S_STOP B12 I/O
Secondary-cycle stop signal. S_STOP is driven by a PCI target to request that the master stop the
current secondary bus transaction. S_STOP
is used for target disconnects and is commonly asserted by
target devices that do not support burst data transfers.
S_TRDY B11 I/O
Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the current
data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both S_IRDY
and S_TRDY are asserted. Until S_IRDY and S_TRDY are asserted, wait states are inserted.
Introduction
13
April 2005 SCPS096A
Table 2−9. Miscellaneous Terminals
TERMINAL
NAME
GHK
NUMBER
I/O DESCRIPTION
BPCCE N5 I
Bus/power clock-control management terminal. When the BPCCE signal is tied high and when
the PCI2060 bridge is placed in the D3 power state, it enables the PCI2060 bridge to place the
secondary bus in the B2 power state. The PCI2060 bridge disables the secondary clocks and
drives them to 0. When tied low, placing the PCI2060 bridge in the D3 power state has no effect
on the secondary bus clocks.
GPIO3/ HSSWITCH
GPIO2
GPIO1
GPIO0
K1
K2
K5
K6
I/O
General-purpose I/O terminals
GPIO3 is HSSWITCH
in the compactPCI mode.
HSSWITCH
provides the status of the ejector handle switch to the compactPCI logic.
HSENUM L15 O Hot-swap ENUM. This signal notifies the host that a card insertion or removal event is pending.
HSLED L14 O Hot-swap LED output
MS0 E17 I Mode select 0
MS1 T19 I Mode select 1
P_M66ENA W16 I
Primary interface 66-MHz enable. This input-only signal terminal designates the primary
interface bus speed. This signal must be pulled low for 33-MHz operation on the primary bus. In
this case, the S_M66ENA signal is driven low by the PCI2060 bridge, forcing the secondary bus
to run at 33 MHz. For 66-MHz operation, this signal must be pulled high.
CONFIG66 L18 I
Configure 66-MHz operation. This input-only terminal specifies whether the PCI2060 bridge is
capable of running at 66 MHz. If this terminal is tied high, then the device can be run at 66 MHz.
If this terminal is tied low, then the PCI2060 bridge can only function under the 33-MHz PCI
specification.
S_M66ENA E18 I/O
Secondary 66-MHz enable. This signal designates the secondary bus speed. See Section 3.10.1
for more detail on the use of the S_M66ENA signal. Note that S_M66ENA is an open-drained
output.
SEC_ASYNC_CLK C1 I
Secondary asynchronous clock. This terminal is the secondary clock input when the
SEC_ASYNC_SEL terminal is high.
SEC_ASYNC_SEL C4 I
Secondary clock select. This terminal selects the clock that generates the secondary bus clock.
If SEC_ASYNC_SEL is low, then the primary PCI clock (P_CLK) input generates the secondary
bus clock. If SEC_ASYNC_SEL is high, then the SEC_ASYNC_CLK generates the secondary
bus clock.
SEC_ASYNC_RATE D18 I
Secondary clock rate. This terminal selects the clock speed of the secondary bus clock. If
SEC_ASYNC_RATE is low, then the secondary clock outputs are one-half of the input clock
frequency. If SEC_ASYNC_RATE is high, then the secondary clock outputs are the same as the
input clock frequency.
MASK_IN L17 I
Secondary clock disable serial input. This input-only signal is used by the hardware mechanism
to disable secondary clock outputs. The serial stream is received by the MASK_IN, starting
when P_RST is detected as deasserted and S_RST is detected as asserted. This serial data is
used for selectively disabling the secondary clock outputs and is shifted into the secondary clock
control register (offset 68h). This input can be tied low to enable all secondary clock outputs or
tied high to drive all secondary clock outputs high.
Introduction
14
April 2005SCPS096A
Table 2−10. JTAG Terminals
TERMINAL
NAME
GHK
NUMBER
I/O DESCRIPTION
TCK J19 I JTAG boundary scan clock. TCK is the clock controlling the JTAG logic.
TDI K18 I
JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the JTAG
interface. The new data on TDI is sampled on the rising edge of TCK.
TDO K17 O
JTAG serial data out. TDO is the serial output through which test instructions and test data from the test logic
leave the PCI2060 bridge.
TMS K14 I JTAG test mode select. TMS causes state transitions in the test-access port controller.
TRST J18 I
JTAG reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter a reset state
and initialize the test logic.
Table 2−11. Power Supply Terminals
TERMINAL
NAME GHK NUMBER
DESCRIPTION
V
CC
A3, A9, A13, A16, C8,
C14, D2, E11, E19, F6,
F7, G17, H18, K3, K15,
M2, M15, N3, N15, P7,
P8, P15, T2, T18, U13,
V11, V16, W4, W8,
W10, W15
3.3-V power terminals
GND
A7, A12, A14, B10, C5,
C15, D19, E7, E9, F13,
F18, G3, H15, J2, J14,
L6, M5, M19, N17, P5,
R8, R10, R14, R19, U1,
U5, U9, U12, V6, V14,
W17
Device ground terminals
P_VIO L19
Primary interface I/O voltage. This signal must be tied to either 3.3 V or 5 V, corresponding to the
signaling environment of the primary PCI bus as described in the PCI Local Bus Specification,
Revision 2.3. When any device on the primary PCI bus uses 5-V signaling levels, tie P_VIO to 5 V.
When all the devices on the primary bus use 3.3-V signaling levels, tie P_VIO to 3.3 V.
S_VIO J17
Secondary interface I/O voltage. This signal must be tied to either 3.3 V or 5 V, corresponding to the
signaling environment of the secondary PCI bus as described in the PCI Local Bus Specification,
Revision 2.3. When any device on the secondary PCI bus uses 5-V signaling levels, tie S_VIO to 5 V.
When all the devices on the secondary bus use 3.3-V signaling levels, tie S_VIO to 3.3 V.
Table 2−12. No Connect Terminals
TERMINAL
NAME GHK NUMBER
DESCRIPTION
NC
A2, A17, A18, B1, B2,
B3, B9, B16, B17, B18,
B19, C2, C3, C10, C16,
C17, C18, C19, D1, D3,
D17, E5, K19, L3, R2,
T3, T17, U2, U3, U4,
U16, U17, U18, U19, V1,
V2, V3, V4,V5, V12, V17,
V18, V19, W2, W3, W18
These terminals have no function on the PCI2060 bridge.
Principles of Operation
15
April 2005 SCPS096A
3 Principles of Operation
The PCI2060 is a bridge between two PCI buses and is compliant with both the PCI Local Bus Specification
and the PCI-to-PCI Bridge Specification. The PCI2060 bridge makes it possible for both the primary and
secondary bus clocks to be completely asynchronous and supports the PCI clock frequency up to 66 MHz.
The primary and secondary buses operate independently in either 3.3-V or 5-V signaling environment. The
core logic of the bridge, however, is powered at 1.8-V to reduce power consumption. Figure 3−1 shows a
simplified block diagram of a typical system implementation using the PCI2060 bridge.
PCI Option Card
CPU
Memory
Host
Bridge
PCI2050B
PCI
Device
PCI
Device
PCI Bus 0
PCI Bus 1
Host Bus
PCI Option Slot
PCI2060
PCI
Device
PCI
Device
PCI Bus 2
(Option)
PCI Option Card
Figure 3−1. System Block Diagram
Host software interacts with the bridge through internal registers. These internal registers provide the standard
PCI status and control for both the primary and secondary buses. Many vendor-specific features that exist in
the TI extension register set are included in the bridge. The PCI configuration header of the bridge is only
accessible from the primary PCI interface.
The bridge provides internal arbitration for the nine possible secondary bus masters, and provides each with
a dedicated active low request/grant pair (REQ
/GNT). The arbiter features a two-tier rotational scheme with
the PCI2060 bridge defaulting to the highest priority tier. The PCI2060 bridge also supports external
arbitration.
Upon system power up, power-on self-test (POST) software configures the bridge according to the devices
that exist on subordinate buses, and enables performance-enhancing features of the PCI2060 bridge. In a
typical system, this is the only communication with the bridge internal register set.
3.1 Types of Transactions
PCI bus commands indicate to the target the type of transaction the master is requesting. Table 3−1 lists the
PCI command and name of each PCI transaction on the command/byte enable (C/BE
) bus during the address
phase of a bus cycle. The master and target columns indicate PCI2060 support for each transaction when the
PCI2060 bridge initiates transactions as a master, on the primary bus and on the secondary bus, and when
the PCI2060 bridge responds to transactions as a target, on the primary bus and on the secondary bus.
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