Texas Instruments PCI2050GHK, PCI2050PDV Datasheet
1999 PCIBus Solutions
Data Manual
Printed in U.S.A., 12/99 SCPS053
PCI2050
PCI-to-PCI Bridge
Data Manual
Literature Number: SCPS053
December 1999
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify, before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUIT ABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
iii
Contents
Section Title Page
1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Related Documents 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Ordering Information 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Feature/Protocol Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Introduction to the PCI2050 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 PCI Commands 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Configuration Cycles 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Special Cycle Generation 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Secondary Clocks 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Primary Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Internal Secondary Bus Arbitration 3–5. . . . . . . . . . . . . . . . . . . .
3.6.3 External Secondary Bus Arbitration 3–6. . . . . . . . . . . . . . . . . . .
3.7 Decode Options 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 System Error Handling 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Posted Write Parity Error 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Posted Write Timeout 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 Target Abort on Posted Writes 3–6. . . . . . . . . . . . . . . . . . . . . . . .
3.8.4 Master Abort on Posted Writes 3–7. . . . . . . . . . . . . . . . . . . . . . .
3.8.5 Master Delayed Write Timeout 3–7. . . . . . . . . . . . . . . . . . . . . . . .
3.8.6 Master Delayed Read Timeout 3–7. . . . . . . . . . . . . . . . . . . . . . .
3.8.7 Secondary SERR 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Parity Handling and Parity Error Reporting 3–7. . . . . . . . . . . . . . . . . . . . . .
3.9.1 Address Parity Error 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9.2 Data Parity Error 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 Master and Target Abort Handling 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 Discard Timer 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.12 Delayed Transactions 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 Mode Selection 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14 Compact PCI Hot-Swap Support 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15 JTAG Support 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.1 Test Port Instructions 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16 GPIO Interface 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.16.1 Secondary Clock Mask 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
3.16.2 Transaction Forwarding Control 3–15. . . . . . . . . . . . . . . . . . . . . . .
3.17 PCI Power Management 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17.1 Behavior in Low Power States 3–15. . . . . . . . . . . . . . . . . . . . . . . .
4 Bridge Configuration Header 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 Vendor ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Device ID Register 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Revision ID Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Class Code Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 Cache Line Size Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Primary Latency Timer Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Header Type Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 BIST Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 Base Address Register 0 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 Base Address Register 1 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Primary Bus Number Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Bus Number Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 Subordinate Bus Number Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 Secondary Bus Latency Timer Register 4–8. . . . . . . . . . . . . . . . . . . . . . . .
4.17 I/O Base Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 I/O Limit Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Secondary Status Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Base Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 Memory Limit Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 Prefetchable Memory Base Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Prefetchable Memory Limit Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Prefetchable Base Upper 32 Bits Register 4–12. . . . . . . . . . . . . . . . . . . . . .
4.25 Prefetchable Limit Upper 32 Bits Register 4–13. . . . . . . . . . . . . . . . . . . . . .
4.26 I/O Base Upper 16 Bits Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 I/O Limit Upper 16 Bits Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 Capability Pointer Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.29 Expansion ROM Base Address Register 4–14. . . . . . . . . . . . . . . . . . . . . . . .
4.30 Interrupt Line Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Interrupt Pin Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Bridge Control Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Extension Registers 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Chip Control Register 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Extended Diagnostic Register 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Arbiter Control Register 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 P_SERR Event Disable Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 GPIO Output Data Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 GPIO Output Enable Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 GPIO Input Data Register 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
5.8 Secondary Clock Control Register 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 P_SERR Status Register 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 PM Capability ID Register 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 PM Next Item Pointer Register 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 Power Management Capabilities Register 5–9. . . . . . . . . . . . . . . . . . . . . .
5.13 Power Management Control/Status Register 5–10. . . . . . . . . . . . . . . . . . . .
5.14 PMCSR Bridge Support Register 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.15 Data Register 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.16 HS Capability ID Register 5–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.17 HS Next Item Pointer Register 5–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.18 Hot Swap Control Status Register 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Absolute Maximum Ratings Over Operating Temperature Ranges 6–1.
6.2 Recommended Operating Conditions 6–2. . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Recommended Operating Conditions for PCI Interface 6–2. . . . . . . . . . .
6.4 Electrical Characteristics Over Recommended Operating Conditions 6–3
6.5 PCI Clock/Reset Timing Requirements Over Recommended
Ranges Of Supply Voltage And Operating Free-Air Temperature 6–4. . .
6.6 PCI Timing Requirements Over Recommended Ranges Of
Supply Voltage And Operating Free-Air Temperature 6–5. . . . . . . . . . . . .
6.7 Parameter Measurement Information 6–6. . . . . . . . . . . . . . . . . . . . . . . . . .
6.8 PCI Bus Parameter Measurement Information 6–7. . . . . . . . . . . . . . . . . . .
7 Mechanical Data 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
List of Illustrations
Figure Title Page
2–1 PCI2050 Terminal Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 System Block Diagram 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI AD31–AD0 During Address Phase of a Type 0 Configuration Cycle 3–2
3–3 PCI AD31–AD0 During Address Phase of a Type 1 Configuration Cycle 3–3
3–4 Bus Hierarchy and Numbering 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Secondary Clock Block Diagram 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Clock Mask Read Timing After Reset 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–1 Load Circuit and Voltage Waveforms 6–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–2 PCLK Timing Waveform 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–3 RSTIN
Timing Waveforms 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6–4 Shared-Signals Timing Waveforms 6–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vii
List of Tables
Table Title Page
2–1 208-Terminal PDV Signal Names Sorted by Terminal Number 2–2. . . . . . . .
2–2 Signal Names Sorted Alphabetically 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–3 208-Terminal GHK Signal Names Sorted by Terminal Number 2–6. . . . . . . .
2–4 Primary PCI System 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 Primary PCI Address and Data 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Primary PCI Interface Control 2–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 Secondary PCI System 2–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 Secondary PCI Address and Data 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 Secondary PCI Interface Control 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–10 Miscellaneous Terminals 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–11 JTAG Interface Terminals 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–12 Power Supply 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 PCI Command Definition 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 PCI S_AD31–S_AD16 During the Address Phase of a Type 0
Configuration Cycle 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Configuration Via MS0 and MS1 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–4 JTAG Instructions and Op Codes 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–5 Boundary Scan Terminal Order 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–6 Clock Mask Data Format 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–1 Bridge Configuration Header 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–2 Command Register 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–3 Status Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–4 Secondary Status Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–5 Bridge Control Register 4–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–1 Chip Control Register 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–2 Extended Diagnostic Register 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–3 Arbiter Control Register 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–4 P_SERR Event Disable Register 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–5 GPIO Output Data Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–6 GPIO Output Enable Register 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–7 GPIO Input Data Register 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–8 Secondary Clock Control Register 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–9 P_SERR Status Register 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–10 Power Management Capabilities Register 5–9. . . . . . . . . . . . . . . . . . . . . . . . . .
5–11 Power Management Control/Status Register 5–10. . . . . . . . . . . . . . . . . . . . . . .
5–12 PMCSR Bridge Support Register 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5–13 Hot Swap Control Status Register 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
1–1
1 Introduction
1.1 Description
The Texas Instruments PCI2050 PCI-to-PCI bridge provides a high performance connection path between two
peripheral component interconnect (PCI) buses. Transactions occur between masters on one PCI bus and targets
on another PCI bus, and the PCI2050 allows bridged transactions to occur concurrently on both buses. The bridge
supports burst-mode transfers to maximize data throughput, and the two bus traffic paths through the bridge act
independently.
The PCI2050 bridge is compliant with the
PCI Local Bus Specification
, and can be used to overcome the electrical
loading limits of 10 devices per PCI bus and one PCI device per expansion slot by creating hierarchical buses. The
PCI2050 provides two-tier internal arbitration for up to nine secondary bus masters and may be implemented with
an external secondary PCI bus arbiter.
The compact-PCI hot-swap extended PCI capability is provided which makes the PCI2050 an ideal solution for
multifunction compact PCI cards and adapting single function cards to hot-swap compliance.
The PCI2050 bridge is compliant with the
PCI-to-PCI Bridge Specification 1.1
. The PCI 2050 provides compliance
for
PCI Power Management 1.0 and 1.1
. The PCI2050 has been designed to lead the industry in power conservation.
An advanced CMOS process is used to achieve low system power consumption while operating at PCI clock rates
up to 33 MHz.
1.2 Features
The PCI2050 supports the following features:
• Configurable for
PCI Bus Power Management Interface Specification
• Provides compact PCI hot-swap functionality
• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments
• Two 32-bit, 33-MHz PCI buses
• Provides internal two-tier arbitration for up to nine secondary bus masters and supports an external
secondary bus arbiter
• Burst data transfers with pipeline architecture to maximize data throughput in both directions
• Independent read and write buffers for each direction
• Up to three delayed transactions in both directions
• Provides 10 secondary PCI clock outputs
• Predictable latency per
PCI Local Bus Specification
• Propagates bus locking
• Secondary bus is driven low during reset
• Provides VGA/palette memory and I/O, and subtractive decoding options
• Advanced submicron, low-power CMOS technology
• Packaged in 208-terminal QFP or 209-terminal MicroStar BGA
1–2
1.3 Related Documents
•
Advanced Configuration and Power Interface (ACPI) Specification (Revision 1.0)
•
PCI Local Bus Specification (Revision 2.2)
•
PCI-to-PCI Bridge Architecture Specification (Revision 1.1)
•
PCI Bus Power Management Interface Specification (Revision 1.1)
•
PICMG Compact-PCI Hot Swap Specification (Revision 1.0)
1.4 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
PCI2050 PCI–PCI Bridge 3.3 V, 5-V Tolerant I/Os 208-terminal QFP
209-terminal MicroStar BGA
2–1
2 Terminal Descriptions
P_AD19
TMS
P_AD11
P_TRDY
S_CLKOUT0
S_GNT8
S_GNT5
S_GNT0
CC
S_REQ1
S_REQ2
S_REQ3
S_REQ5
S_REQ8
S_GNT1
S_GNT2
S_GNT3
S_GNT4
S_GNT6
S_GNT7
GND
S_CLK
S_RST
S_CFN
HSSWITCH/GPIO3
GPIO2
GPIO0
S_CLKOUT1
S_CLKOUT2
S_CLKOUT5
S_CLKOUT4
S_CLKOUT8
P_RST
BPCCE
P_CLK
P_GNT
P_AD30
P_REQ
GND
P_AD31
GND
GND
GPIO1
S_CLKOUT3
S_CLKOUT7
S_CLKOUT9
S_AD13
S_AD15
S_C/BE1
S_SERR
GND
S_LOCK
S_PERR
GND
S_TRDY
S_FRAME
S_C/BE2
GND
S_AD16
S_AD19
S_IRDY
S_AD17
S_AD22
GND
S_C/BE3
S_AD24
S_AD25
GND
S_AD27
S_AD30
GND
S_AD31
S_REQ0
GND
NC
GND
P_AD12
P_AD13
P_C/BE1
P_AD14
GND
P_AD15
P_PAR
P_SERR
P_LOCK
P_STOP
P_DEVSEL
P_IRDY
P_FRAME
P_C/BE2
GND
P_AD16
P_AD17
P_AD18
GND
P_AD20
P_AD22
P_AD23
GND
P_AD21
P_AD24
P_IDSEL
V
P_AD25
P_AD26
GND
P_AD27
P_AD28
P_AD29
GND
158
157
160
159
162
161
164
163
166
165
168
167
170
169
172
171
174
173
176
175
178
177
180
179
182
181
184
183
186
185
188
187
190
189
192
191
194
193
196
195
198
197
200
199
202
201
204
203
206
205
208
207
103
104
101
102
99
100
97
98
95
96
93
94
91
92
89
90
87
88
85
86
83
84
81
82
79
80
77
78
75
76
73
74
71
72
69
70
67
68
65
66
63
64
61
62
59
60
57
58
55
56
53
54
P_PERR
P_AD10
214365871091211141316151817201922212423262528273029323134333635383740394241444346454847504952
51 106
105
108
107
110
109
112
111
114
113
116
115
118
117
120
119
122
121
124
123
126
125
128
127
130
129
132
131
134
133
136
135
138
137
140
139
142
141
144
143
146
145
148
147
150
149
152
151
154
153
156
155
GND
S_M66ENA
S_AD10
S_AD9
S_C/BE0
S_AD8
S_AD7
S_AD6
GND
S_AD5
S_AD2
S_AD3
S_AD0
S_AD1
GND
TCLK
TRST
TDO
HSLED
GND
NC
MSK_IN
HSENUM
GND
P_V
P_AD1
P_AD0
P_AD2
P_AD4
P_AD5
P_AD7
P_AD3
P_AD8
P_C/BE0
P_AD9
MS1
S_PAR
S_AD18
S_AD20
S_AD21
S_AD26
V
S_REQ4
CC
V
CC
V
CC
MS0
GND
S_AD11
GND
S_AD12
V
CC
S_AD23
V
CC
S_AD29
CC
V
PCI2050
PDV LOW-PROFILE QUAD FLAT PACKAGE
TOP VIEW
S_REQ6
S_REQ7
GND
CC
V
GND
S_CLKOUT6
CC
V
CC
V
V
CC
V
CC
P_C/BE3
V
CC
V
CC
V
CC
GND
V
CC
V
CC
V
CC
V
CC
V
CC
P_AD6
V
CC
GND
CCP
TDI
V
CC
S_V
CCP
V
CC
S_AD4
V
CC
GND
V
CC
V
CC
S_AD14
V
CC
S_STOP
S_DEVSEL
V
CC
GND
V
CC
S_AD28
V
CC
V
CC
Figure 2–1. PCI2050 Terminal Diagram
2–2
T able 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
1 D1 V
CC
44 P2 BPCCE 87 V12 P_LOCK 130 K17 TDO
2 E3 S_REQ1 45 N5 P_CLK 88 U12 P_PERR 131 K15 V
CC
3 F5 S_REQ2 46 P3 P_GNT 89 P12 P_SERR 132 K14 TMS
4 G6 S_REQ3 47 R1 P_REQ 90 R12 P_PAR 133 J19 TCLK
5 E2 S_REQ4 48 P6 GND 91 W13 V
CC
134 J18 TRST
6 E1 S_REQ5 49 R2 P_AD31 92 V13 P_C/BE1 135 J17 S_V
CCP
7 F3 S_REQ6 50 P5 P_AD30 93 U13 P_AD15 136 J14 GND
8 F2 S_REQ7 51 R3 V
CC
94 P13 GND 137 J15 S_AD0
9 G5 S_REQ8 52 T1 GND 95 W14 P_AD14 138 H19 S_AD1
10 F1 S_GNT0 53 W4 V
CC
96 V14 P_AD13 139 H18 V
CC
11 H6 S_GNT1 54 U5 GND 97 R13 V
CC
140 H17 S_AD2
12 G3 GND 55 R6 P_AD29 98 U14 P_AD12 141 H14 S_AD3
13 G2 S_GNT2 56 P7 V
CC
99 W15 P_AD11 142 H15 GND
14 G1 S_GNT3 57 V5 P_AD28 100 P14 GND 143 G19 S_AD4
15 H5 S_GNT4 58 W5 P_AD27 101 V15 P_AD10 144 G18 S_AD5
16 H3 S_GNT5 59 U6 GND 102 R14 NC 145 G17 V
CC
17 H2 S_GNT6 60 V6 P_AD26 103 U15 V
CC
146 G14 S_AD6
18 H1 S_GNT7 61 R7 P_AD25 104 W16 GND 147 F19 S_AD7
19 J1 S_GNT8 62 W6 V
CC
105 T19 V
CC
148 F18 GND
20 J2 GND 63 P8 P_AD24 106 R17 MS1 149 G15 S_C/BE0
21 J3 S_CLK 64 U7 P_C/BE3 107 P15 P_AD9 150 F17 S_AD8
22 J5 S_RST 65 V7 P_IDSEL 108 N14 V
CC
151 E19 V
CC
23 J6 S_CFN 66 W7 GND 109 R18 P_AD8 152 F14 S_AD9
24 K1 HSSWITCH/GPIO3 67 R8 P_AD23 110 R19 P_C/BE0 153 E18 S_M66ENA
25 K2 GPIO2 68 U8 P_AD22 111 P17 GND 154 F15 S_AD10
26 K3 V
CC
69 V8 V
CC
112 P18 P_AD7 155 E17 MS0
27 K5 GPIO1 70 W8 P_AD21 113 N15 P_AD6 156 D19 GND
28 K6 GPIO0 71 W9 P_AD20 114 P19 V
CC
157 A16 V
CC
29 L1 S_CLKOUT0 72 V9 GND 115 M14 P_AD5 158 C15 GND
30 L2 S_CLKOUT1 73 U9 P_AD19 116 N17 P_AD4 159 E14 S_AD11
31 L3 GND 74 R9 P_AD18 117 N18 GND 160 F13 GND
32 L6 S_CLKOUT2 75 P9 V
CC
118 N19 P_AD3 161 B15 S_AD12
33 L5 S_CLKOUT3 76 W10 P_AD17 119 M15 P_AD2 162 A15 S_AD13
34 M1 V
CC
77 V10 P_AD16 120 M17 V
CC
163 C14 V
CC
35 M2 S_CLKOUT4 78 U10 GND 121 M18 P_AD1 164 B14 S_AD14
36 M3 S_CLKOUT5 79 R10 P_C/BE2 122 M19 P_AD0 165 E13 S_AD15
37 M6 GND 80 P10 P_FRAME 123 L19 GND 166 A14 GND
38 M5 S_CLKOUT6 81 W11 V
CC
124 L18 P_V
CCP
167 F12 S_C/BE1
39 N1 S_CLKOUT7 82 V11 P_IRDY 125 L17 NC 168 C13 S_PAR
40 N2 V
CC
83 U11 P_TRDY 126 L15 MSK_IN 169 B13 S_SERR
41 N3 S_CLKOUT8 84 P11 P_DEVSEL 127 L14 HSENUM 170 A13 V
CC
42 N6 S_CLKOUT9 85 R11 P_STOP 128 K19 HSLED 171 E12 S_PERR
43 P1 P_RST 86 W12 GND 129 K18 TDI 172 C12 S_LOCK
2–3
T able 2–1. 208-Terminal PDV Signal Names Sorted by Terminal Number (continued)
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
173 B12 S_STOP 182 C10 S_AD16 191 B8 S_AD22 200 B6 S_AD27
174 A12 GND 183 E10 S_AD17 192 C8 S_AD23 201 E7 S_AD28
175 A11 S_DEVSEL 184 F10 V
CC
193 F8 GND 202 C6 V
CC
176 B11 S_TRDY 185 A9 S_AD18 194 E8 S_C/BE3 203 A5 S_AD29
177 C11 S_IRDY 186 B9 S_AD19 195 A7 S_AD24 204 F6 S_AD30
178 E11 V
CC
187 C9 GND 196 B7 V
CC
205 B5 GND
179 F11 S_FRAME 188 F9 S_AD20 197 C7 S_AD25 206 E6 S_AD31
180 A10 S_C/BE2 189 E9 S_AD21 198 F7 S_AD26 207 C5 S_REQ0
181 B10 GND 190 A8 V
CC
199 A6 GND 208 A4 V
CC
2–4
Table 2–2. Signal Names Sorted Alphabetically
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
BPCCE 44 P2 P_AD0 122 M19 P_PAR 90 R12 S_C/BE3 194 E8
GND 12 G3 P_AD1 121 M18 P_PERR 88 U12 S_CFN 23 J6
GND 20 J2 P_AD2 119 M15 P_REQ 47 R1 S_CLK 21 J3
GND 31 L3 P_AD3 118 N19 P_RST 43 P1 S_CLKOUT0 29 L1
GND 37 M6 P_AD4 116 N17 P_SERR 89 P12 S_CLKOUT1 30 L2
GND 48 P6 P_AD5 115 M14 P_ST OP 85 R11 S_CLKOUT2 32 L6
GND 52 T1 P_AD6 113 N15 P_TRDY 83 U11 S_CLKOUT3 33 L5
GND 54 U5 P_AD7 112 P18 P_V
CCP
124 L18 S_CLKOUT4 35 M2
GND 59 U6 P_AD8 109 R18 S_AD0 137 J15 S_CLKOUT5 36 M3
GND 66 W7 P_AD9 107 P15 S_AD1 138 H19 S_CLKOUT6 38 M5
GND 72 V9 P_AD10 101 V15 S_AD2 140 H17 S_CLKOUT7 39 N1
GND 78 U10 P_AD11 99 W15 S_AD3 141 H14 S_CLKOUT8 41 N3
GND 86 W12 P_AD12 98 U14 S_AD4 143 G19 S_CLKOUT9 42 N6
GND 94 P13 P_AD13 96 V14 S_AD5 144 G18 S_DEVSEL 175 A11
GND 100 P14 P_AD14 95 W14 S_AD6 146 G14 S_FRAME 179 F11
GND 104 W16 P_AD15 93 U13 S_AD7 147 F19 S_GNT0 10 F1
GND 111 P17 P_AD16 77 V10 S_AD8 150 F17 S_GNT1 11 H6
GND 117 N18 P_AD17 76 W10 S_AD9 152 F14 S_GNT2 13 G2
GND 123 L19 P_AD18 74 R9 S_AD10 154 F15 S_GNT3 14 G1
GND 136 J14 P_AD19 73 U9 S_AD11 159 E14 S_GNT4 15 H5
GND 142 H15 P_AD20 71 W9 S_AD12 161 B15 S_GNT5 16 H3
GND 148 F18 P_AD21 70 W8 S_AD13 162 A15 S_GNT6 17 H2
GND 156 D19 P_AD22 68 U8 S_AD14 164 B14 S_GNT7 18 H1
GND 158 C15 P_AD23 67 R8 S_AD15 165 E13 S_GNT8 19 J1
GND 160 F13 P_AD24 63 P8 S_AD16 182 C10 S_IRDY 177 C11
GND 166 A14 P_AD25 61 R7 S_AD17 183 E10 S_LOCK 172 C12
GND 174 A12 P_AD26 60 V6 S_AD18 185 A9 S_M66ENA 153 E18
GND 181 B10 P_AD27 58 W5 S_AD19 186 B9 S_PAR 168 C13
GND 187 C9 P_AD28 57 V5 S_AD20 188 F9 S_PERR 171 E12
GND 193 F8 P_AD29 55 R6 S_AD21 189 E9 S_REQ0 207 C5
GND 199 A6 P_AD30 50 P5 S_AD22 191 B8 S_REQ1 2 E3
GND 205 B5 P_AD31 49 R2 S_AD23 192 C8 S_REQ2 3 F5
GPIO0 28 K6 P_C/BE0 110 R19 S_AD24 195 A7 S_REQ3 4 G6
GPIO1 27 K5 P_C/BE1 92 V13 S_AD25 197 C7 S_REQ4 5 E2
GPIO2 25 K2 P_C/BE2 79 R10 S_AD26 198 F7 S_REQ5 6 E1
HSENUM 127 L14 P_C/BE3 64 U7 S_AD27 200 B6 S_REQ6 7 F3
HSLED 128 K19 P_CLK 45 N5 S_AD28 201 E7 S_REQ7 8 F2
HSSWITCH/GPIO3 24 K1 P_DEVSEL 84 P11 S_AD29 203 A5 S_REQ8 9 G5
MS0 155 E17 P_FRAME 80 P10 S_AD30 204 F6 S_RST 22 J5
MS1 106 R17 P_GNT 46 P3 S_AD31 206 E6 S_SERR 169 B13
MSK_IN 126 L15 P_IDSEL 65 V7 S_C/BE0 149 G15 S_STOP 173 B12
NC 102 R14 P_IRDY 82 V11 S_C/BE1 167 F12 S_TRDY 176 B11
NC 125 L17 P_LOCK 87 V12 S_C/BE2 180 A10 S_V
CCP
135 J17
2–5
Table 2–2. Signal Names Sorted Alphabetically (continued)
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
SIGNAL NAME
PDV
NO.
GHK
NO.
TCLK 133 J19 V
CC
51 R3 V
CC
103 U15 V
CC
157 A16
TDI 129 K18 V
CC
53 W4 V
CC
105 T19 V
CC
163 C14
TDO 130 K17 V
CC
56 P7 V
CC
108 N14 V
CC
170 A13
TMS 132 K14 V
CC
62 W6 V
CC
114 P19 V
CC
178 E11
TRST 134 J18 V
CC
69 V8 V
CC
120 M17 V
CC
184 F10
V
CC
1 D1 V
CC
75 P9 V
CC
131 K15 V
CC
190 A8
V
CC
26 K3 V
CC
81 W11 V
CC
139 H18 V
CC
196 B7
V
CC
34 M1 V
CC
91 W13 V
CC
145 G17 V
CC
202 C6
V
CC
40 N2 V
CC
97 R13 V
CC
151 E19 V
CC
208 A4
2–6
Table 2–3. 209-Terminal GHK Signal Names Sorted by Terminal Number
GHK
NO.
SIGNAL NAME
GHK
NO.
SIGNAL NAME
GHK
NO.
SIGNAL NAME
GHK
NO.
SIGNAL NAME
GHK
NO.
SIGNAL NAME
A4 V
CC
E9 S_AD21 H17 S_AD2 N1 S_CLKOUT7 T19 V
CC
A5 S_AD29 E10 S_AD17 H18 V
CC
N2 V
CC
U5 GND
A6 GND E11 V
CC
H19 S_AD1 N3 S_CLKOUT8 U6 GND
A7 S_AD24 E12 S_PERR J1 S_GNT8 N5 P_CLK U7 P_C/BE3
A8 V
CC
E13 S_AD15 J2 GND N6 S_CLKOUT9 U8 P_AD22
A9 S_AD18 E14 S_AD11 J3 S_CLK N14 V
CC
U9 P_AD19
A10 S_C/BE2 E17 MS0 J5 S_RST N15 P_AD6 U10 GND
A11 S_DEVSEL E18 S_M66ENA J6 S_CFN N17 P_AD4 U11 P_TRDY
A12 GND E19 V
CC
J14 GND N18 GND U12 P_PERR
A13 V
CC
F1 S_GNT0 J15 S_AD0 N19 P_AD3 U13 P_AD15
A14 GND F2 S_REQ7 J17 S_V
CCP
P1 P_RST U14 P_AD12
A15 S_AD13 F3 S_REQ6 J18 TRST P2 BPCCE U15 V
CC
A16 V
CC
F5 S_REQ2 J19 TCLK P3 P_GNT V5 P_AD28
B5 GND F6 S_AD30 K1 HSSWITCH/GPIO3 P5 P_AD30 V6 P_AD26
B6 S_AD27 F7 S_AD26 K2 GPIO2 P6 GND V7 P_IDSEL
B7 V
CC
F8 GND K3 V
CC
P7 V
CC
V8 V
CC
B8 S_AD22 F9 S_AD20 K5 GPIO1 P8 P_AD24 V9 GND
B9 S_AD19 F10 V
CC
K6 GPIO0 P9 V
CC
V10 P_AD16
B10 GND F11 S_FRAME K14 TMS P10 P_FRAME V11 P_IRDY
B11 S_TRDY F12 S_C/BE1 K15 V
CC
P11 P_DEVSEL V12 P_LOCK
B12 S_STOP F13 GND K17 TDO P12 P_SERR V13 P_C/BE1
B13 S_SERR F14 S_AD9 K18 TDI P13 GND V14 P_AD13
B14 S_AD14 F15 S_AD10 K19 HSLED P14 GND V15 P_AD10
B15 S_AD12 F17 S_AD8 L1 S_CLKOUT0 P15 P_AD9 W4 V
CC
C5 S_REQ0 F18 GND L2 S_CLKOUT1 P17 GND W5 P_AD27
C6 V
CC
F19 S_AD7 L3 GND P18 P_AD7 W6 V
CC
C7 S_AD25 G1 S_GNT3 L5 S_CLKOUT3 P19 V
CC
W7 GND
C8 S_AD23 G2 S_GNT2 L6 S_CLKOUT2 R1 P_REQ W8 P_AD21
C9 GND G3 GND L14 HSENUM R2 P_AD31 W9 P_AD20
C10 S_AD16 G5 S_REQ8 L15 MSK_IN R3 V
CC
W10 P_AD17
C11 S_IRDY G6 S_REQ3 L17 NC R6 P_AD29 W11 V
CC
C12 S_LOCK G14 S_AD6 L18 P_V
CCP
R7 P_AD25 W12 GND
C13 S_PAR G15 S_C/BE0 L19 GND R8 P_AD23 W13 V
CC
C14 V
CC
G17 V
CC
M1 V
CC
R9 P_AD18 W14 P_AD14
C15 GND G18 S_AD5 M2 S_CLKOUT4 R10 V
CC
W15 P_AD11
D1 V
CC
G19 S_AD4 M3 S_CLKOUT5 R11 P_STOP W16 GND
D19 GND H1 S_GNT7 M5 S_CLKOUT6 R12 P_PAR
E1 S_REQ5 H2 S_GNT6 M6 GND R13 V
CC
E2 S_REQ4 H3 S_GNT5 M14 P_AD5 R14 NC
E3 S_REQ1 H5 S_GNT4 M15 P_AD2 R17 MS1
E6 S_AD31 H6 S_GNT1 M17 V
CC
R18 P_AD8
E7 S_AD28 H14 S_AD3 M18 P_AD1 R19 P_C/BE0
E8 S_C/BE3 H15 GND M19 P_AD0 T1 GND
2–7
T able 2–4. Primary PCI System
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O DESCRIPTION
P_CLK 45 N5 I
Primary PCI bus clock. P_CLK provides timing for all transactions on the primary PCI bus. All primary PCI
signals are sampled at rising edge of P_CLK.
P_RST
43 P1 I
PCI reset. When the primary PCI bus reset is asserted, P_RST causes the bridge to put all output buffers
in a high–impedance state and reset all internal registers. When asserted, the device is completely
nonfunctional. During P_RST
, the secondary interface is driven low. After P_RST is deasserted, the bridge
is in its default state.
Table 2–5. Primary PCI Address and Data
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O DESCRIPTION
P_AD31
P_AD30
P_AD29
P_AD28
P_AD27
P_AD26
P_AD25
P_AD24
P_AD23
P_AD22
P_AD21
P_AD20
P_AD19
P_AD18
P_AD17
P_AD16
P_AD15
P_AD14
P_AD13
P_AD12
P_AD11
P_AD10
P_AD9
P_AD8
P_AD7
P_AD6
P_AD5
P_AD4
P_AD3
P_AD2
P_AD1
P_AD0
49
50
55
57
58
60
61
63
67
68
70
71
73
74
76
77
93
95
96
98
99
101
107
109
112
113
115
116
118
119
121
122
R2
P5
R6
V5
W5
V6
R7
P8
R8
U8
W8
W9
U9
R9
W10
V10
U13
W14
V14
U14
W15
V15
P15
R18
P18
N15
M14
N17
N19
M15
M18
M19
I/O
Primary address/data bus. These signals make up the multiplexed PCI address and data bus on the
primary interface. During the address phase of a primary bus PCI cycle, P_AD31–P_AD0 contain a
32-bit address or other destination information. During the data phase, P_AD31–P_AD0 contain data.
P_C/BE3
P_C/BE2
P_C/BE1
P_C/BE0
64
79
92
110
U7
R10
V13
R19
I/O
Primary bus commands and byte enables. These signals are multiplexed on the same PCI terminals.
During the address phase of a primary bus PCI cycle, P_C/BE3
–P_C/BE0 define the bus command.
During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte
paths of the full 32-bit data bus carry meaningful data. P_C/BE0
applies to byte 0 (P_AD7–P_AD0),
P_C/BE1
applies to byte 1 (P_AD15–P_AD8), P_C/BE2 applies to byte 2 (P_AD23–P_AD16), and
P_C/BE3
applies to byte 3 (P_AD31–P_AD24).
2–8
Table 2–6. Primary PCI Interface Control
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O DESCRIPTION
P_DEVSEL 84 P11 I/O
Primary device select. The bridge asserts P_DEVSEL to claim a PCI cycle as the target device. As
a PCI initiator on the primary bus, the bridge monitors P_DEVSEL
until a target responds. If no target
responds before time-out occurs, then the bridge terminates the cycle with an initiator abort.
P_FRAME
80 P10 I/O
Primary cycle frame. P_FRAME is driven by the initiator of a primary bus cycle. P_FRAME is asserted
to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When P_FRAME
is deasserted, the primary bus transaction is in the final data phase.
P_GNT
46 P3 I
Primary bus grant to bridge. P_GNT is driven by the primary PCI bus arbiter to grant the bridge access
to the primary PCI bus after the current data transaction has completed. P_GNT
may or may not follow
a primary bus request, depending on the primary bus parking algorithm.
P_IDSEL 65 V7 I
Primary initialization device select. P_IDSEL selects the bridge during configuration space accesses.
P_IDSEL can be connected to one of the upper 24 PCI address lines on the primary PCI bus.
Note: There is no IDSEL signal interfacing the secondary PCI bus; thus, the entire configuration space
of the bridge can only be accessed from the primary bus.
P_IRDY 82 V11 I/O
Primary initiator ready. P_IRDY indicates ability of the primary bus initiator to complete the current data
phase of the transaction. A data phase is completed on a rising edge of P_CLK where both P_IRDY
and P_TRDY are asserted. Until P_IRDY and P_TRDY are both sampled asserted, wait states are
inserted.
P_LOCK 87 V12 I/O Primary PCI bus lock. P_LOCK is used to lock the primary bus and gain exclusive access as an initiator.
P_PAR 90 R12 I/O
Primary parity. In all primary bus read and write cycles, the bridge calculates even parity across the
P_AD and P_C/BE
buses. As an initiator during PCI write cycles, the bridge outputs this parity indicator
with a one-P_CLK delay. As a target during PCI read cycles, the calculated parity is compared to the
parity indicator of the initiator; a miscompare can result in a parity error assertion (P_PERR
).
P_PERR
88 U12 I/O
Primary parity error indicator. P_PERR is driven by a primary bus PCI device to indicate that calculated
parity does not match P_PAR when P_PERR
is enabled through bit 6 of the command register.
P_REQ 47 R1 O
Primary PCI bus request. Asserted by the bridge to request access to the primary PCI bus as an
initiator.
P_SERR 89 P12 O
Primary system error. Output pulsed from the bridge when enabled through the command register
indicating a system error has occurred. The bridge needs not be the target of the primary PCI cycle
to assert this signal. When bit 6 is enabled in the bridge control register (offset 3Eh, see Section 4.32),
this signal also pulses indicating that a system error has occurred on one of the subordinate buses
downstream from the bridge.
P_STOP 85 R11 I/O
Primary cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current
primary bus transaction. This signal is used for target disconnects and is commonly asserted by target
devices which do not support burst data transfers.
P_TRDY 83 U11 I/O
Primary target ready. P_TRDY indicates the ability of the primary bus target to complete the current
data phase of the transaction. A data phase is completed upon a rising edge of P_CLK where both
P_IRDY
and P_TRDY are asserted. Until both P_IRDY and P_TRDY are asserted, wait states are
inserted.
2–9
T able 2–7. Secondary PCI System
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O DESCRIPTION
S_CLKOUT9
S_CLKOUT8
S_CLKOUT7
S_CLKOUT6
S_CLKOUT5
S_CLKOUT4
S_CLKOUT3
S_CLKOUT2
S_CLKOUT1
S_CLKOUT0
42
41
39
38
36
35
33
32
30
29
N6
N3
N1
M5
M3
M2
L5
L6
L2
L1
O
Secondary PCI bus clocks. Provide timing for all transactions on the secondary PCI bus. Each
secondary bus device samples all secondary PCI signals at the rising edge of its corresponding
S_CLKOUT input.
S_CLK
21 J3 I Secondary PCI bus clock input. This input syncronizes the PCI2050 to the secondary bus clocks.
S_CFN 23 J6 I
Secondary external arbiter enable. When this signal is high, the secondary external arbiter is enabled.
When the external arbiter is enabled, the PCI2050 S_REQ0
pin is reconfigured as a secondary bus
grant input to the bridge and S_GNT0
is reconfigured as a secondary bus master request to the
external arbiter on the secondary bus.
S_RST 22 J5 O
Secondary PCI reset. S_RST is a logical OR of P_RST and the state of the secondary bus reset bit
(bit 6) of the bridge control register (offset 3Eh, see Section 4.32). S_RST
is asynchronous with
respect to the state of the secondary interface CLK signal.
2–10
Table 2–8. Secondary PCI Address and Data
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O DESCRIPTION
S_AD31
S_AD30
S_AD29
S_AD28
S_AD27
S_AD26
S_AD25
S_AD24
S_AD23
S_AD22
S_AD21
S_AD20
S_AD19
S_AD18
S_AD17
S_AD16
S_AD15
S_AD14
S_AD13
S_AD12
S_AD11
S_AD10
S_AD9
S_AD8
S_AD7
S_AD6
S_AD5
S_AD4
S_AD3
S_AD2
S_AD1
S_AD0
206
204
203
201
200
198
197
195
192
191
189
188
186
185
183
182
165
164
162
161
159
154
152
150
147
146
144
143
141
140
138
137
E6
F6
A5
E7
B6
F7
C7
A7
C8
B8
E9
F9
B9
A9
E10
C10
E13
B14
A15
B15
E14
F15
F14
F17
F19
G14
G18
G19
H14
H17
H19
J15
I/O
Secondary address/data bus. These signals make up the multiplexed PCI address and data bus on
the secondary interface. During the address phase of a secondary bus PCI cycle, S_AD31–S_AD0
contain a 32-bit address or other destination information. During the data phase, S_AD31–S_AD0
contain data.
S_C/BE3
S_C/BE2
S_C/BE1
S_C/BE0
194
180
167
149
E8
A10
F12
G15
I/O
Secondary bus commands and byte enables. These signals are multiplexed on the same PCI
terminals. During the address phase of a secondary bus PCI cycle, S_C/BE3
–S_C/BE0 define the bus
command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine
which byte paths of the full 32-bit data bus carry meaningful data. S_C/BE0
applies to byte 0
(S_AD7–S_AD0), S_C/BE1
applies to byte 1 (S_AD15–S_AD8), S_C/BE2 applies to byte 2
(S_AD23–S_AD16), and S_C/BE3
applies to byte 3 (S_AD31–S_AD24).
S_DEVSEL 175 A11 I/O
Secondary device select. The bridge asserts S_DEVSEL to claim a PCI cycle as the target device. As
a PCI initiator on the secondary bus, the bridge monitors S_DEVSEL
until a target responds. If no target
responds before timeout occurs, then the bridge terminates the cycle with an initiator abort.
S_FRAME 179 F11 I/O
Secondary cycle frame. S_FRAME is driven by the initiator of a secondary bus cycle. S_FRAME is
asserted to indicate that a bus transaction is beginning and data transfers continue while S_FRAME
is asserted. When S_FRAME is deasserted, the secondary bus transaction is in the final data phase.
S_GNT8
S_GNT7
S_GNT6
S_GNT5
S_GNT4
S_GNT3
S_GNT2
S_GNT1
S_GNT0
19
18
17
16
15
14
13
11
10
J1
H1
H2
H3
H5
G1
G2
H6
F1
O
Secondary bus grant to the bridge. The bridge provides internal arbitration and these signals are used
to grant potential secondary PCI bus masters access to the bus. T en potential initiators (including the
bridge) can be located on the secondary PCI bus.
When the internal arbiter is disabled, S_GNT0
is reconfigured as an external secondary bus request
signal for the bridge.
2–11
Table 2–9. Secondary PCI Interface Control
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O DESCRIPTION
S_IRDY 177 C11 I/O
Secondary initiator ready. S_IRDY indicates the ability of the secondary bus initiator to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_PCLKn where
both S_IRDY and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are
inserted.
S_LOCK 172 C12 I/O
Secondary PCI bus lock. S_LOCK is used to lock the secondary bus and gain exclusive access as an
initiator.
S_PAR 168 C13 I/O
Secondary parity. In all secondary bus read and write cycles, the bridge calculates even parity across
the S_AD and S_C/BE
buses. As an initiator during PCI write cycles, the bridge outputs this parity
indicator with a one-S_CLK delay . As a target during PCI read cycles, the calculated parity is compared
to the initiator parity indicator. A miscompare can result in a parity error assertion (S_PERR
).
S_PERR
171 E12 I/O
Secondary parity error indicator. S_PERR is driven by a secondary bus PCI device to indicate that
calculated parity does not match S_PAR when enabled through the command register.
S_REQ8
S_REQ7
S_REQ6
S_REQ5
S_REQ4
S_REQ3
S_REQ2
S_REQ1
S_REQ0
9
8
7
6
5
4
3
2
207
G5
F2
F3
E1
E2
G6
F5
E3
C5
I
Secondary PCI bus request signals. The bridge provides internal arbitration, and these signals are used
as inputs from secondary PCI bus initiators requesting the bus. Ten potential initiators (including the
bridge) can be located on the secondary PCI bus.
When the internal arbiter is disabled, the S_REQ0
signal is reconfigures as an external secondary bus
grant for the bridge.
S_SERR
169 B13 I
Secondary system error. S_SERR is passed through the primary interface by the bridge if enabled
through the bridge control register. S_SERR
is never asserted by the bridge.
S_STOP 173 B12 I/O
Secondary cycle stop signal. S_STOP is driven by a PCI target to request the initiator to stop the current
secondary bus transaction. S_STOP
is used for target disconnects and is commonly asserted by target
devices that do not support burst data transfers.
S_TRDY 176 B11 I/O
Secondary target ready. S_TRDY indicates the ability of the secondary bus target to complete the
current data phase of the transaction. A data phase is completed on a rising edge of S_CLK where both
S_IRDY
and S_TRDY are asserted; until S_IRDY and S_TRDY are asserted, wait states are inserted.
Table 2–10. Miscellaneous Terminals
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O DESCRIPTION
BPCCE 44 P2 I
Bus/power clock control management terminal. When signal BPCCE is tied high, and when the
PCI2050 is placed in the D3 power state, it enables the PCI2050 to place the secondary bus
in the B2 power state. The PCI2050 disables the secondary clocks and drives them to 0. When
tied low, placing the PCI2050 in the D3 power state has no ef fect on the secondary bus clocks.
GPIO3/HSSWITCH
GPIO2
GPIO1
GPIO0
24
25
27
28
K1
K2
K5
K6
I
General-purpose I/O pins
GPIO3 is HSSWITCH
in CPCI mode.
HSSWITCH
provides the status of the ejector handle switch to the CPCI logic.
HSENUM 127 L14 O Hot swap ENUM
HSLED 128 K19 O Hot swap LED output
MS0
155 E17 I Mode select 0
MS1
106 R17 I Mode select 1
NC
102
125
R14
L17
NC These terminals have no function on the PCI2050.
S_M66ENA 153 E18 O
Secondary bus 66-MHz enable pin. This pin is always driven low to incicate that the secondary
bus speed is 33 MHz.
2–12
Table 2–11. JTAG Interface Terminals
TERMINAL
NAME
PDV
NO.
GHK
NO.
I/O DESCRIPTION
TCLK 133 J19 I JTAG boundary-scan clock. TCLK is the clock controlling the JTAG logic.
TDI 129 K18 I
JTAG serial data in. TDI is the serial input through which JTAG instructions and test data enter the
JTAG interface. The new data on TDI is sampled on the rising edge of TCLK.
TDO 130 K17 O
JTAG serial data out. TDO is the serial output through which test instructions and data from the test
logic leave the PCI2050.
TMS 132 K14 I JTAG test mode select. TMS causes state transitions in the test access port controller.
TRST 134 J18 I
JTAG TAP reset. When TRST is asserted low, the TAP controller is asynchronously forced to enter
a reset state and initialize the test logic.
Table 2–12. Power Supply
TERMINAL
NAME PDV NO. GHK NO.
DESCRIPTION
GND
12, 20, 31, 37, 48, 52, 54,
59, 66, 72, 78, 86, 94, 100,
104, 111, 117, 123, 136,
142, 148, 156, 158, 160,
166, 174, 181, 187, 193,
199, 205
A6, A12, A14, B5, B10, C9,
C15, D19, F8, F13, F18,
G3, H15, J2, J14, L3, L19,
M6, N18, P6, P13, P14,
P17, T1, U5, U6, U10, V9,
W7, W12, W16
Device ground terminals
V
CC
1, 26, 34, 40, 51, 53, 56, 62,
69, 75, 81, 91, 97, 103, 105,
108, 114, 120, 131, 139,
145, 151, 157, 163, 170,
178, 184, 190, 196, 202,
208
A4, A8, A13, A16, B7, C6,
C14, D1, E11, E19, F10,
G17, H18, K3, K15, M1,
M17, N2, N14, P7, P9, P19,
R3, R13, T19, U15, V8, W4,
W6, W11, W13
Power-supply terminal for core logic (3.3 V)
P_V
CCP
124 L18
Primary bus-signaling environment supply. P_V
CCP
is used in
protection circuitry on primary bus I/O signals.
S_V
CCP
135 J17
Secondary bus-signaling environment supply. S_V
CCP
is used in
protection circuitry on secondary bus I/O signals.
3–1
3 Feature/Protocol Descriptions
The following sections give an overview of the PCI2050 PCI-to-PCI bridge features and functionality. Figure 3–1
shows a simplified block diagram of a typical system implementation using the PCI2050.
PCI Option Card
CPU
Memory
Host
Bridge
PCI2050
PCI
Device
PCI
Device
PCI Bus 0
PCI Bus 1
Host Bus
PCI Option Slot
PCI2050
PCI
Device
PCI
Device
PCI Bus 2
(Option)
PCI Option Card
Figure 3–1. System Block Diagram
3.1 Introduction to the PCI2050
The PCI2050 is a bridge between two PCI buses and is compliant with both the
PCI Local Bus Specification
and the
PCI-to-PCI Bridge Specification
. The bridge supports two 32-bit PCI buses operating at a maximum of 33 MHz. The
primary and secondary buses operate independently in either a 3.3-V or 5-V signaling environment. The core logic
of the bridge, however, is powered at 3.3 V to reduce power consumption.
Host software interacts with the bridge through internal registers. These internal registers provide the standard PCI
status and control for both the primary and secondary buses. Many vendor-specific features that exist in the TI
extension register set are included in the bridge. The PCI configuration header of the bridge is only accessible from
the primary PCI interface.
The bridge provides internal arbitration for the nine possible secondary bus masters, and provides each with a
dedicated active low request/grant pair (REQ
/GNT). The arbiter features a two-tier rotational scheme with the
PCI2050 bridge defaulting to the highest priority tier.
Upon system power up, power-on self-test (POST) software configures the bridge according to the devices that exist
on subordinate buses, and enables performance-enhancing features of the PCI2050. In a typical system, this is the
only communication with the bridge internal register set.
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