TEXAS INSTRUMENTS PCI1520 Technical data

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查询PCI1520供应商

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Data Manua

March 2004 PCIBus Solutions

SCPS065D

IMPORTANT NOTICE

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Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

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Copyright  2004, Texas Instruments Incorporated

Contents

Section Title Page

1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Description 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Related Documents 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Trademarks 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Ordering Information 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 PCI1520 Data Manual Document History 1−3. . . . . . . . . . . . . . . . . . . . . . .

2 Terminal Descriptions 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Feature/Protocol Descriptions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Power Supply Sequencing 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 I/O Characteristics 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Clamping Voltages 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Peripheral Component Interconnect (PCI) Interface 3−2. . . . . . . . . . . . . .

3.4.1 PCI GRST

3.4.2 PCI Bus Lock (LOCK

3.4.3 Loading Subsystem Identification 3−3. . . . . . . . . . . . . . . . . . . . .

3.5 PC Card Applications 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.1 PC Card Insertion/Removal and Recognition 3−4. . . . . . . . . . .

2

3.5.2 P

3.5.3 Zoomed Video Support 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.4 Standardized Zoomed-Video Register Model 3−7. . . . . . . . . . .

3.5.5 Internal Ring Oscillator 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.6 Integrated Pullup Resistors 3−8. . . . . . . . . . . . . . . . . . . . . . . . . .

3.5.7 SPKROUT and CAUDPWM Usage 3−9. . . . . . . . . . . . . . . . . . .

3.5.8 LED Socket Activity Indicators 3−10. . . . . . . . . . . . . . . . . . . . . . . .

3.5.9 CardBus Socket Registers 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Serial-Bus Interface 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6.1 Serial-Bus Interface Implementation 3−11. . . . . . . . . . . . . . . . . . .

3.6.2 Serial-Bus Interface Protocol 3−11. . . . . . . . . . . . . . . . . . . . . . . . .

3.6.3 Serial-Bus EEPROM Application 3−13. . . . . . . . . . . . . . . . . . . . . .

3.6.4 Accessing Serial-Bus Devices Through Software 3−14. . . . . . .

3.7 Programmable Interrupt Subsystem 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.1 PC Card Functional and Card Status Change

3.7.2 Interrupt Masks and Flags 3−17. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7.3 Using Parallel IRQ Interrupts 3−17. . . . . . . . . . . . . . . . . . . . . . . . .

3.7.4 Using Parallel PCI Interrupts 3−18. . . . . . . . . . . . . . . . . . . . . . . . .

C Power-Switch Interface (TPS222X) 3−4. . . . . . . . . . . . . . .

Interrupts 3−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Signal 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

) 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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3.7.5 Using Serialized IRQSER Interrupts 3−18. . . . . . . . . . . . . . . . . . .

3.7.6 SMI Support in the PCI1520 3−18. . . . . . . . . . . . . . . . . . . . . . . . . .

3.8 Power Management Overview 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR) 3−19. . . .

3.8.2 Clock Run Protocol 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.3 CardBus PC Card Power Management 3−20. . . . . . . . . . . . . . . .

3.8.4 16-Bit PC Card Power Management 3−20. . . . . . . . . . . . . . . . . . .

3.8.5 Suspend Mode 3−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.6 Requirements for Suspend Mode 3−21. . . . . . . . . . . . . . . . . . . . .

3.8.7 Ring Indicate 3−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.8 PCI Power Management 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.9 CardBus Bridge Power Management 3−23. . . . . . . . . . . . . . . . . .

3.8.10 ACPI Support 3−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.8.11 Master List of PME

Context Bits and Global

Reset-Only Bits 3−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 PC Card Controller Programming Model 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 PCI Configuration Registers (Functions 0 and 1) 4−1. . . . . . . . . . . . . . . . .

4.2 Vendor ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Device ID Register 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Command Register 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Status Register 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Revision ID Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 PCI Class Code Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Cache Line Size Register 4−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Latency Timer Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 Header Type Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 BIST Register 4−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 CardBus Socket/ExCA Base-Address Register 4−7. . . . . . . . . . . . . . . . . .

4.13 Capability Pointer Register 4−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Secondary Status Register 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 PCI Bus Number Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 CardBus Bus Number Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17 Subordinate Bus Number Register 4−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.18 CardBus Latency Timer Register 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19 Memory Base Registers 0, 1 4−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.20 Memory Limit Registers 0, 1 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.21 I/O Base Registers 0, 1 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22 I/O Limit Registers 0, 1 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 Interrupt Line Register 4−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.24 Interrupt Pin Register 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.25 Bridge Control Register 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.26 Subsystem Vendor ID Register 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.27 Subsystem ID Register 4−15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.28 PC Card 16-Bit I/F Legacy-Mode Base Address Register 4−15. . . . . . . . .

iv

4.29 System Control Register 4−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.30 Multifunction Routing Register 4−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.31 Retry Status Register 4−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.32 Card Control Register 4−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.33 Device Control Register 4−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.34 Diagnostic Register 4−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.35 Capability ID Register 4−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.36 Next-Item Pointer Register 4−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.37 Power-Management Capabilities Register 4−26. . . . . . . . . . . . . . . . . . . . . .

4.38 Power-Management Control/Status Register 4−27. . . . . . . . . . . . . . . . . . . .

4.39 Power-Management Control/Status Register Bridge

Support Extensions 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.40 Power-Management Data Register 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.41 General-Purpose Event Status Register 4−29. . . . . . . . . . . . . . . . . . . . . . . .

4.42 General-Purpose Event Enable Register 4−30. . . . . . . . . . . . . . . . . . . . . . .

4.43 General-Purpose Input Register 4−31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.44 General-Purpose Output Register 4−32. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.45 Serial-Bus Data Register 4−32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.46 Serial-Bus Index Register 4−33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.47 Serial-Bus Slave Address Register 4−33. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.48 Serial-Bus Control and Status Register 4−34. . . . . . . . . . . . . . . . . . . . . . . . .

5 ExCA Compatibility Registers (Functions 0 and 1) 5−1. . . . . . . . . . . . . . . . . .

5.1 ExCA Identification and Revision Register 5−5. . . . . . . . . . . . . . . . . . . . . .

5.2 ExCA Interface Status Register 5−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 ExCA Power Control Register 5−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 ExCA Interrupt and General Control Register 5−8. . . . . . . . . . . . . . . . . . .

5.5 ExCA Card Status-Change Register 5−9. . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 ExCA Card Status-Change Interrupt Configuration Register 5−10. . . . . . .

5.7 ExCA Address Window Enable Register 5−11. . . . . . . . . . . . . . . . . . . . . . . .

5.8 ExCA I/O Window Control Register 5−12. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 5−13. . . .

5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 5−13. . . .

5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 5−14. . . . .

5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 5−14. . . .

5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers 5−15. . .

5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers 5−16. . .

5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers 5−17. . . .

5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers 5−18. . .

5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers 5−19. .

5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers 5−20.

5.19 ExCA Card Detect and General Control Register 5−21. . . . . . . . . . . . . . . .

5.20 ExCA Global Control Register 5−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 5−23. . .

5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 5−23. . .

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5.23 ExCA Memory Windows 0−4 Page Registers 5−24. . . . . . . . . . . . . . . . . . .

6 CardBus Socket Registers (Functions 0 and 1) 6−1. . . . . . . . . . . . . . . . . . . . . .

6.1 Socket Event Register 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 Socket Mask Register 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 Socket Present-State Register 6−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 Socket Force Event Register 6−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 Socket Control Register 6−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.6 Socket Power-Management Register 6−9. . . . . . . . . . . . . . . . . . . . . . . . . .

7 Electrical Characteristics 7−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Absolute Maximum Ratings Over Operating Temperature Ranges 7−1.

7.2 Recommended Operating Conditions 7−2. . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Electrical Characteristics Over Recommended

Operating Conditions 7−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 PCI Clock/Reset Timing Requirements Over Recommended
Ranges of Supply Voltage and Operating Free-Air Temperature 7−3. . .

7.5 PCI Timing Requirements Over Recommended Ranges of

Supply Voltage and Operating Free-Air Temperature 7−4. . . . . . . . . . . . .

8 Mechanical Information 8−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

List of Illustrations

Figure Title Page

2−1 PCI1520 GHK-Package Terminal Diagram 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 PCI1520 PDV-Package Terminal Diagram 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 PCI1520 Simplified Block Diagram 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 3-State Bidirectional Buffer 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 TPS222X Typical Application 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Zoomed Video Implementation Using the PCI1520 3−6. . . . . . . . . . . . . . . . . . . .

3−5 Zoomed Video Switching Application 3−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 Sample Application of SPKROUT and CAUDPWM 3−10. . . . . . . . . . . . . . . . . . . .

3−7 Two Sample LED Circuits 3−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 Serial EEPROM Application 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−9 Serial-Bus Start/Stop Conditions and Bit Transfers 3−12. . . . . . . . . . . . . . . . . . . .

3−10 Serial-Bus Protocol Acknowledge 3−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 Serial-Bus Protocol − Byte Write 3−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 Serial-Bus Protocol − Byte Read 3−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 EEPROM Interface Doubleword Data Collection 3−13. . . . . . . . . . . . . . . . . . . . .

3−14 IRQ Implementation 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−15 Signal Diagram of Suspend Function 3−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−16 RI_OUT

3−17 Block Diagram of a Status/Enable Cell 3−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−1 ExCA Register Access Through I/O 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 ExCA Register Access Through Memory 5−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 Accessing CardBus Socket Registers Through PCI Memory 6−1. . . . . . . . . . . .

Functional Diagram 3−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

List of Tables

Table Title Page

2−1 Signal Names by PDV Terminal Number 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Signal Names by GHK Terminal Number 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 CardBus PC Card Signal Names Sorted Alphabetically 2−7. . . . . . . . . . . . . . . .

2−4 16-Bit PC Card Signal Names Sorted Alphabetically 2−9. . . . . . . . . . . . . . . . . . .

2−5 Power Supply Terminals 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 PC Card Power Switch Terminals 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 PCI System Terminals 2−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 PCI Address and Data Terminals 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 PCI Interface Control Terminals 2−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 Multifunction and Miscellaneous Terminals 2−15. . . . . . . . . . . . . . . . . . . . . . . . . .

2−11 16-Bit PC Card Address and Data Terminals (Slots A and B) 2−16. . . . . . . . . .

2−12 16-Bit PC Card Interface Control Terminals (Slots A and B) 2−17. . . . . . . . . . . .

2−13 CardBus PC Card Interface System Terminals (Slots A and B) 2−19. . . . . . . . .

2−14 CardBus PC Card Address and Data Terminals (Slots A and B) 2−20. . . . . . . .

2−15 CardBus PC Card Interface Control Terminals (Slots A and B) 2−21. . . . . . . . .

3−1 PC Card Card-Detect and Voltage-Sense Connections 3−4. . . . . . . . . . . . . . . .

3−2 Power Switch Options 3−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−3 Functionality of the ZV Output Signals 3−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−4 Zoomed-Video Card Interrogation 3−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−5 Integrated Pullup Resistors 3−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−6 CardBus Socket Registers 3−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−7 Register- and Bit-Loading Map 3−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−8 PCI1520 Registers Used to Program Serial-Bus Devices 3−15. . . . . . . . . . . . . . .

3−9 Interrupt Mask and Flag Registers 3−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−10 PC Card Interrupt Events and Description 3−16. . . . . . . . . . . . . . . . . . . . . . . . . . .

3−11 Interrupt Pin Register Cross Reference 3−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−12 SMI Control 3−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−13 Requirements for Internal/External 2.5-V Core Power Supply 3−19. . . . . . . . . .

3−14 Power-Management Registers 3−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 PCI Configuration Registers (Functions 0 and 1) 4−1. . . . . . . . . . . . . . . . . . . . . .

4−2 Bit Field Access Tag Descriptions 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 Command Register Description 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 Status Register Description 4−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 Secondary Status Register Description 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−6 Interrupt Pin Register Cross-Reference 4−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−7 Bridge Control Register Description 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−8 System Control Register Description 4−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

4−9 Multifunction Routing Register Description 4−19. . . . . . . . . . . . . . . . . . . . . . . . . . .

4−10 Retry Status Register Description 4−21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−11 Card Control Register Description 4−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−12 Device Control Register Description 4−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−13 Diagnostic Register Description 4−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−14 Power-Management Capabilities Register Description 4−26. . . . . . . . . . . . . . . .

4−15 Power-Management Control/Status Register Description 4−27. . . . . . . . . . . . . .

4−16 Power-Management Control/Status Register Bridge Support

Extensions Description 4−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−17 General-Purpose Event Status Register Description 4−29. . . . . . . . . . . . . . . . . .

4−18 General-Purpose Event Enable Register Description 4−30. . . . . . . . . . . . . . . . .

4−19 General-Purpose Input Register Description 4−31. . . . . . . . . . . . . . . . . . . . . . . . .

4−20 General-Purpose Output Register Description 4−32. . . . . . . . . . . . . . . . . . . . . . .

4−21 Serial-Bus Data Register Description 4−32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−22 Serial-Bus Index Register Description 4−33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−23 Serial-Bus Slave Address Register Description 4−33. . . . . . . . . . . . . . . . . . . . . .

4−24 Serial-Bus Control and Status Register Description 4−34. . . . . . . . . . . . . . . . . . .

5−1 ExCA Registers and Offsets 5−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−2 ExCA Identification and Revision Register Description 5−5. . . . . . . . . . . . . . . . .

5−3 ExCA Interface Status Register Description 5−6. . . . . . . . . . . . . . . . . . . . . . . . . .

5−4 ExCA Power Control Register Description—82365SL Support 5−7. . . . . . . . . .

5−5 ExCA Power Control Register Description—82365SL-DF Support 5−7. . . . . . .

5−6 ExCA Interrupt and General Control Register Description 5−8. . . . . . . . . . . . . .

5−7 ExCA Card Status-Change Register Description 5−9. . . . . . . . . . . . . . . . . . . . . .

5−8 ExCA Card Status-Change Interrupt Configuration

Register Description 5−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−9 ExCA Address Window Enable Register Description 5−11. . . . . . . . . . . . . . . . . . .

5−10 ExCA I/O Window Control Register Description 5−12. . . . . . . . . . . . . . . . . . . . . .

5−11 ExCA Memory Windows 0−4 Start-Address High-Byte Registers

Description 5−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−12 ExCA Memory Windows 0−4 End-Address High-Byte Registers

Description 5−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers

Description 5−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5−14 ExCA Card Detect and General Control Register Description 5−21. . . . . . . . . .

5−15 ExCA Global Control Register Description 5−22. . . . . . . . . . . . . . . . . . . . . . . . . .

6−1 CardBus Socket Registers 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−2 Socket Event Register Description 6−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−3 Socket Mask Register Description 6−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−4 Socket Present-State Register Description 6−4. . . . . . . . . . . . . . . . . . . . . . . . . . .

6−5 Socket Force Event Register Description 6−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−6 Socket Control Register Description 6−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6−7 Socket Power-Management Register Description 6−9. . . . . . . . . . . . . . . . . . . . .

ix

x

1 Introduction

1.1 Description

The Texas Instruments PCI1520, a 208-terminal dual-slot CardBus controller designed to meet the PCI Bus Power
Management Interface Specification for PCI to CardBus Bridges, is an ultralow-power high-performance

PCI-to-CardBus controller that supports two independent card sockets compliant with the PC Card Standard (rev.

7.1). The PCI1520 provides features that make it the best choice for bridging between PCI and PC Cards in both
notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in
PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at
33 MHz. The PCI1520 supports any combination of 16-bit and CardBus PC Cards in the two sockets, powered at
5 V or 3.3 V, as required.

The PCI1520 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master
device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging transactions. The
PCI1520 is also compliant with PCI Bus Power Management Interface Specification (rev. 1.1).

All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1520 is
register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The PCI1520 internal data path logic
allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent
buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The
PCI1520 can also be programmed to accept fast posted writes to improve system-bus utilization.

Multiple system-interrupt signaling options are provided, including parallel PCI, parallel ISA, serialized ISA, and
serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement
sideband functions. Many other features designed into the PCI1520, such as socket activity light-emitting diode (LED)
outputs, are discussed in detail throughout the design specification.

An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption
while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management
system to further reduce power consumption.

1.2 Features

The PCI1520 supports the following features:

• A 208-terminal low-profile QFP (PDV) or 209-terminal MicroStar BGA ball-grid array (GHK/ZHK) package

• 2.5-V core logic and 3.3-V I/O with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling

environments

• Integrated low-dropout voltage regulator (LDO-VR) eliminates the need for an external 2.5-V power supply

• Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards

• Two PC Card or CardBus slots with hot insertion and removal

• Serial interface to TI TPS222X dual-slot PC Card power switch

• Burst transfers to maximize data throughput with CardBus Cards

• Interrupt configurations: parallel PCI, serialized PCI, parallel ISA, and serialized ISA

• Serial EEPROM interface for loading subsystem ID and subsystem vendor ID

• Pipelined architecture for greater than 130-Mbps throughput from CardBus-to-PCI and from

PCI-to-CardBus

1−1

• Up to five general-purpose I/Os

• Programmable output select for CLKRUN

• Multifunction PCI device with separate configuration space for each socket

• Five PCI memory windows and two I/O windows available for each 16-bit interface

• Two I/O windows and two memory windows available to each CardBus socket

• Exchangeable-card-architecture- (ExCA-) compatible registers are mapped in memory and I/O space

• Intel 82365SL-DF and 82365SL register compatible

• Ring indicate, SUSPEND

, PCI CLKRUN, and CardBus CCLKRUN

• Socket activity LED terminals

• PCI bus lock (LOCK

)

• Advanced quarter-micron, ultralow-power CMOS technology

• Internal ring oscillator

1.3 Related Documents

• Advanced Configuration and Power Interface (ACPI) Specification (revision 1.1)

• PCI Bus Power Management Interface Specification (revision 1.1)

• PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (revision 0.6)

• PCI to PCMCIA CardBus Bridge Register Description (Yenta) (revision 2.1)

• PCI Local Bus Specification (revision 2.2)

• PCI Mobile Design Guide (revision 1.0)

• PC Card Standard (revision 7.1)

• PC 2001

• Serialized IRQ Support for PCI Systems (revision 6)

1.4 Trademarks

Intel is a trademark of Intel Corporation.
TI and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.

1.5 Ordering Information

ORDERING NUMBER NAME VOLTAGE PACKAGE

PCI1520 PC Card controller 3.3 V, 5-V tolerant I/Os 208-terminal LQFP

209-ball PBGA

PCI1520I PC Card controller,

industrial temperature

1−2

3.3 V, 5-V tolerant I/Os 208-terminal LQFP
209-ball PBGA

1.6 PCI1520 Data Manual Document History

DATE PAGE NUMBER REVISION

01/2003 2−1 Corrected part number typo in the first sentence of the page
01/2003 2−15 Corrected description of EEPROM detection scheme. EEPROM detection happens on

01/2003 3−2 Added new subsection 3.4.1 to describe GRST during power up
12/2003 3−3 Corrected bit description of SUBSYSRW bit in the system control register
01/2003 3−13 Modified byte-read diagram (Figure 3−12) to better reflect a read transaction to the EEPROM
01/2003 3−23 Modified description of power management capabilities register. This register is not a static

01/2003 4−13 Corrected default value for interrupt pin register
01/2003 4−26 Corrected default value for power management capabilities register
01/2003 5−13 Corrected typo on register description for ExCA I/O windows 0 and 1 start-address high-byte

01/2003 5−24 Corrected typo on the bit type for ExCA memory 0−4 page register
01/2003 6−8 Corrected default value for socket control register
01/2003 6−8 Modified description for bit 10 in the socket control register
03/2004 Cover Added ZHK package to document title
03/2004 1−1 Added ZHK package to text
03/2004 2−1 Added ZHK package to text
03/2004 8−1 Added ZHK package to text
03/2004 8−2 Added ZHK mechanical

deassertion of GRST

read-only register.

register

rather than PRST.

1−3

1−4

2 Terminal Descriptions

The PCI1520 is available in three packages, a 208-terminal quad flatpack (PDV) and two 209-terminal MicroStar
BGA packages (GHK/ZHK). The GHK and ZHK packages are mechanically and electrically identical, but the ZHK
is a lead-free (Pb, atomic number 82) design. Throughout the remainder of this manual (except Chapter 8), only the
GHK designator is used for either the GHK or ZHK package. The terminal layout for the GHK package is shown in
Figure 2−1. The terminal layout with signal names for the PDV package is shown in Figure 2−2.

GHK PLASTIC BALL GRID ARRAY (PBGA) PACKAGE

BOTTOM VIEW

W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A

2

1

75634

18

19171613 14 1511 129810

Figure 2−1. PCI1520 GHK-Package Terminal Diagram

2−1

I)

M

PDV LOW-PROFILE QUAD FLAT PACKAGE

(LQFP)

TOP VIEW

/RI)

)

//A_CD2

156 MFUNC0

155 DATA

154 CLOCK

153 LATCH

152 SPKROUT

151 A_CAD31//A_D10

150 A_RSVD//A_D2

149 A_CAD30//A_D9

148 A_CAD29//A_D1

147 GND

146 A_CAD28//A_D8

145 A_CAD27//A_D0

MFUNC1 157

SUSPEND

MFUNC2 159

MFUNC3/IRQSER 160

MFUNC4 161
MFUNC5 162

FUNC6/CLKRUN 163

RI_OUT

DEVSEL 198

C/BE3 164

/PME 165

GND 166

AD25 167

PRST

GNT

REQ 170
AD31 171
AD30 172
AD11 173

V

CC

AD29 175
AD28 176

GRST

AD27 178
AD26 179
V

CCP

AD24 181

PCLK 182

IDSEL 183

AD23 184

GND 185
AD22 186
AD21 187
AD20 188
AD19 189
AD18 190
AD17 191
AD16 192

C/BE2

FRAME

V

CC

IRDY

TRDY

GND 199

STOP
PERR
SERR

PAR 203

C/BE1

AD15 205
AD14 206
AD13 207
AD12 208

158

168
169

174

177

180

193
194
195
196
197

200
201
202

204

AD9 2

AD10 1

4

AD8 3

AD7 5

AD6 7

AD5 8

GND 6

C/BE0

144 A_CCD2

AD4 9

AD3 10

AD2 11

AD1 12

AD0 13

//A_WAIT

139 A_CSERR

143 VCC142 A_CCLKRUN//A_WP(IOIS16)

141 A_CSTSCHG//A_BVD1(STSCHG

138 A_CINT//A_READY(IREQ)

140 A_CAUDIO//A_BVD2(SPKR

137 A_CVS1//A_VS1

14

CC

V

//B_CD1 15

B_CAD0//B_D3 16

B_CAD3//B_D5 20

B_CAD1//B_D4 18

B_CAD2//B_D11 17

B_CAD4//B_D12 19

B_CCD1

136 A_CAD26//A_A0

135 A_CAD25//A_A1

B_CAD5//B_D6 22

B_CAD6//B_D13 21

134 A_CAD24//A_A2

133 VCC132 A_CC/BE3//A_REG

131 A_CAD23//A_A3

PCI1520

GND 24

B_CAD7//B_D7 25

B_CAD8//B_D15 26

B_RSVD//B_D14 23

//A_INPACK

A_CAD22//A_A4

130 A_CREQ

129

128 VR_PORT

29

VR_EN

//B_CE1 27

B_CAD9//B_A10 28

B_CC/BE0

//A_RESET

125 A_CAD20//A_A6

127 A_CAD21//A_A5

126 A_CRST

30

B_CAD11//B_OE 31

B_CAD12//B_A11 32

B_CAD10//B_CE2

//A_A12

124 A_CVS2//A_VS2

123 A_CAD19//A_A25

122 A_CAD18//A_A7

121 A_CAD17//A_A24

120 A_CC/BE2

33

34

//B_A8 37

B_CAD14//B_A9 35

B_CC/BE1

B_CAD16//B_A17 36

B_CAD13//B_IORD

B_CAD15//B_IOWR

CC

A_CFRAME//A_A23

119

118 V

39

CC

V

B_RSVD//B_A18 38

//A_A22

117 A_CIRDY//A_A15

116 A_CTRDY

//B_A19 41

B_CPAR//B_A13 40

B_CBLOCK

CCA

115 A_CCLK//A_A16

114 V

113 A_CDEVSEL//A_A21

GND 43

//B_A20 44

//B_A14 42

B_CSTOP

B_CPERR

//A_A20

//A_WE

111 A_CSTOP

112 A_CGNT

//B_WE 45

//B_A21 46

B_CGNT

B_CDEVSEL

//A_A14

A_CPERR

110 GND

109

47

CCB

V

B_CCLK//B_A16 48

//A_A19

//A_A8

107 A_CPAR//A_A13

106 A_RSVD//A_A18

105 A_CC/BE1

108 A_CBLOCK

104 A_CAD16//A_A17
103 A_CAD14//A_A9
102 A_CAD15//A_IOWR
101 A_CAD13//A_IORD
100 A_CAD12//A_A11

99 A_CAD11//A_OE
98 A_CAD10//A_CE2
97 A_CAD9//A_A10
96 A_CC/BE0//A_CE1
95 GND
94 A_CAD8//A_D15
93 A_CAD7//A_D7
92 A_RSVD//A_D14
91 V

CC

90 A_CAD5//A_D6
89 A_CAD6//A_D13
88 A_CAD3//A_D5
87 A_CAD4//A_D12
86 A_CAD1//A_D4
85 A_CAD2//A_D11
84 A_CAD0//A_D3
83 A_CCD1
82 B_CAD31//B_D10
81 NC
80 B_RSVD//B_D2
79 B_CAD30//B_D9
78 B_CAD29//B_D1
77

B_CAD28//B_D8
76 B_CAD27//B_D0
75 B_CCD2
74 B_CCLKRUN//B_WP(IOIS16)
73 B_CSTSCHG//B_BVD1(STSCHG
72 B_CAUDIO//B_BVD2(SPKR)
71 B_CSERR
70 V

CC

69 B_CINT
68 B_CVS1//B_VS1
67

B_CAD26//B_A0
66 B_CAD25//B_A1
65 B_CAD24//B_A2
64 B_CC/BE3
63 B_CAD23//B_A3
62 GND
61 B_CREQ
60 B_CAD22//B_A4
59 B_CAD21//B_A5
58 B_CRST

B_CAD20//B_A6

57
56 B_CVS2//B_VS2
55 B_CAD19//B_A25
54 B_CAD18//B_A7
53 B_CAD17//B_A24

//B_A23 51

//B_A12 52

//B_A22 49

B_CIRDY//B_A15 50

B_CTRDY

B_CC/BE2

B_CFRAME

//A_CD1

//B_CD2

/R

//B_WAIT

//B_READY(IREQ)

//B_REG

//B_INPACK

//B_RESET

2−2

Figure 2−2. PCI1520 PDV-Package Terminal Diagram

Table 2−1 and Table 2−2 list the terminal assignments arranged in terminal-number order, with corresponding signal

TERM.

TERM.

TERM.

names for both CardBus and 16-bit PC Cards; Table 2−1 is for terminals on the PDV package and Table 2−2 is for
terminals on the GHK package. Table 2−3 and Table 2−4 list the terminal assignments arranged in alphanumerical
order by signal name, with corresponding terminal numbers for both PDV and GHK packages; Table 2−3 is for
CardBus signal names and Table 2−4 is for 16-bit PC Card signal names.

Terminal E5 on the GHK package is an identification ball used for device orientation; it has no internal connection
within the device.

Table 2−1. Signal Names by PDV Terminal Number

SIGNAL NAME

NO.

10 AD3 AD3 47 V
11 AD2 AD2 48 B_CCLK B_A16 85 A_CAD2 A_D11
12 AD1 AD1 49 B_CTRDY B_A22 86 A_CAD1 A_D4
13 AD0 AD0 50 B_CIRDY B_A15 87 A_CAD4 A_D12
14 V
15 B_CCD1 B_CD1 52 B_CC/BE2 B_A12 89 A_CAD6 A_D13
16 B_CAD0 B_D3 53 B_CAD17 B_A24 90 A_CAD5 A_D6
17 B_CAD2 B_D11 54 B_CAD18 B_A7 91 V
18 B_CAD1 B_D4 55 B_CAD19 B_A25 92 A_RSVD A_D14
19 B_CAD4 B_D12 56 B_CVS2 B_VS2 93 A_CAD7 A_D7
20 B_CAD3 B_D5 57 B_CAD20 B_A6 94 A_CAD8 A_D15
21 B_CAD6 B_D13 58 B_CRST B_RESET 95 GND GND
22 B_CAD5 B_D6 59 B_CAD21 B_A5 96 A_CC/BE0 A_CE1
23 B_RSVD B_D14 60 B_CAD22 B_A4 97 A_CAD9 A_A10
24 GND GND 61 B_CREQ B_INPACK 98 A_CAD10 A_CE2
25 B_CAD7 B_D7 62 GND GND 99 A_CAD11 A_OE
26 B_CAD8 B_D15 63 B_CAD23 B_A3 100 A_CAD12 A_A11
27 B_CC/BE0 B_CE1 64 B_CC/BE3 B_REG 101 A_CAD13 A_IORD
28 B_CAD9 B_A10 65 B_CAD24 B_A2 102 A_CAD15 A_IOWR
29 VR_EN VR_EN 66 B_CAD25 B_A1 103 A_CAD14 A_A9
30 B_CAD10 B_CE2 67 B_CAD26 B_A0 104 A_CAD16 A_A17
31 B_CAD11 B_OE 68 B_CVS1 B_VS1 105 A_CC/BE1 A_A8
32 B_CAD12 B_A11 69 B_CINT B_READY(IREQ) 106 A_RSVD A_A18
33 B_CAD13 B_IORD 70 V
34 B_CAD15 B_IOWR 71 B_CSERR B_WAIT 108 A_CBLOCK A_A19
35 B_CAD14 B_A9 72 B_CAUDIO B_BVD2(SPKR) 109 A_CPERR A_A14
36 B_CAD16 B_A17 73 B_CSTSCHG B_BVD1(STSCHG/RI) 110 GND GND
37 B_CC/BE1 B_A8 74 B_CCLKRUN B_WP(IOIS16) 111 A_CSTOP A_A20

†

Terminal 81 is an NC on the PCI1520 to allow for terminal compatibility with the next generation of devices.

CardBus

PC Card

1 AD10 AD10 38 B_RSVD B_A18 75 B_CCD2 B_CD2
2 AD9 AD9 39 V
3 AD8 AD8 40 B_CPAR B_A13 77 B_CAD28 B_D8
4 C/BE0 C/BE0 41 B_CBLOCK B_A19 78 B_CAD29 B_D1
5 AD7 AD7 42 B_CPERR B_A14 79 B_CAD30 B_D9
6 GND GND 43 GND GND 80 B_RSVD B_D2
7 AD6 AD6 44 B_CSTOP B_A20 81 NC
8 AD5 AD5 45 B_CGNT B_WE 82 B_CAD31 B_D10
9 AD4 AD4 46 B_CDEVSEL B_A21 83 A_CCD1 A_CD1

CC

16-Bit

PC Card

V

CC

NO.

51 B_CFRAME B_A23 88 A_CAD3 A_D5

CardBus

PC Card

SIGNAL NAME

CC

CCB

CC

16-Bit

PC Card

V

CC

V

CCB

V

CC

SIGNAL NAME

NO.

76 B_CAD27 B_D0

84 A_CAD0 A_D3

107 A_CPAR A_A13

CardBus

PC Card

†

CC

16-Bit

PC Card

†

NC

V

CC

2−3

Table 2−1. Signal Names by PDV Terminal Number (Continued)

TERM.

TERM.

TERM.

SIGNAL NAME

NO.

112 A_CGNT A_WE 145 A_CAD27 A_D0 178 AD27 AD27
113 A_CDEVSEL A_A21 146 A_CAD28 A_D8 179 AD26 AD26
114 V
115 A_CCLK A_A16 148 A_CAD29 A_D1 181 AD24 AD24
116 A_CTRDY A_A22 149 A_CAD30 A_D9 182 PCLK PCLK
117 A_CIRDY A_A15 150 A_RSVD A_D2 183 IDSEL IDSEL
118 V
119 A_CFRAME A_A23 152 SPKROUT SPKROUT 185 GND GND
120 A_CC/BE2 A_A12 153 LATCH LATCH 186 AD22 AD22
121 A_CAD17 A_A24 154 CLOCK CLOCK 187 AD21 AD21
122 A_CAD18 A_A7 155 DATA DATA 188 AD20 AD20
123 A_CAD19 A_A25 156 MFUNC0 MFUNC0 189 AD19 AD19
124 A_CVS2 A_VS2 157 MFUNC1 MFUNC1 190 AD18 AD18
125 A_CAD20 A_A6 158 SUSPEND SUSPEND 191 AD17 AD17
126 A_CRST A_RESET 159 MFUNC2 MFUNC2 192 AD16 AD16
127 A_CAD21 A_A5 160 MFUNC3/IRQSER MFUNC3/IRQSER 193 C/BE2 C/BE2
128 VR_PORT VR_PORT 161 MFUNC4 MFUNC4 194 FRAME FRAME
129 A_CAD22 A_A4 162 MFUNC5 MFUNC5 195 V
130 A_CREQ A_INPACK 163 MFUNC6/CLKRUN MFUNC6/CLKRUN 196 IRDY IRDY
131 A_CAD23 A_A3 164 C/BE3 C/BE3 197 TRDY TRDY
132 A_CC/BE3 A_REG 165 RI_OUT/PME RI_OUT/PME 198 DEVSEL DEVSEL
133 V
134 A_CAD24 A_A2 167 AD25 AD25 200 STOP STOP
135 A_CAD25 A_A1 168 PRST PRST 201 PERR PERR
136 A_CAD26 A_A0 169 GNT GNT 202 SERR SERR
137 A_CVS1 A_VS1 170 REQ REQ 203 PAR PAR
138 A_CINT A_READY(IREQ) 171 AD31 AD31 204 C/BE1 C/BE1
139 A_CSERR A_WAIT 172 AD30 AD30 205 AD15 AD15
140 A_CAUDIO A_BVD2(SPKR) 173 AD11 AD11 206 AD14 AD14
141 A_CSTSCHG A_BVD1(STSCHG/

142 A_CCLKRUN A_WP(IOIS16) 175 AD29 AD29 208 AD12 AD12
143 V
144 A_CCD2 A_CD2 177 GRST GRST

CardBus

PC Card

CCA

CC

CC

CC

16-Bit

PC Card

V

CCA

V

CC

V

CC

)

RI

V

CC

NO.

147 GND GND 180 V

151 A_CAD31 A_D10 184 AD23 AD23

166 GND GND 199 GND GND

174 V

176 AD28 AD28

CardBus

PC Card

CC

SIGNAL NAME

16-Bit

PC Card

V

CC

SIGNAL NAME

NO.

207 AD13 AD13

CardBus

PC Card

CCP

CC

16-Bit

PC Card

V

CCP

V

CC

2−4

Table 2−2. Signal Names by GHK Terminal Number

TERM.

TERM.

TERM.

SIGNAL NAME

NO.

A04 AD12 AD12 E07 PERR PERR H06 AD2 AD2
A05 PAR PAR E08 FRAME FRAME H14 A_CSTSCHG A_BVD1(STSCHG/RI)
A06 GND GND E09 AD19 AD19 H15 A_CCLKRUN A_WP(IOIS16)
A07 V
A08 AD18 AD18 E11 AD27 AD27 H18 A_CSERR A_WAIT
A09 GND GND E12 AD31 AD31 H19 A_CINT A_READY(IREQ)
A10 V
A11 AD29 AD29 E14 MFUNC2 MFUNC2 J02 B_CAD3 B_D5
A12 V
A13 REQ REQ E18 LATCH LATCH J05 B_CAD5 B_D6
A14 GND GND E19 A_CAD31 A_D10 J06 B_RSVD B_D14
A15 MFUNC5 MFUNC5 F01 AD3 AD3 J14 A_CAD26 A_A0
A16 MFUNC1 MFUNC1 F02 AD5 AD5 J15 A_CVS1 A_VS1
B05 AD15 AD15 F03 AD6 AD6 J17 A_CAD25 A_A1
B06 STOP STOP F05 AD8 AD8 J18 A_CAD24 A_A2
B07 IRDY IRDY F06 C/BE1 C/BE1 J19 V
B08 AD17 AD17 F07 DEVSEL DEVSEL K01 GND GND
B09 AD22 AD22 F08 C/BE2 C/BE2 K02 B_CAD7 B_D7
B10 AD24 AD24 F09 AD20 AD20 K03 B_CAD8 B_D15
B11 AD28 AD28 F10 AD23 AD23 K05 B_CC/BE0 B_CE1
B12 AD11 AD11 F11 AD26 AD26 K06 B_CAD9 B_A10
B13 GNT GNT F12 AD25 AD25 K14 A_CC/BE3 A_REG
B14 C/BE3 C/BE3 F13 MFUNC3/IRQSER MFUNC3/IRQSER K15 A_CAD23 A_A3
B15 MFUNC4 MFUNC4 F14 SPKROUT SPKROUT K17 A_CREQ A_INPACK
C05 AD13 AD13 F15 CLOCK CLOCK K18 A_CAD22 A_A4
C06 SERR SERR F17 A_RSVD A_D2 K19 VR_PORT VR_PORT
C07 TRDY TRDY F18 A_CAD29 A_D1 L01 VR_EN VR_EN
C08 AD16 AD16 F19 GND GND L02 B_CAD10 B_CE2
C09 AD21 AD21 G01 V
C10 PCLK PCLK G02 AD0 AD0 L05 B_CAD13 B_IORD
C11 GRST GRST G03 AD1 AD1 L06 B_CAD12 B_A11
C12 AD30 AD30 G05 AD4 AD4 L14 A_CAD21 A_A5
C13 PRST PRST G06 C/BE0 C/BE0 L15 A_CRST A_RESET
C14 MFUNC6/

C15 SUSPEND SUSPEND G15 A_CAD30 A_D9 L18 A_CVS2 A_VS2
D01 AD10 AD10 G17 A_CAD27 A_D0 L19 A_CAD19 A_A25
D19 MFUNC0 MFUNC0 G18 A_CCD2 A_CD2 M01 B_CAD15 B_IOWR
E01 GND GND G19 V
E02 AD7 AD7 H01 B_CAD1 B_D4 M03 B_CAD16 B_A17
E03 AD9 AD9 H02 B_CAD2 B_D11 M05 B_RSVD B_A18
E05 NC NC H03 B_CAD0 B_D3 M06 B_CC/BE1 B_A8
E06 AD14 AD14 H05 B_CCD1 B_CD1 M14 A_CCLK A_A16

CardBus
PC Card

CC

CCP

CC

CLKRUN

16-Bit

PC Card

V

CC

V

CCP

V

CC

MFUNC6/

CLKRUN

NO.

E10 IDSEL IDSEL H17 A_CAUDIO A_BVD2(SPKR)

E13 RI_OUT/PME RI_OUT/PME J01 B_CAD4 B_D12

E17 DATA DATA J03 B_CAD6 B_D13

G14 A_CAD28 A_D8 L17 A_CAD20 A_A6

CardBus

PC Card

CC

CC

SIGNAL NAME

16-Bit

PC Card

V

CC

V

CC

SIGNAL NAME

NO.

L03 B_CAD11 B_OE

M02 B_CAD14 B_A9

CardBus

PC Card

CC

16-Bit

PC Card

V

CC

2−5

Table 2−2. Signal Names by GHK Terminal Number (Continued)

TERM.

TERM.

TERM.

SIGNAL NAME

NO.

M15 A_CFRAME A_A23 P17 A_CSTOP A_A20 U13 A_CAD7 A_D7
M17 A_CC/BE2 A_A12 P18 A_CGNT A_WE U14 A_CAD10 A_CE2
M18 A_CAD17 A_A24 P19 V
M19 A_CAD18 A_A7 R01 V
N01 V
N02 B_CPAR B_A13 R03 B_CFRAME B_A23 V07 B_CAD24 B_A2
N03 B_CBLOCK B_A19 R06 B_CAD19 B_A25 V08 B_CINT B_READY(IREQ)
N05 B_CGNT B_WE R07 B_CREQ B_INPACK V09 B_CAUDIO B_BVD2(SPKR)
N06 B_CPERR B_A14 R08 B_CAD26 B_A0 V10 B_CAD28 B_D8
N14 A_CBLOCK A_A19 R09 B_CCLKRUN B_WP(IOIS16) V11 B_CAD31 B_D10
N15 A_CDEVSEL A_A21 R10 B_CAD30 B_D9 V12 A_CAD4 A_D12
N17 A_CTRDY A_A22 R11 A_CAD2 A_D11 V13 A_RSVD A_D14
N18 A_CIRDY A_A15 R12 A_CAD5 A_D6 V14 A_CC/BE0 A_CE1
N19 V
P01 GND GND R14 A_CAD15 A_IOWR W04 B_CAD17 B_A24
P02 B_CSTOP B_A20 R17 A_RSVD A_A18 W05 B_CRST B_RESET
P03 B_CDEVSEL B_A21 R18 A_CPERR A_A14 W06 GND GND
P05 B_CIRDY B_A15 R19 GND GND W07 B_CAD25 B_A1
P06 B_CCLK B_A16 T01 B_CC/BE2 B_A12 W08 V
P07 B_CVS2 B_VS2 T19 A_CC/BE1 A_A8 W09 B_CSERR B_WAIT
P08 B_CAD23 B_A3 U05 B_CAD18 B_A7 W10 B_CAD27 B_D0
P09 B_CCD2 B_CD2 U06 B_CAD21 B_A5 W11 NC
P10 B_RSVD B_D2 U07 B_CC/BE3 B_REG W12 A_CAD1 A_D4
P11 A_CAD0 A_D3 U08 B_CVS1 B_VS1 W13 V
P12 A_CAD6 A_D13 U09 B_CSTSCHG B_BVD1(STSCHG/RI) W14 GND GND
P13 A_CAD8 A_D15 U10 B_CAD29 B_D1 W15 A_CAD11 A_OE
P14 A_CAD12 A_A11 U11 A_CCD1 A_CD1 W16 A_CAD16 A_A17
P15 A_CPAR A_A13 U12 A_CAD3 A_D5

†

Terminal W11 is an NC on the PCI1520 to allow for terminal compatibility with the next generation of devices.

CardBus

PC Card

CC

CC

16-Bit

PC Card

V

CC

V

CC

NO.

R02 B_CTRDY B_A22 V06 B_CAD22 B_A4

R13 A_CAD9 A_A10 V15 A_CAD13 A_IORD

CardBus

PC Card

SIGNAL NAME

CCA
CCB

16-Bit

PC Card

V

CCA

V

CCB

SIGNAL NAME

NO.

U15 A_CAD14 A_A9
V05 B_CAD20 B_A6

CardBus

PC Card

CC

†

CC

16-Bit

PC Card

V

CC

NC

V

CC

†

2−6

Table 2−3. CardBus PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

TERM NO.

PDV GHK

A_CAD0 84 P11 A_CDEVSEL 113 N15 AD24 181 B10
A_CAD1 86 W12 A_CFRAME 119 M15 AD25 167 F12
A_CAD2 85 R11 A_CGNT 112 P18 AD26 179 F11
A_CAD3 88 U12 A_CINT 138 H19 AD27 178 E11
A_CAD4 87 V12 A_CIRDY 117 N18 AD28 176 B11
A_CAD5 90 R12 A_CPAR 107 P15 AD29 175 A11
A_CAD6 89 P12 A_CPERR 109 R18 AD30 172 C12
A_CAD7 93 U13 A_CREQ 130 K17 AD31 171 E12
A_CAD8 94 P13 A_CRST 126 L15 B_CAD0 16 H03

A_CAD9 97 R13 A_CSERR 139 H18 B_CAD1 18 H01
A_CAD10 98 U14 A_CSTOP 111 P17 B_CAD2 17 H02
A_CAD11 99 W15 A_CSTSCHG 141 H14 B_CAD3 20 J02
A_CAD12 100 P14 A_CTRDY 116 N17 B_CAD4 19 J01
A_CAD13 101 V15 A_CVS1 137 J15 B_CAD5 22 J05
A_CAD14 103 U15 A_CVS2 124 L18 B_CAD6 21 J03
A_CAD15 102 R14 A_RSVD 106 R17 B_CAD7 25 K02
A_CAD16 104 W16 A_RSVD 92 V13 B_CAD8 26 K03
A_CAD17 121 M18 A_RSVD 150 F17 B_CAD9 28 K06
A_CAD18 122 M19 AD0 13 G02 B_CAD10 30 L02
A_CAD19 123 L19 AD1 12 G03 B_CAD11 31 L03
A_CAD20 125 L17 AD2 11 H06 B_CAD12 32 L06
A_CAD21 127 L14 AD3 10 F01 B_CAD13 33 L05
A_CAD22 129 K18 AD4 9 G05 B_CAD14 35 M02
A_CAD23 131 K15 AD5 8 F02 B_CAD15 34 M01
A_CAD24 134 J18 AD6 7 F03 B_CAD16 36 M03
A_CAD25 135 J17 AD7 5 E02 B_CAD17 53 W04
A_CAD26 136 J14 AD8 3 F05 B_CAD18 54 U05
A_CAD27 145 G17 AD9 2 E03 B_CAD19 55 R06
A_CAD28 146 G14 AD10 1 D01 B_CAD20 57 V05
A_CAD29 148 F18 AD11 173 B12 B_CAD21 59 U06
A_CAD30 149 G15 AD12 208 A04 B_CAD22 60 V06
A_CAD31 151 E19 AD13 207 C05 B_CAD23 63 P08

A_CAUDIO 140 H17 AD14 206 E06 B_CAD24 65 V07

A_CBLOCK 108 N14 AD15 205 B05 B_CAD25 66 W07

A_CC/BE0 96 V14 AD16 192 C08 B_CAD26 67 R08
A_CC/BE1 105 T19 AD17 191 B08 B_CAD27 76 W10
A_CC/BE2 120 M17 AD18 190 A08 B_CAD28 77 V10
A_CC/BE3 132 K14 AD19 189 E09 B_CAD29 78 U10

A_CCD1 83 U11 AD20 188 F09 B_CAD30 79 R10

A_CCD2 144 G18 AD21 187 C09 B_CAD31 82 V11

A_CCLK 115 M14 AD22 186 B09 B_CAUDIO 72 V09

A_CCLKRUN 142 H15 AD23 184 F10 B_CBLOCK 41 N03

TERM. NO.

PDV GHK

TERM. NO.

PDV GHK

2−7

Table 2−3. CardBus PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

TERM NO.

PDV GHK

B_CC/BE0 27 K05 C/BE2 193 F08 NC — E05
B_CC/BE1 37 M06 C/BE3 164 B14 NC
B_CC/BE2 52 T01 CLOCK 154 F15 PAR 203 A05
B_CC/BE3 64 U07 DATA 155 E17 PCLK 182 C10

B_CCD1 15 H05 DEVSEL 198 F07 PERR 201 E07
B_CCD2 75 P09 FRAME 194 E08 PRST 168 C13

B_CCLK 48 P06 GND 6 A06 REQ 170 A13
B_CCLKRUN 74 R09 GND 24 A09 RI_OUT/PME 165 E13
B_CDEVSEL 46 P03 GND 43 A14 SERR 202 C06

B_CFRAME 51 R03 GND 62 E01 SPKROUT 152 F14

B_CGNT 45 N05 GND 95 K01 STOP 200 B06

B_CINT 69 V08 GND 110 P01 SUSPEND 158 C15

B_CIRDY 50 P05 GND 147 R19 TRDY 197 C07

B_CPAR 40 N02 GND 166 W06 V

B_CPERR 42 N06 GND 185 F19 V

B_CREQ 61 R07 GND 199 W14 V

B_CRST 58 W05 GNT 169 B13 V

B_CSERR 71 W09 GRST 177 C11 V

B_CSTOP 44 P02 IDSEL 183 E10 V

B_CSTSCHG 73 U09 IRDY 196 B07 V

B_CTRDY 49 R02 LATCH 153 E18 V

B_CVS1 68 U08 MFUNC0 156 D19 V

B_CVS2 56 P07 MFUNC1 157 A16 V

B_RSVD 23 J06 MFUNC2 159 E14 V

B_RSVD 38 M05 MFUNC3/IRQSER 160 F13 V

B_RSVD 80 P10 MFUNC4 161 B15 VR_EN 29 L01

C/BE0 4 G06 MFUNC5 162 A15 VR_PORT 128 K19
C/BE1 204 F06 MFUNC6/CLKRUN 163 C14

†

Terminals 81 and W11 are NC on the PCI1520 to allow for terminal compatibility with the next generation of devices.

TERM NO.

PDV GHK

†

CC
CC
CC
CC
CC
CC
CC
CC

CC
CCA
CCB
CCP

TERM NO.

PDV GHK

81 W11

14 A07
39 A12
70 G01

91 G19
118 J19
133 N01
143 N19
174 W08
195 W13
114 P19

47 R01
180 A10

2−8

Table 2−4. 16-Bit PC Card Signal Names Sorted Alphabetically

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

TERM. NO.

PDV GHK

A_A0 136 J14 A_D10 151 E19 AD24 181 B10
A_A1 135 J17 A_D11 85 R11 AD25 167 F12
A_A2 134 J18 A_D12 87 V12 AD26 179 F11
A_A3 131 K15 A_D13 89 P12 AD27 178 E11
A_A4 129 K18 A_D14 92 V13 AD28 176 B11
A_A5 127 L14 A_D15 94 P13 AD29 175 A11
A_A6 125 L17 A_INPACK 130 K17 AD30 172 C12
A_A7 122 M19 A_IORD 101 V15 AD31 171 E12
A_A8 105 T19 A_IOWR 102 R14 B_A0 67 R08

A_A9 103 U15 A_OE 99 W15 B_A1 66 W07
A_A10 97 R13 A_READY(IREQ) 138 H19 B_A2 65 V07
A_A11 100 P14 A_REG 132 K14 B_A3 63 P08
A_A12 120 M17 A_RESET 126 L15 B_A4 60 V06
A_A13 107 P15 A_VS1 137 J15 B_A5 59 U06
A_A14 109 R18 A_VS2 124 L18 B_A6 57 V05
A_A15 117 N18 A_WAIT 139 H18 B_A7 54 U05
A_A16 115 M14 A_WE 112 P18 B_A8 37 M06
A_A17 104 W16 A_WP(IOIS16) 142 H15 B_A9 35 M02
A_A18 106 R17 AD0 13 G02 B_A10 28 K06
A_A19 108 N14 AD1 12 G03 B_A11 32 L06
A_A20 111 P17 AD2 11 H06 B_A12 52 T01
A_A21 113 N15 AD3 10 F01 B_A13 40 N02
A_A22 116 N17 AD4 9 G05 B_A14 42 N06
A_A23 119 M15 AD5 8 F02 B_A15 50 P05
A_A24 121 M18 AD6 7 F03 B_A16 48 P06
A_A25 123 L19 AD7 5 E02 B_A17 36 M03

A_BVD1(STSCHG/RI) 141 H14 AD8 3 F05 B_A18 38 M05

A_BVD2(SPKR) 140 H17 AD9 2 E03 B_A19 41 N03

A_CD1 83 U11 AD10 1 D01 B_A20 44 P02
A_CD2 144 G18 AD11 173 B12 B_A21 46 P03
A_CE1 96 V14 AD12 208 A04 B_A22 49 R02
A_CE2 98 U14 AD13 207 C05 B_A23 51 R03

A_D0 145 G17 AD14 206 E06 B_A24 53 W04

A_D1 148 F18 AD15 205 B05 B_A25 55 R06

A_D2 150 F17 AD16 192 C08 B_BVD1(STSCHG/RI) 73 U09

A_D3 84 P11 AD17 191 B08 B_BVD2(SPKR) 72 V09

A_D4 86 W12 AD18 190 A08 B_CD1 15 H05

A_D5 88 U12 AD19 189 E09 B_CD2 75 P09

A_D6 90 R12 AD20 188 F09 B_CE1 27 K05

A_D7 93 U13 AD21 187 C09 B_CE2 30 L02

A_D8 146 G14 AD22 186 B09 B_D0 76 W10

A_D9 149 G15 AD23 184 F10 B_D1 78 U10

TERM. NO.

PDV GHK

TERM NO.

PDV GHK

2−9

Table 2−4. 16-Bit PC Card Signal Names Sorted Alphabetically (Continued)

SIGNAL NAME

SIGNAL NAME

SIGNAL NAME

TERM NO.

PDV GHK

B_D2 80 P10 C/BE2 193 F08 NC — E05
B_D3 16 H03 C/BE3 164 B14 NC
B_D4 18 H01 CLOCK 154 F15 PAR 203 A05
B_D5 20 J02 DATA 155 E17 PCLK 182 C10
B_D6 22 J05 DEVSEL 198 F07 PERR 201 E07
B_D7 25 K02 FRAME 194 E08 PRST 168 C13
B_D8 77 V10 GND 6 A06 REQ 170 A13

B_D9 79 R10 GND 24 A09 RI_OUT/PME 165 E13
B_D10 82 V11 GND 43 A14 SERR 202 C06
B_D11 17 H02 GND 62 E01 SPKROUT 152 F14
B_D12 19 J01 GND 95 K01 STOP 200 B06
B_D13 21 J03 GND 110 P01 SUSPEND 158 C15
B_D14 23 J06 GND 147 R19 TRDY 197 C07
B_D15 26 K03 GND 166 W06 V

B_INPACK 61 R07 GND 185 F19 V

B_IORD 33 L05 GND 199 W14 V

B_IOWR 34 M01 GNT 169 B13 V

B_OE 31 L03 GRST 177 C11 V

B_READY(IREQ) 69 V08 IDSEL 183 E10 V

B_REG 64 U07 IRDY 196 B07 V

B_RESET 58 W05 LATCH 153 E18 V

B_VS1 68 U08 MFUNC0 156 D19 V
B_VS2 56 P07 MFUNC1 157 A16 V

B_WAIT 71 W09 MFUNC2 159 E14 V

B_WE 45 N05 MFUNC3/IRQSER 160 F13 V

B_WP(IOIS16) 74 R09 MFUNC4 161 B15 VR_EN 29 L01

C/BE0 4 G06 MFUNC5 162 A15 VR_PORT 128 K19
C/BE1 204 F06 MFUNC6/CLKRUN 163 C14

†

Terminals 81 and W11 are NC on the PCI1520 to allow for terminal compatibility with the next generation of devices.

TERM NO.

PDV GHK

†

CC
CC
CC
CC
CC
CC
CC
CC

CC
CCA
CCB
CCP

TERM NO.

PDV GHK

81 W11

14 A07
39 A12
70 G01

91 G19
118 J19
133 N01
143 N19
174 W08
195 W13
114 P19

47 R01
180 A10

2−10

The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc. The

NAME

I/O

DESCRIPTION

NAME

I/O

DESCRIPTION

terminal numbers are also listed for convenient reference.

Table 2−5. Power Supply Terminals

TERMINAL

NO.

PDV GHK

6, 24, 43, 62,

GND

V

CC

V

CCA

V

CCB

V

CCP

VR_EN 29 L01 I Internal voltage regulator enable. Active-low

VR_PORT 128 K19 I/O

95, 110, 147,
166, 185, 199

14, 39, 70, 91,
118, 133, 143,

174, 195

114 P19 −

47 R01 −

180 A10 − Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V

A06, A09, A14,
E01, F19, K01,

P01, R19, W06,

W14

A07, A12, G01,
G19, J19, N01,

N19, W08, W13

I/O DESCRIPTION

Device ground terminals

−

Power supply terminal for I/O and internal voltage regulator

−

Clamp voltage for PC Card A interface. Matches card A signaling environment, 5 V
or 3.3 V

Clamp voltage for PC Card B interface. Matches card B signaling environment, 5 V
or 3.3 V

Internal voltage regulator input/output. When VR_EN is low, the regulator is en­abled and this terminal is an output. An external bypass capacitor is required on this
terminal. When VR_EN is high, the regulator is disabled and this terminal is an input
for an external 2.5-V core power source.

Table 2−6. PC Card Power Switch Terminals

TERMINAL

NO.

PDV GHK

CLOCK 154 F15 I/O

DATA 155 E17 O

LATCH 153 E18 I/O

I/O DESCRIPTION

Power switch clock. Information on the DATA line is sampled at the rising edge of CLOCK. CLOCK defaults to
an input, but can be changed to a PCI1520 output by using bit 27 (P2CCLK) in the system control register
(offset 80h, see Section 4.29). The TPS222X defines the maximum frequency of this signal to be 2 MHz. How­ever, PCI1520 requires a 16-KHz to 100-KHz frequency range. If a system design defines this terminal as an
output, then this terminal requires an external pulldown resistor. The frequency of the PCI1520 output CLOCK
is derived from the internal ring oscillator (16 KHz typical).

Power switch data. DATA is used to communicate socket power control information serially to the power
switch.

Power switch latch. LATCH is asserted by the PCI1520 to indicate to the power switch that the data on the
DATA line is valid. When a pulldown resistor is implemented on this terminal, the MFUNC1 and MFUNC4 ter­minals provide the serial EEPROM SDA and SCL interface.

2−11

TERMINAL

NAME

I/O

DESCRIPTION

NO.

PDV GHK

GRST 177 C11 I

PCLK 182 C10 I

PRST

168 C13 I

Table 2−7. PCI System Terminals

I/O DESCRIPTION

Global reset. When the global reset is asserted, the GRST signal causes the PCI1520 to place all output
buffers in a high-impedance state and reset all internal registers. When GRST
completely in its default state. For systems that require wake-up from D3, GRST
during initial boot. PRST
transition from D3 to D0. For systems that do not require wake-up from D3, GRST
When the SUSPEND
preserved. All outputs are placed in a high-impedance state.

PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the
rising edge of PCLK.

PCI reset. When the PCI bus reset is asserted, PRST causes the PCI1520 to place all output buffers in a
high-impedance state and reset internal registers. When PRST
signal only if it is enabled. After PRST is deasserted, the PCI1520 is in a default state.
When the SUSPEND
preserved. All outputs are placed in a high-impedance state.

should be asserted following initial boot so that PME context is retained during the

mode is enabled, the device is protected from GRST, and the internal registers are

is asserted, the device can generate the PME

mode is enabled, the device is protected from PRST, and the internal registers are

is asserted, the device is

normally is asserted only

should be tied to PRST.

2−12

TERMINAL

NAME

I/O

DESCRIPTION

NO.

PDV GHK

AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10

AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0

C/BE3
C/BE2
C/BE1
C/BE0

PAR 203 A05 I/O

171
172
175
176
178
179
167
181
184
186
187
188
189
190
191
192
205
206
207
208
173

1
2
3
5
7
8

9
10
11
12
13

164
193
204

4

E12
C12

A11
B11
E11

F11
F12
B10
F10
B09
C09
F09
E09
A08
B08
C08
B05
E06
C05
A04
B12
D01
E03
F05
E02
F03
F02
G05
F01
H06
G03
G02

B14
F08
F06
G06

Table 2−8. PCI Address and Data T erminals

I/O DESCRIPTION

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary-bus PCI cycle, AD31−AD0 contain a 32-bit address or

I/O

other destination information. During the data phase, AD31−AD0 contain data.

PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During
the address phase of a primary-bus PCI cycle, C/BE3
phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit

I/O

data bus carry meaningful data. C/BE0
C/BE2

applies to byte 2 (AD23−AD16), and C/BE3 applies to byte 3 (AD31−AD24).

PCI-bus parity. In all PCI-bus read and write cycles, the PCI1520 calculates even parity across the
AD31−AD0 and C/BE3
indicator with a one-PCLK delay. As a target during PCI cycles, the PCI1520 compares its calculated parity
to the parity indicator of the initiator. A compare error results in the assertion of a parity error (PERR).

−C/BE0 buses. As an initiator during PCI cycles, the PCI1520 outputs this parity

applies to byte 0 (AD7−AD0), C/BE1 applies to byte 1 (AD15−AD8),

−C/BE0 define the bus command. During the data

2−13

TERMINAL

NAME

I/O

DESCRIPTION

NO.

PDV GHK

DEVSEL

FRAME

GNT

IDSEL 183 E10 I

IRDY

PERR

REQ

SERR

STOP

TRDY

198 F07 I/O

194 E08 I/O

169 B13 I

196 B07 I/O

201 E07 I/O
170 A13 O PCI bus request. REQ is asserted by the PCI1520 to request access to the PCI bus as an initiator.

202 C06 O

200 B06 I/O

197 C07 I/O

Table 2−9. PCI Interface Control T erminals

I/O DESCRIPTION

PCI device select. The PCI1520 asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator
on the bus, the PCI1520 monitors DEVSEL
occurs, then the PCI1520 terminates the cycle with an initiator abort.

PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus
transaction is beginning, and data transfers continue while this signal is asserted. When FRAME
deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. GNT is driven by the PCI bus arbiter to grant the PCI1520 access to the PCI bus after the
current data transaction has completed. GNT
bus parking algorithm.

Initialization device select. IDSEL selects the PCI1520 during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the
transaction. A data phase is completed on a rising edge of PCLK where both IRDY
Until IRDY

PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match
PAR when PERR

PCI system error. SERR is an output that is pulsed from the PCI1520 when enabled through bit 8 of the
command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The PCI1520
need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register,
this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.

PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. STOP
support burst data transfers.

PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of
the transaction. A data phase is completed on a rising edge of PCLK when both IRDY
Until both IRDY

and TRDY are both sampled asserted, wait states are inserted.

is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4).

is used for target disconnects and is commonly asserted by target devices that do not

and TRDY are asserted, wait states are inserted.

until a target responds. If no target responds before timeout

may or may not follow a PCI bus request, depending on the PCI

and TRDY are asserted.

and TRDY are asserted.

is

2−14

TERMINAL

NAME

I/O

DESCRIPTION

NO.

PDV GHK

MFUNC0 156 D19 I/O

MFUNC1 157 A16 I/O

MFUNC2 159 E14 I/O

MFUNC3/

IRQSER

MFUNC4 161 B15 I/O

MFUNC5 162 A15 I/O

MFUNC6/

CLKRUN

NC

RI_OUT/PME 165 E13 O

SPKROUT

SUSPEND 158 C15 I

160 F13 I/O

163 C14 I/O

—81E05

W11

152 F14 O

Table 2−10. Multifunction and Miscellaneous Terminals

I/O DESCRIPTION

Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0, socket
activity LED output, ZV switching output, CardBus audio PWM, GPE
Section 4.30, Multifunction Routing Register, for configuration details.

Multifunction terminal 1. MFUNC1 can be configured as parallel PCI interrupt INTB, GPI1, GPO1, socket
activity LED output, ZV switching output, CardBus audio PWM, GPE
Section 4.30, Multifunction Routing Register, for configuration details.

Serial data (SDA). When LA TCH is detected low after the deassertion of GRST
provides the SDA signaling for the serial bus interface. The two-terminal serial interface loads the
subsystem identification and other register defaults from an EEPROM after a PCI reset. See
Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.

Multifunction terminal 2. MFUNC2 can be configured as GPI2, GPO2, socket activity LED output, ZV
switching output, CardBus audio PWM, GPE
Multifunction Routing Register, for configuration details.

Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal
IRQSER. This terminal is IRQSER by default. See Section 4.30, Multifunction Routing Register, for
configuration details.

Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED
output, ZV switching output, CardBus audio PWM, GPE
Section 4.30, Multifunction Routing Register, for configuration details.

Serial clock (SCL). When LA TCH is detected low after the deassertion of GRST, the MFUNC4 terminal
provides the SCL signaling for the serial bus interface. The two-terminal serial interface loads the
subsystem identification and other register defaults from an EEPROM after a PCI reset. See
Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.

Multifunction terminal 5. MFUNC5 can be configured as GPI4, GPO4, socket activity LED output, ZV
switching output, CardBus audio PWM, D3_STAT
Multifunction Routing Register, for configuration details.

Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See
Section 4.30, Multifunction Routing Register, for configuration details.

No connect. These terminals have no connection anywhere within the package. Terminal E05 on the
GHK package is used as a key to indicate the location of the A1 corner of the BGA package. Terminals
W11 on the GHK package and 81 on the PDV package will be used as a 48-MHz clock input on
future-generation devices.

Ring indicate out and power management event output. This terminal provides an output for ring-indicate
or PME

signals.

Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through
the PCI1520 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card
SPKR//CAUDIO inputs.

Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST signal is
asserted. See Section 3.8.5, Suspend Mode, for details.

, RI_OUT, D3_STAT, or a parallel IRQ. See Section 4.30,

, D3_STAT, RI_OUT, or a parallel IRQ. See

, GPE, or a parallel IRQ. See Section 4.30,

, or a parallel IRQ. See

, or a parallel IRQ. See

, the MFUNC1 terminal

2−15

Table 2−11. 16-Bit PC Card Address and Data Terminals (Slots A and B)

I/O

DESCRIPTION

NAME

TERMINAL

NUMBER

†

NAME

A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12

A11

A10

A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

D15
D14
D13
D12

D11

D10

D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

†

Terminal name for slot A is preceded with A_. For example, the full name for terminals 123 and L19 is A_A25.

‡

Terminal name for slot B is preceded with B_. For example, the full name for terminals 55 and R06 is B_A25.

SLOT A

PDV

123
121
119
116
113

111
108
106
104
115
117
109
107
120
100

97
103
105
122
125
127
129
131
134
135
136

94

92

89

87

85
151
149
146

93

90

88

86

84
150
148
145

GHK

L19
M18
M15
N17
N15
P17
N14
R17
W16
M14
N18
R18
P15
M17
P14
R13
U15

T19

M19

L17

L14
K18
K15

J18

J17

J14
P13

V13
P12
V12
R11
E19
G15
G14
U13
R12
U12
W12

P11

F17

F18
G17

PDV

55
53
51
49
46
44
41
38
36
48
50
42
40
52
32
28
35
37
54
57
59
60
63
65
66
67

26
23
21
19
17
82
79
77
25
22
20
18
16
80
78
76

SLOT B

‡

GHK

R06

W04

R03
R02
P03
P02

N03
M05
M03

P06

P05

N06

N02

T01

L06

K06
M02
M06

U05

V05

U06

V06

P08

V07
W07

R08

K03

J06
J03

J01
H02
V11
R10
V10
K02

J05

J02
H01
H03
P10
U10

W10

O PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.

I/O PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.

2−16