TEXAS INSTRUMENTS PCI1510R Technical data
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查询PCI1510R供应商
PCI1510R GVF/ZVF PC Card
Controllers
Data Manual
Literature Number: SCPS114
December 2004
Printed on Recycled Pape
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Contents
Section Page
1 PCI1510R Features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Introduction 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Controller Functional Description 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Related Documents 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Trademarks 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Document Conventions 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Ordering Information 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 PCI1510R Data Manual Document History 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Terminal Assignments 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Terminal Descriptions 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Principles of Operation 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Power Supply Sequencing 19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 I/O Characteristics 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Clamping Voltages 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Peripheral Component Interconnect (PCI) Interface 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.1 PCI GRST Signal 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.2 PCI Bus Lock (LOCK) 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4.3 Loading Subsystem Identification 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 PC Card Applications 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.1 PC Card Insertion/Removal and Recognition 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.2 Parallel Power-Switch Interface (TPS2211A) 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.3 Zoomed Video Support 23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.4 Standardized Zoomed-Video Register Model 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.5 Internal Ring Oscillator 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.6 Integrated Pullup Resistors 25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.7 SPKROUT and CAUDPWM Usage 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.8 LED Socket Activity Indicators 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5.9 CardBus Socket Registers 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Serial-Bus Interface 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Serial-Bus Interface Implementation 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.2 Serial-Bus Interface Protocol 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.3 Serial-Bus EEPROM Application 30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.4 Accessing Serial-Bus Devices Through Software 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Programmable Interrupt Subsystem 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.1 PC Card Functional and Card Status Change Interrupts 32 . . . . . . . . . . . . . . . . . . . . . .
3.7.2 Interrupt Masks and Flags 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.3 Using Parallel IRQ Interrupts 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.4 Using Parallel PCI Interrupts 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.5 Using Serialized IRQSER Interrupts 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7.6 SMI Support in the Controller 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Power Management Overview 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1 Integrated Low-Dropout Voltage Regulator (LDO-VR) 36 . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2 Clock Run Protocol 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3 CardBus PC Card Power Management 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.4 16-Bit PC Card Power Management 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.5 Suspend Mode 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.6 Requirements for Suspend Mode 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
December 2004 SCPS114
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Contents
Section Page
3.8.7 Ring Indicate 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.8 PCI Power Management 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.9 CardBus Bridge Power Management 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.10 ACPI Support 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.11 Master List of PME Context Bits and Global Reset-Only Bits 41 . . . . . . . . . . . . . . . . . .
4 PC Card Controller Programming Model 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1 PCI Configuration Registers 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Vendor ID Register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Device ID Register 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4 Command Register 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.5 Status Register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.6 Revision ID Register 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.7 PCI Class Code Register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.8 Cache Line Size Register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.9 Latency Timer Register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.10 Header Type Register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.11 BIST Register 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.12 CardBus Socket/ExCA Base-Address Register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.13 Capability Pointer Register 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.14 Secondary Status Register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.15 PCI Bus Number Register 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.16 CardBus Bus Number Register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.17 Subordinate Bus Number Register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.18 CardBus Latency Timer Register 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.19 Memory Base Registers 0, 1 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.20 Memory Limit Registers 0, 1 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.21 I/O Base Registers 0, 1 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.22 I/O Limit Registers 0, 1 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.23 Interrupt Line Register 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.24 Interrupt Pin Register 53 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.25 Bridge Control Register 54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.26 Subsystem Vendor ID Register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.27 Subsystem ID Register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.28 PC Card 16-Bit I/F Legacy-Mode Base Address Register 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.29 System Control Register 56 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.30 Multifunction Routing Register 58 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.31 Retry Status Register 59 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.32 Card Control Register 60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.33 Device Control Register 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.34 Diagnostic Register 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.35 Capability ID Register 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.36 Next-Item Pointer Register 62 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.37 Power-Management Capabilities Register 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.38 Power-Management Control/Status Register 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.39 Power-Management Control/Status Register Bridge Support Extensions 65 . . . . . . . . . . . . . . . . .
4.40 Power-Management Data Register 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.41 General-Purpose Event Status Register 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.42 General-Purpose Event Enable Register 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.43 General-Purpose Input Register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.44 General-Purpose Output Register 68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.45 Serial-Bus Data Register 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.46 Serial-Bus Index Register 69 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.47 Serial-Bus Slave Address Register 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.48 Serial-Bus Control and Status Register 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 ExCA Compatibilty Registers 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 ExCA Identification and Revision Register 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 ExCA Interface Status Register 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 ExCA Power Control Register 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 ExCA Interrupt and General Control Register 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 ExCA Card Status-Change Register 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6 ExCA Card Status-Change Interrupt Configuration Register 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7 ExCA Address Window Enable Register 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.8 ExCA I/O Window Control Register 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9 ExCA I/O Windows 0 and 1 Start-Address Low-Byte Registers 83 . . . . . . . . . . . . . . . . . . . . . . . . . .
5.10 ExCA I/O Windows 0 and 1 Start-Address High-Byte Registers 83 . . . . . . . . . . . . . . . . . . . . . . . . .
5.11 ExCA I/O Windows 0 and 1 End-Address Low-Byte Registers 83 . . . . . . . . . . . . . . . . . . . . . . . . . .
5.12 ExCA I/O Windows 0 and 1 End-Address High-Byte Registers 83 . . . . . . . . . . . . . . . . . . . . . . . . . .
5.13 ExCA Memory Windows 0−4 Start-Address Low-Byte Registers 84 . . . . . . . . . . . . . . . . . . . . . . . .
5.14 ExCA Memory Windows 0−4 Start-Address High-Byte Registers 84 . . . . . . . . . . . . . . . . . . . . . . . .
5.15 ExCA Memory Windows 0−4 End-Address Low-Byte Registers 85 . . . . . . . . . . . . . . . . . . . . . . . . .
5.16 ExCA Memory Windows 0−4 End-Address High-Byte Registers 85 . . . . . . . . . . . . . . . . . . . . . . . . .
5.17 ExCA Memory Windows 0−4 Offset-Address Low-Byte Registers 86 . . . . . . . . . . . . . . . . . . . . . . .
5.18 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers 86 . . . . . . . . . . . . . . . . . . . . . . .
5.19 ExCA Card Detect and General Control Register 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.20 ExCA Global Control Register 88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.21 ExCA I/O Windows 0 and 1 Offset-Address Low-Byte Registers 89 . . . . . . . . . . . . . . . . . . . . . . . .
5.22 ExCA I/O Windows 0 and 1 Offset-Address High-Byte Registers 89 . . . . . . . . . . . . . . . . . . . . . . . .
5.23 ExCA Memory Windows 0−4 Page Registers 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 CardBus Socket Registers 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1 Socket Event Register 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Socket Mask Register 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3 Socket Present-State Register 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4 Socket Force Event Register 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5 Socket Control Register 96 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.6 Socket Power-Management Register 97 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 Electrical Characteristics 98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1 Absolute Maximum Ratings Over Operating Temperature Ranges 98 . . . . . . . . . . . . . . . . . . . . . . .
7.2 Recommended Operating Conditions 99 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.3 Electrical Characteristics Over Recommended Operating Conditions 100 . . . . . . . . . . . . . . . . . . . .
7.4 PCI Clock/Reset Timing Requirements Over Recommended Ranges of Supply Voltage and
Operating Free-Air Temperature 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5 PCI Timing Requirements Over Recommended Ranges of Supply Voltage and Operating Free-Air
Temperature 101 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Mechanical Data 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
December 2004 SCPS114
v
Figures
List of Figures
Figure Page
2−1 PCI1510R GVF Package Terminal Diagram 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 PCI1510R Simplified Block Diagram 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 3-State Bidirectional Buffer 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 TPS2211A Typical Application 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 Zoomed Video Implementation Using the PCI1510R Controller 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Zoomed Video Switching Application 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 Sample Application of SPKROUT and CAUDPWM 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Two Sample LED Circuits 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 Serial EEPROM Application 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 Serial-Bus Start/Stop Conditions and Bit Transfers 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Serial-Bus Protocol Acknowledge 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Serial-Bus Protocol − Byte Write 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−12 Serial-Bus Protocol − Byte Read 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−13 EEPROM Interface Doubleword Data Collection 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−14 IRQ Implementation 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−15 Signal Diagram of Suspend Function 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−16 RI_OUT Functional Diagram 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−17 Block Diagram of a Status/Enable Cell 41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Register Access Through I/O 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Register Access Through Memory 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 Accessing CardBus Socket Registers Through PCI Memory 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
vi
December 2004SCPS114
List of Tables
Table Page
2−1 Signal Names Sorted by GVF Terminal Number 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−2 CardBus PC Card Signal Names Sorted Alphabetically to GVF Terminals 8. . . . . . . . . . . . . . . . . . .
2−3 16-Bit PC Card Signal Names Sorted Alphabetically to GVF Terminals 9. . . . . . . . . . . . . . . . . . . . . .
2−4 Power Supply Terminals 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−5 PC Card Power Switch Terminals 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−6 PCI System Terminals 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−7 PCI Address and Data Terminals 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−8 PCI Interface Control Terminals 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−9 Multifunction and Miscellaneous Terminals 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−10 16-Bit PC Card Address and Data Terminals 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−11 16-Bit PC Card Interface Control Terminals 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−12 CardBus PC Card Interface System Terminals 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−13 CardBus PC Card Address and Data Terminals 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2−14 CardBus PC Card Interface Control Terminals 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−1 PC Card Card-Detect and Voltage-Sense Connections 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 Zoomed-Video Card Interrogation 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−3 Integrated Pullup Resistors 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−4 CardBus Socket Registers 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−5 Register- and Bit-Loading Map 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−6 PCI1510R Registers Used to Program Serial-Bus Devices 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−7 Interrupt Mask and Flag Registers 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−8 PC Card Interrupt Events and Description 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−9 SMI Control 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−10 Requirements for Internal/External 2.5-V Core Power Supply 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−11 Power-Management Registers 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−1 PCI Configuration Registers 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−2 Bit Field Access Tag Descriptions 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−3 Command Register Description 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−4 Status Register Description 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−5 Secondary Status Register Description 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−6 Bridge Control Register Description 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−7 System Control Register Description 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Multifunction Routing Register Description 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−9 Retry Status Register Description 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−10 Card Control Register Description 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−11 Device Control Register Description 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 Diagnostic Register Description 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−13 Power-Management Capabilities Register Description 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 Power-Management Control/Status Register Description 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−15 Power-Management Control/Status Register Bridge Support Extensions Description 65. . . . . . . . . .
4−16 General-Purpose Event Status Register Description 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 General-Purpose Event Enable Register Description 67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 General-Purpose Input Register Description 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−19 General-Purpose Output Register Description 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−20 Serial-Bus Data Register Description 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−21 Serial-Bus Index Register Description 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−22 Serial-Bus Slave Address Register Description 70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
December 2004 SCPS114
vii
Tables
Table Page
4−23 Serial-Bus Control and Status Register Description 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−1 ExCA Registers and Offsets 73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 ExCA Identification and Revision Register Description 75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−3 ExCA Interface Status Register Description 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 ExCA Power Control Register Description—82365SL Support 77. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−5 ExCA Power Control Register Description—82365SL-DF Support 77. . . . . . . . . . . . . . . . . . . . . . . . . .
5−6 ExCA Interrupt and General Control Register Description 78. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−7 ExCA Card Status-Change Register Description 79. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−8 ExCA Card Status-Change Interrupt Configuration Register Description 80. . . . . . . . . . . . . . . . . . . . .
5−9 ExCA Address Window Enable Register Description 81. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−10 ExCA I/O Window Control Register Description 82. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−11 ExCA Memory Windows 0−4 Start-Address High-Byte Registers Description 84. . . . . . . . . . . . . . . .
5−12 ExCA Memory Windows 0−4 End-Address High-Byte Registers Description 85. . . . . . . . . . . . . . . . .
5−13 ExCA Memory Windows 0−4 Offset-Address High-Byte Registers Description 86. . . . . . . . . . . . . . .
5−14 ExCA Card Detect and General Control Register Description 87. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−15 ExCA Global Control Register Description 88. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−1 CardBus Socket Registers 90. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−2 Socket Event Register Description 91. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−3 Socket Mask Register Description 92. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−4 Socket Present-State Register Description 93. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−5 Socket Force Event Register Description 95. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−6 Socket Control Register Description 96. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6−7 Socket Power-Management Register Description 97. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
viii
December 2004SCPS114
1 PCI1510R Features
Features
D A 253-Terminal MicroStar BGAE Ball-Grid
Array (GVF/ZVF) Package
D 2.5-V Core Logic and 3.3-V I/O with
Universal PCI Interfaces Compatible with
3.3-V and 5-V PCI Signaling Environments
D Integrated Low-Dropout Voltage Regulator
(LDO-VR) Eliminates the Need for an
External 2.5-V Power Supply
D Mix-and-Match 5-V/3.3-V 16-Bit PC Cards
and 3.3-V CardBus Cards
D A Single PC Card or CardBus Slot with Hot
Insertion and Removal
D Parallel Interface to TI TPS2211A
Single-Slot PC Card Power Switch
D Burst Transfers to Maximize Data
Throughput with CardBus Cards
D Interrupt Configurations: Parallel PCI,
Serialized PCI, Parallel ISA, and Serialized
ISA
D Serial EEPROM Interface for Loading
Subsystem ID, Subsystem Vendor ID, and
other Configuration Registers
D Pipelined Architecture for Greater Than
130-Mbps Throughput from CardBus-to-PCI
and from PCI-to-CardBus
D Up to Five General-Purpose I/Os
D Programmable Output Select for CLKRUN
D Five PCI Memory Windows and Two I/O
Windows Available for the 16-Bit Interface
D Two I/O Windows and Two Memory
Windows Available to the CardBus Socket
D Exchangeable-Card-Architecture- (ExCA-)
Compatible Registers Are Mapped in
Memory and I/O Space
D IntelE 82365SL-DF and 82365SL Register
Compatible
D Ring Indicate, SUSPEND, PCI CLKRUN, and
CardBus CCLKRUN
D Socket Activity LED Terminal
D PCI Bus Lock (LOCK)
D Internal Ring Oscillator
T able 1−1.
Figure 1−1.
MicroStar BGA is a trademark of Texas Instruments.
Other trademarks are the property of their respective owners.
December 2004 SCPS114
1
Introduction
2 Introduction
The Texas Instruments PCI1510R device, a 144-terminal, 209-terminal, or 253-terminal single-slot CardBus
controller designed to meet the PCI Bus Power Management Interface Specification for PCI to CardBus
Bridges, is an ultralow-power high-performance PCI-to-CardBus controller that supports a single PC card
socket compliant with the PC Card Standard (rev. 7.2). The controller provides features that make it the best
choice for bridging between PCI and PC Cards in both notebook and desktop computers. The PC Card
Standard retains the 16-bit PC Card specification defined in the PCI Local Bus Specification and defines the
32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The controller supports both 16-bit
and CardBus PC Cards, powered at 5 V or 3.3 V, as required.
2.1 Controller Functional Description
The controller is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI
master device or a PCI slave device. The PCI bus mastering is initiated during CardBus PC Card bridging
transactions. The controller is also compliant with PCI Bus Power Management Interface Specification (rev.
1.1).
All card signals are internally buffered to allow hot insertion and removal without external buffering. The
controller is register-compatible with the Intel 82365SL-DF and 82365SL ExCA controllers. The controller
internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for
maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed
performance level with sustained bursting. The controller can also be programmed to accept fast posted writes
to improve system-bus utilization.
Multiple system-interrupt signaling options are provided, including parallel PCI, parallel ISA, serialized ISA,
and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to
implement sideband functions. Many other features designed into the controller, such as a socket activity
light-emitting diode (LED) outputs, are discussed in detail throughout this document.
An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power
consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host
power management system to further reduce power consumption.
2.2 Related Documents
• Advanced Configuration and Power Interface (ACPI) Specification (revision 1.1)
• PCI Bus Power Management Interface Specification (revision 1.1)
• PCI Bus Power Management Interface Specification for PCI to CardBus Bridges (revision 0.6)
• PCI to PCMCIA CardBus Bridge Register Description (Yenta) (revision 2.1)
• PCI Local Bus Specification (revision 2.2)
• PCI Mobile Design Guide (revision 1.0)
• PC Card Standard (revision 7.2)
• Serialized IRQ Support for PCI Systems (revision 6)
2.3 Trademarks
Intel is a trademark of Intel Corporation.
TI and MicroStar BGA are trademarks of Texas Instruments.
Other trademarks are the property of their respective owners.
2
December 2004SCPS114
2.4 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are
listed below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary
field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a
12-bit hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number are
assumed to be decimal format.
Introduction
4. If the signal or terminal name has a bar above the name (for example, GRST
logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. RSVD indicates that the referenced item is reserved.
6. In Sections 4 through 6, the configuration space for the controller is defined. For each register bit, the
software access method is identified in an access column. The legend for this access column includes
the following entries:
r – read-only access
ru – read-only access with updates by the controller internal hardware
rw – read and write access
rcu – read access with the option to clear an asserted bit with a write-back of 1b including updates
by the controller internal hardware.
2.5 Ordering Information
ORDERING NUMBER NAME VOLTAGE PACKAGE
PCI1510R PC Card controller 3.3 V, 5-V tolerant I/Os 253-ball PBGA (GVF or ZVF)
2.6 PCI1510R Data Manual Document History
DATE PAGE NUMBER REVISION
11/2004 All Initial release
), then this indicates the
2.7 Terminal Assignments
The PCI1510R controller is available in two 253-terminal MicroStar BGA packages (GVF/ZVF). The GVF
and ZVF packages are mechanically and electrically identical, but the ZVF is a lead-free (Pb, atomic number
82) design. Throughout the remainder of this manual, only the GVF package designator is used for either the
GVF or ZVF package. The terminal layout for the GVF package is shown in Figure 2−1.
Table 2−1 lists the terminal assignments for the GVF package. The signal names for the PC Card slot are given
in a CardBus // 16-bit signal format. Table 2−1 is arranged in order by increasing terminal designator, which
is alphanumeric for this package. Table 2−2 and Table 2−3 list the CardBus and 16-bit signal names,
respectively, in alphanumerical order with the corresponding terminal number for the package.
December 2004 SCPS114
3
É
Introduction
GVF PACKAGE
(TOP VIEW)
19
18
17
16
15
14
13
12
11
10
NNNN N
N
NNNNNNNNN
N
NNNNNNNNN N NNNN
NN
NNNNNN
N
NNN
N
NNN
C
N NNN
N
CCC
CC
CC
CC
9
8
7
6
5
C
CC
CC
CC
CC
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
CC
T
T
MM
N
N
NNN N
NN
P
P
P
P
P
P
P
P
P
P
P
P
P
N
NNN
P
P
P
P
P
P
P
P
N
N
N
NN
NN
P
P
P
P
P
P
P
P
P
P
P
PP
P
P
4
3
2
C
C
C
1
C
C
CC
CC
CC
C
NNN
C
N
C
N
NN NNNNNN
N
N
NN
N
N
N
N
NN
M
M
T
M
T
M
M
PPP
P
PPPP
PPP
PPPP
ABCDEFGHJKLMNPRTUVW
P
PCI Interface
C
PC Card Interface
T
TPS Power Switch
M
MFUNC Pins
VCC
Ground (GND)
Miscellaneous
N
No Connection
Figure 2−1. PCI1510R GVF Package Terminal Diagram
4
December 2004SCPS114
Table 2−1. Signal Names Sorted by GVF Terminal Number
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
A02 CAUDIO BVD2(SPKR) C08 CFRAME A23
A03 CVS1 VS1 C09 CDEVSEL A21
A04 CAD25 A1 C10 CRSVD A18
A05 V
A06 CRST RESET C12 CAD11 OE
A07 CAD17 A24 C13 CAD7 D7
A08 CTRDY A22 C14 CAD4 D12
A09 CSTOP A20 C15 CCD1 CD1
A10 CAD16 A17 C16 NC NC
A11 V
A12 CAD9 A10 C18 NC NC
A13 CAD5 D6 C19 NC NC
A14 CAD2 D11 D01 CAD31 D10
A15 NC NC D02 CRSVD D2
A16 NC NC D03 CAD29 D1
A17 NC NC D17 NC NC
A18 NC NC D18 NC NC
B01 CAD27 D0 D19 NC NC
B02 CSTSCHG BVD1(STSCHG/RI) E01 NC NC
B03 CSERR WAIT E02 NC NC
B04 CAD26 A0 E03 NC NC
B05 CAD23 A3 E05 CCD2 CD2
B06 CAD21 A5 E06 CAD24 A2
B07 CAD18 A7 E07 CREQ INPACK
B08 CIRDY A15 E08 CVS2 VS2
B09 CGNT WE E09 CCLK A16
B10 CC/BE1 A8 E10 CBLOCK A19
B11 CAD12 A11 E11 CAD15 IOWR
B12 CAD10 CE2 E12 CAD8 D15
B13 CRSVD D14 E13 CAD3 D5
B14 CAD1 D4 E14 CAD0 D3
B15 NC NC E17 NC NC
B16 NC NC E18 NC NC
B17 NC NC E19 NC NC
B18 NC NC F01 NC NC
B19 NC NC F02 NC NC
C01 CAD30 D9 F03 NC NC
C02 CAD28 D8 F09 CC/BE2 A12
C03 CCLKRUN WP(IOIS16) F10 CPERR A14
C04 CINT READY(IREQ) F12 CAD6 D13
C05 CC/BE3 REG F17 NC NC
C06 CAD22 A4 F18 NC NC
C07 CAD19 A25 F19 NC NC
CCCB
CCCB
V
CCCB
V
CCCB
C11 CAD13 IORD
C17 NC NC
CARDBUS 16-BIT
SIGNAL NAME
Introduction
December 2004 SCPS114
5
Introduction
TERMINAL
TERMINAL
Table 2−1. Signal Names Sorted by GVF Terminal Number (Continued)
SIGNAL NAME
CARDBUS 16-BIT
G01 NC NC K12 V
G02 NC NC K17 NC NC
G03 NC NC K18 NC NC
G07 GND GND K19 NC NC
G08 GND GND L01 NC NC
G09 CAD20 A6 L02 NC NC
G10 CPAR A13 L03 NC NC
G11 CAD14 A9 L05 VCCD1 VCCD1
G12 CC/BE0 CE1 L06 VCCD0 VCCD0
G13 GND GND L07 SPKROUT SPKROUT
G17 NC NC L08 GND GND
G18 NC NC L09 GND GND
G19 NC NC L10 GND GND
H01 NC NC L11 GND GND
H02 VR_EN VR_EN L12 GND GND
H03 NC NC L17 NC NC
H08 V
H09 V
H10 V
H11 V
H12 V
H13 GND GND M05 MFUNC1 MFUNC1
H17 NC NC M07 V
H18 NC NC M08 GND GND
H19 NC NC M09 V
J01 NC NC M10 V
J02 NC NC M12 V
J03 NC NC M17 NC NC
J08 V
J09 GND GND M19 VR_PORT VR_PORT
J10 GND GND N01 VPPD1 VPPD1
J11 GND GND N02 VPPD0 VPPD0
J12 V
J17 NC NC N05 MFUNC5 MFUNC5
J18 NC NC N07 V
J19 NC NC N08 DEVSEL DEVSEL
K01 NC NC N09 AD12 AD12
K02 NC NC N10 AD8 AD8
K03 NC NC N11 AD1 AD1
K08 V
K09 GND GND N18 NC NC
K10 GND GND N19 NC NC
K11 GND GND P01 MFUNC2 MFUNC2
CC
CC
CC
CC
CC
CC
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
L18 NC NC
L19 NC NC
M01 NC NC
M02 NC NC
M03 NC NC
M18 NC NC
N03 MFUNC0 MFUNC0
N17 NC NC
CARDBUS 16-BIT
CC
CC
CC
CC
CC
CC
SIGNAL NAME
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
6
December 2004SCPS114
Table 2−1. Signal Names Sorted by GVF Terminal Number (Continued)
TERMINAL
TERMINAL
SIGNAL NAME
CARDBUS 16-BIT
P02 MFUNC3 MFUNC3 U16 NC NC
P03 MFUNC4 MFUNC4 U17 NC NC
P05 PCLK PCLK U18 NC NC
P06 AD20 AD20 U19 NC NC
P09 PAR PAR V01 AD30 AD30
P17 NC NC V02 AD29 AD29
P18 NC NC V03 AD26 AD26
P19 NC NC V04 AD24 AD24
R01 MFUNC6 MFUNC6 V05 AD23 AD23
R02 SUSPEND SUSPEND V06 AD18 AD18
R03 PRST PRST V07 FRAME FRAME
R06 AD21 AD21 V08 PERR PERR
R07 AD16 AD16 V09 AD15 AD15
R08 TRDY TRDY V10 AD11 AD11
R09 AD13 AD13 V11 AD7 AD7
R10 AD9 AD9 V12 AD3 AD3
R11 AD5 AD5 V13 NC NC
R17 NC NC V14 NC NC
R18 NC NC V15 NC NC
R19 NC NC V16 NC NC
T01 GRST GRST V17 NC NC
T02 GNT GNT V18 NC NC
T03 RI_OUT/PME RI_OUT/PME V19 NC NC
T17 NC NC W02 AD27 AD27
T18 NC NC W03 V
T19 NC NC W04 C/BE3 C/BE3
U01 REQ REQ W05 IDSEL IDSEL
U02 AD31 AD31 W06 AD19 AD19
U03 AD28 AD28 W07 C/BE2 C/BE2
U04 AD25 AD25 W08 STOP STOP
U05 AD22 AD22 W09 C/BE1 C/BE1
U06 AD17 AD17 W10 V
U07 IRDY IRDY W11 C/BE0 C/BE0
U08 SERR SERR W12 AD4 AD4
U09 AD14 AD14 W13 AD0 AD0
U10 AD10 AD10 W14 NC NC
U11 AD6 AD6 W15 NC NC
U12 AD2 AD2 W16 NC NC
U13 NC NC W17 NC NC
U14 NC NC W18 NC NC
U15 NC NC
CARDBUS 16-BIT
CCP
CCP
SIGNAL NAME
V
CCP
V
CCP
Introduction
December 2004 SCPS114
7
Introduction
Table 2−2. CardBus PC Card Signal Names Sorted Alphabetically to GVF Terminals
SIGNAL NAME TERMINAL SIGNAL NAME TERMINAL SIGNAL NAME TERMINAL
AD0 W13 CAD11 C12 CREQ E07
AD1 N11 CAD12 B11 CRST A06
AD2 U12 CAD13 C11 CRSVD B13
AD3 V12 CAD14 G11 CRSVD C10
AD4 W12 CAD15 E11 CRSVD D02
AD5 R11 CAD16 A10 CSERR B03
AD6 U11 CAD17 A07 CSTOP A09
AD7 V11 CAD18 B07 CSTSCHG B02
AD8 N10 CAD19 C07 CTRDY A08
AD9 R10 CAD20 G09 CVS1 A03
AD10 U10 CAD21 B06 CVS2 E08
AD11 V10 CAD22 C06 DEVSEL N08
AD12 N09 CAD23 B05 FRAME V07
AD13 R09 CAD24 E06 GNT T02
AD14 U09 CAD25 A04 GRST T01
AD15 V09 CAD26 B04 IDSEL W05
AD16 R07 CAD27 B01 IRDY U07
AD17 U06 CAD28 C02 MFUNC0 N03
AD18 V06 CAD29 D03 MFUNC1 M05
AD19 W06 CAD30 C01 MFUNC2 P01
AD20 P06 CAD31 D01 MFUNC3 P02
AD21 R06 CAUDIO A02 MFUNC4 P03
AD22 U05 C/BE0 W11 MFUNC5 N05
AD23 V05 C/BE1 W09 MFUNC6 R01
AD24 V04 C/BE2 W07 PAR P09
AD25 U04 C/BE3 W04 PCLK P05
AD26 V03 CBLOCK E10 PERR V08
AD27 W02 CC/BE0 G12 PRST R03
AD28 U03 CC/BE1 B10 REQ U01
AD29 V02 CC/BE2 F09 RI_OUT/PME T03
AD30 V01 CC/BE3 C05 SERR U08
AD31 U02 CCD1 C15 SPKROUT L07
CAD0 E14 CCD2 E05 STOP W08
CAD1 B14 CCLK E09 SUSPEND R02
CAD2 A14 CCLKRUN C03 TRDY R08
CAD3 E13 CDEVSEL C09 VCCD0 L06
CAD4 C14 CFRAME C08 VCCD1 L05
CAD5 A13 CGNT B09 VPPD0 N02
CAD6 F12 CINT C04 VPPD1 N01
CAD7 C13 CIRDY B08 VR_EN H02
CAD8 E12 CLK_48_RSVD — VR_PORT M19
CAD9 A12 CPAR G10
CAD10 B12 CPERR F10
8
December 2004SCPS114
Introduction
Table 2−3. 16-Bit PC Card Signal Names Sorted Alphabetically to GVF Terminals
SIGNAL NAME TERMINAL SIGNAL NAME TERMINAL SIGNAL NAME TERMINAL
AD0 W13 A11 B11 FRAME V07
AD1 N11 A12 F09 GNT T02
AD2 U12 A13 G10 GRST T01
AD3 V12 A14 F10 IDSEL W05
AD4 W12 A15 B08 INPACK E07
AD5 R11 A16 E09 IORD C11
AD6 U11 A17 A10 IOWR E11
AD7 V11 A18 C10 IRDY U07
AD8 N10 A19 E10 MFUNC0 N03
AD9 R10 A20 A09 MFUNC1 M05
AD10 U10 A21 C09 MFUNC2 P01
AD11 V10 A22 A08 MFUNC3 P02
AD12 N09 A23 C08 MFUNC4 P03
AD13 R09 A24 A07 MFUNC5 N05
AD14 U09 A25 C07 MFUNC6 R01
AD15 V09 BVD1(STSCHG/RI) B02 OE C12
AD16 R07 BVD2(SPKR) A02 PAR P09
AD17 U06 C/BE0 W11 PCLK P05
AD18 V06 C/BE1 W09 PERR V08
AD19 W06 C/BE2 W07 PRST R03
AD20 P06 C/BE3 W04 READY(IREQ) C04
AD21 R06 CD1 C15 REG C05
AD22 U05 CD2 E05 REQ U01
AD23 V05 CE1 G12 RESET A06
AD24 V04 CE2 B12 RI_OUT/PME T03
AD25 U04 CLK_48_RSVD — SERR U08
AD26 V03 DEVSEL N08 SPKROUT L07
AD27 W02 D0 B01 STOP W08
AD28 U03 D1 D03 SUSPEND R02
AD29 V02 D2 D02 TRDY R08
AD30 V01 D3 E14 VCCD0 L06
AD31 U02 D4 B14 VCCD1 L05
A0 B04 D5 E13 VPPD0 N02
A1 A04 D6 A13 VPPD1 N01
A2 E06 D7 C13 VR_EN H02
A3 B05 D8 C02 VR_PORT M19
A4 C06 D9 C01 VS1 A03
A5 B06 D10 D01 VS2 E08
A6 G09 D11 A14 WAIT B03
A7 B07 D12 C14 WE B09
A8 B10 D13 F12 WP(IOIS16) C03
A9 G11 D14 B13
A10 A12 D15 E12
December 2004 SCPS114
9
Introduction
I/O
DESCRIPTION
I/O
DESCRIPTION
I/O
DESCRIPTION
2.8 Terminal Descriptions
The terminals are grouped in tables by functionality, such as PCI system function, power-supply function, etc.
The terminal numbers are also listed for convenient reference.
Table 2−4. Power Supply T erminals
TERMINAL
NAME NUMBER
G07, G08, G13,
H13, J09, J10,
GND
V
CC
V
CCCB
V
CCP
VR_EN H02 I Internal voltage regulator enable. Active-low
VR_PORT M19
J11, K09, K10,
K11, L08, L09,
L10, L11, L12,
M08
H08, H09, H10,
H11, H12, J08,
J12, K08, K12,
M07, M09, M10,
M12, N07
A05, A11 Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V
W03, W10 Clamp voltage for PCI and miscellaneous I/O, 5 V or 3.3 V
Device ground terminals
Power supply terminals for I/O and internal voltage regulator
Internal voltage regulator input/output. When VR_EN is low, the regulator is enabled and this
terminal is an output. An external bypass capacitor is required on this terminal. When VR_EN
high, the regulator is disabled and this terminal is an input for an external 2.5 V core power source.
is
TERMINAL
NAME NUMBER
VCCD0
VCCD1
VPPD0
VPPD1
TERMINAL
NAME NUMBER
GRST T01 I
PCLK P05 I
PRST R03 I
L06
L05
N02
N01
Table 2−5. PC Card Power Switch T erminals
O Logic controls to the TPS2211A PC Card power interface switch to control AVCC
O Logic controls to the TPS2211A PC Card power interface switch to control AVPP
Table 2−6. PCI System T erminals
Global reset. When the global reset is asserted, the GRST signal causes the controller to place all output
buffers in a high-impedance state and reset all internal registers. When GRST
completely in its default state. For systems that require wake-up from D3, GRST
during initial boot. PRST
transition from D3 to D0.
When the SUSPEND
preserved. All outputs are placed in a high-impedance state.
PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the
rising edge of PCLK.
PCI bus reset. When the PCI bus reset is asserted, PRST causes the controller to place all output buffers in
a high-impedance state and reset internal registers. When PRST
signal only if it is enabled. After PRST is deasserted, the controller is in a default state.
PME
When the SUSPEND
preserved. All outputs are placed in a high-impedance state.
must be asserted following initial boot so that PME context is retained during the
mode is enabled, the device is protected from GRST, and the internal registers are
is asserted, the device can generate the
mode is enabled, the device is protected from PRST, and the internal registers are
is asserted, the device is
normally is asserted only
10
December 2004SCPS114
TERMINAL
I/O
DESCRIPTION
NAME NUMBER
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AD22
AD21
AD20
AD19
AD18
AD17
AD16
AD15
AD14
AD13
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
C/BE3
C/BE2
C/BE1
C/BE0
PAR P09 I/O
U02
V01
V02
U03
W02
V03
U04
V04
V05
U05
R06
P06
W06
V06
U06
R07
V09
U09
R09
N09
V10
U10
R10
N10
V11
U11
R11
W12
V12
U12
N11
W13
W04
W07
W09
W11
Table 2−7. PCI Address and Data Terminals
PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary
interface. During the address phase of a primary-bus PCI cycle, AD31–AD0 contain a 32-bit address or
I/O
other destination information. During the data phase, AD31–AD0 contain data.
PCI-bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the
address phase of a primary-bus PCI cycle, C/BE3
this 4-bit bus is used as a byte enable. The byte enable determines which byte paths of the full 32-bit data
I/O
bus carry meaningful data. C/BE0 applies to byte 0 (AD7–AD0), C/BE1 applies to byte 1 (AD15–AD8),
C/BE2
applies to byte 2 (AD23–AD16), and C/BE3 applies to byte 3 (AD31–AD24).
PCI-bus parity. In all PCI-bus read and write cycles, the controller calculates even parity across the
AD31–AD0 and C/BE3
indicator with a one-PCLK delay. As a target during PCI cycles, the controller compares its calculated parity
to the parity indicator of the initiator. A compare error results in the assertion of a parity error (PERR).
–C/BE0 buses. As an initiator during PCI cycles, the controller outputs this parity
–C/BE0 define the bus command. During the data phase,
Introduction
December 2004 SCPS114
11
Introduction
I/O
DESCRIPTION
Table 2−8. PCI Interface Control Terminals
TERMINAL
NAME NUMBER
PCI device select. The controller asserts DEVSEL to claim a PCI cycle as the target device. As a PCI initiator
DEVSEL N08 I/O
FRAME V07 I/O
GNT T02 I
IDSEL W05 I
IRDY U07 I/O
PERR V08 I/O
REQ U01 O PCI bus request. REQ is asserted by the controller to request access to the PCI bus as an initiator.
SERR U08 O
STOP W08 I/O
TRDY R08 I/O
on the bus, the controller monitors DEVSEL
occurs, then the controller terminates the cycle with an initiator abort.
PCI cycle frame. FRAME is driven by the initiator of a bus cycle. FRAME is asserted to indicate that a bus
transaction is beginning, and data transfers continue while this signal is asserted. When FRAME
deasserted, the PCI bus transaction is in the final data phase.
PCI bus grant. GNT is driven by the PCI bus arbiter to grant the controller access to the PCI bus after the
current data transaction has completed. GNT
PCI bus parking algorithm.
Initialization device select. IDSEL selects the controller during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines on the PCI bus.
PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of
the transaction. A data phase is completed on a rising edge of PCLK where both IRDY
asserted. Until IRDY
PCI parity error indicator. PERR is driven by a PCI device to indicate that calculated parity does not match
PAR when PERR
PCI system error. SERR is an output that is pulsed from the controller when enabled through bit 8 of the
command register (PCI offset 04h, see Section 4.4) indicating a system error has occurred. The controller
need not be the target of the PCI cycle to assert this signal. When SERR is enabled in the command register ,
this signal also pulses, indicating that an address parity error has occurred on a CardBus interface.
PCI cycle stop signal. STOP is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. STOP
support burst data transfers.
PCI target ready. TRDY indicates the ability of the primary bus target to complete the current data phase of
the transaction. A data phase is completed on a rising edge of PCLK when both IRDY
Until both IRDY
and TRDY are both sampled asserted, wait states are inserted.
is enabled through bit 6 of the command register (PCI offset 04h, see Section 4.4).
is used for target disconnects and is commonly asserted by target devices that do not
and TRDY are asserted, wait states are inserted.
until a target responds. If no target responds before timeout
may or may not follow a PCI bus request, depending on the
and TRDY are
and TRDY are asserted.
is
12
December 2004SCPS114
Table 2−9. Multifunction and Miscellaneous Terminals
I/O
DESCRIPTION
TERMINAL
NAME NUMBER
MFUNC0 N03 I/O
MFUNC1 M05 I/O
MFUNC2 P01 I/O
MFUNC3/
IRQSER
MFUNC4 P03 I/O
MFUNC5 N05 I/O
MFUNC6/
CLKRUN
RI_OUT / PME T03 O
SPKROUT L07 O
SUSPEND R02 I
P02 I/O
R01 I/O
Introduction
Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA, GPI0, GPO0,
socket activity LED output, ZV switching output, CardBus audio PWM, GPE
Section 4.30, Multifunction Routing Register, for configuration details.
Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity LED output,
D3_STAT
Multifunction Routing Register, for configuration details.
Serial data (SDA). When VCCD0 and VCCD1 are detected high after a global reset, the MFUNC1
terminal provides the SDA signaling for the serial bus interface. The two-terminal serial interface loads
the subsystem identification and other register defaults from an EEPROM after a global reset. See
Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.
Multifunction terminal 2. MFUNC2 can be configured as GPI2, GPO2, socket activity LED output, ZV
switching output, CardBus audio PWM, GPE
Multifunction Routing Register, for configuration details.
Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal
IRQSER. This terminal is IRQSER by default. See Section 4.30, Multifunction Routing Register, for
configuration details.
Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK, GPI3, GPO3, socket activity LED
output, ZV switching output, CardBus audio PWM, GPE
Section 4.30, Multifunction Routing Register, for configuration details.
Serial clock (SCL). When VCCD0
terminal provides the SCL signaling for the serial bus interface. The two-terminal serial interface loads
the subsystem identification and other register defaults from an EEPROM after a global reset. See
Section 3.6.1, Serial Bus Interface Implementation, for details on other serial bus applications.
Multifunction terminal 5. MFUNC5 can be configured as GPI4, GPO4, socket activity LED output, ZV
switching output, CardBus audio PWM, D3_STAT
Multifunction Routing Register, for configuration details.
Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN or a parallel IRQ. See
Section 4.30, Multifunction Routing Register, for configuration details.
Ring indicate out and power management event output. Terminal provides an output for ring- indicate
or PME
Speaker output. SPKROUT is the output to the host system that can carry SPKR or CAUDIO through
the controller from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card
SPKR//CAUDIO inputs.
Suspend. SUSPEND protects the internal registers from clearing when the GRST or PRST signal is
asserted. See Section 3.8.5, Suspend Mode, for details.
, ZV switching output, CardBus audio PWM, GPE, or a parallel IRQ. See Section 4.30,
, RI_OUT, D3_ST AT, or a parallel IRQ. See Section 4.30,
, D3_STAT, RI_OUT, or a parallel IRQ. See
and VCCD1 are detected high after a global reset, the MFUNC4
, GPE, or a parallel IRQ. See Section 4.30,
signals.
, or a parallel IRQ. See
December 2004 SCPS114
13
Introduction
I/O
DESCRIPTION
TERMINAL
NAME NUMBER
A25
A24
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
C07
A07
C08
A08
C09
A09
E10
C10
A10
E09
B08
F10
G10
F09
B11
A12
G11
B10
B07
G09
B06
C06
B05
E06
A04
B04
E12
B13
F12
C14
A14
D01
C01
C02
C13
A13
E13
B14
E14
D02
D03
B01
Table 2−10. 16-Bit PC Card Address and Data Terminals
O PC Card address. 16-bit PC Card address lines. A25 is the most significant bit.
I/O PC Card data. 16-bit PC Card data lines. D15 is the most significant bit.
14
December 2004SCPS114
TERMINAL
I/O
DESCRIPTION
NAME NUMBER
BVD1
(STSCHG
BVD2(SPKR) A02
CD1
CD2
CE1
CE2
INPACK E07
IORD C11
IOWR E11
OE C12
READY
(IREQ
REG C05
RESET A06
VS1
VS2
WAIT B03
/RI)
)
B02
C15
E05
G12
B12
C04
A03
E08
Table 2−11. 16-Bit PC Card Interface Control Terminals
Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1
is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1
and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak
and must be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the
memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register,
I
for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface
Status Register, for the status bits for this signal.
Status change. STSCHG
battery voltage dead condition of a 16-bit I/O PC Card.
Ring indicate. RI
Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2
is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1
and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak
and must be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the
memory PC Card is lost. See Section 5.6, ExCA Card Status-Change Interrupt Configuration Register,
I
for enable bits. See Section 5.5, ExCA Card Status-Change Register, and Section 5.2, ExCA Interface
Status Register, for the status bits for this signal.
Speaker. SPKR
configured for the 16-bit I/O interface.
Card detect 1 and card detect 2. CD1 and CD2 are internally connected to ground on the PC Card.
I
When a PC Card is inserted into a socket, CD1
Section 5.2, ExCA Interface Status Register.
Card enable 1 and card enable 2. CE1 and CE2 enable even- and odd-numbered address bytes. CE1
O
enables even-numbered address bytes, and CE2 enables odd-numbered address bytes.
Input acknowledge. INPACK is asserted by the PC Card when it can respond to an I/O read cycle at
I
the current address.
I/O read. IORD is asserted by the controller to enable 16-bit I/O PC Card data output during host I/O
O
read cycles.
I/O write. IOWR is driven low by the controller to strobe write data into 16-bit I/O PC Cards during host
O
I/O write cycles.
Output enable. OE is driven low by the controller to enable 16-bit memory PC Card data output during
O
host memory read cycles.
Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are
configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to
indicate that the memory card circuits are busy processing a previous write command. READY is
driven high when the 16-bit memory PC Card is ready to accept a new data transfer command.
I
Interrupt request. IREQ
16-bit I/O PC Card requires service by the host software. IREQ
is requested.
Attribute memory select. REG remains high for all common memory accesses. When REG is
asserted, access is limited to attribute memory (OE
O
O
I/O
I
active). Attribute memory is a separately accessed section of card memory and is generally
IOWR
used to record card capacity and other configuration and attribute information.
PC Card reset. RESET forces a hard reset to a 16-bit PC Card.
Voltage sense 1 and voltage sense 2. VS1 and VS2, when used in conjunction with each other,
determine the operating voltage of the PC Card.
Bus cycle wait. WAIT is driven by a 16-bit PC Card to extend the completion of the memory or I/O in
progress.
is used by 16-bit modem cards to indicate a ring detection.
is an optional binary audio signal available only when the card and socket have been
is used to alert the system to a change in the READY, write protect, or
and CD2 are pulled low. For signal status, see
is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the
is high (deasserted) when no interrupt
or WE active) and to the I/O space (IORD or
Introduction
December 2004 SCPS114
15
Introduction
I/O
DESCRIPTION
I/O
DESCRIPTION
Table 2−11. 16-Bit PC Card Interface Control Terminals (Continued)
TERMINAL
NAME NUMBER
WE B09 O
WP
(IOIS16
)
TERMINAL
NAME NUMBER
CCLK E09 O
CCLKRUN C03 I/O
CRST A06 O
C03 I
Write enable. WE is used to strobe memory write data into 16-bit memory PC Cards. WE is also used for
memory PC Cards that employ programmable memory technologies.
Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on
16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16
I/O is 16 bits. IOIS16
address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port
that is addressed is capable of 16-bit accesses.
applies to 16-bit I/O PC Cards. IOIS16 is asserted by the 16-bit PC Card when the
) function.
Table 2−12. CardBus PC Card Interface System Terminals
CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All
signals except CRST
sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this
signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed
down for power savings.
CardBus clock run. CCLKRUN is used by a CardBus PC Card to request an increase in the CCLK
frequency, and by the controller to indicate that the CCLK frequency is going to be decreased.
CardBus reset. CRST brings CardBus PC Card-specific registers, sequencers, and signals to a known
state. When CRST
the controller drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but
deassertion must be synchronous to CCLK.
, CCLKRUN, CINT, CSTSCHG, CAUDIO, CCD2, CCD1, CVS2, and CVS1 are
is asserted, all CardBus PC Card signals are placed in a high-impedance state, and
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December 2004SCPS114
TERMINAL
I/O
DESCRIPTION
NAME NUMBER
CAD31
CAD30
CAD29
CAD28
CAD27
CAD26
CAD25
CAD24
CAD23
CAD22
CAD21
CAD20
CAD19
CAD18
CAD17
CAD16
CAD15
CAD14
CAD13
CAD12
CAD11
CAD10
CAD9
CAD8
CAD7
CAD6
CAD5
CAD4
CAD3
CAD2
CAD1
CAD0
CC/BE3
CC/BE2
CC/BE1
CC/BE0
CPAR G10 I/O
D01
C01
D03
C02
B01
B04
A04
E06
B05
C06
B06
G09
C07
B07
A07
A10
E11
G11
C11
B11
C12
B12
A12
E12
C13
F12
A13
C14
E13
A14
B14
E14
C05
F09
B10
G12
I/O
I/O
Introduction
Table 2−13. CardBus PC Card Address and Data Terminals
CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the
CardBus interface. During the address phase of a CardBus cycle, CAD31–CAD0 contain a 32-bit address.
During the data phase of a CardBus cycle, CAD31–CAD0 contain data. CAD31 is the most significant bit.
CardBus bus commands and byte enables. CC/BE3–CC/BE0 are multiplexed on the same CardBus
terminals. During the address phase of a CardBus cycle, CC/BE3
During the data phase, this 4-bit bus is used as a byte enable. The byte enable determines which byte
paths of the full 32-bit data bus carry meaningful data. CC/BE0 applies to byte 0 (CAD7–CAD0), CC/BE1
applies to byte 1 (CAD15–CAD8), CC/BE2 applies to byte 2 (CAD23–CAD16), and CC/BE3 applies to byte
(CAD31–CAD24).
CardBus parity. In all CardBus read and write cycles, the controller calculates even parity across the CAD
and CC/BE
delay. As a target during CardBus cycles, the controller compares its calculated parity to the parity indicator
of the initiator; a compare error results in a parity error assertion.
buses. As an initiator during CardBus cycles, the controller outputs CPAR with a one-CCLK
–CC/BE0 define the bus command.
December 2004 SCPS114
17
Introduction
I/O
DESCRIPTION
Table 2−14. CardBus PC Card Interface Control Terminals
TERMINAL
NAME NUMBER
CAUDIO A02 I
CBLOCK E10 I/O CardBus lock. CBLOCK is used to gain exclusive access to a target.
CCD1
CCD2
CDEVSEL C09 I/O
CFRAME C08 I/O
CGNT B09 O
CINT C04 I
CIRDY B08 I/O
CPERR F10 I/O
CREQ E07 I
CSERR B03 I
CSTOP A09 I/O
CSTSCHG B02 I
CTRDY A08 I/O
CVS1
CVS2
C15
E05
A03
E08
CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The controller
supports the binary audio mode and outputs a binary signal from the card to SPKROUT.
CardBus detect 1 and CardBus detect 2. CCD1 and CCD2 are used in conjunction with CVS1 and CVS2
I
to identify card insertion and interrogate cards to determine the operating voltage and card type.
CardBus device select. The controller asserts CDEVSEL to claim a CardBus cycle as the target device.
As a CardBus initiator on the bus, the controller monitors CDEVSEL
responds before timeout occurs, then the controller terminates the cycle with an initiator abort.
CardBus cycle frame. CFRAME is driven by the initiator of a CardBus bus cycle. CFRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When CFRAME
CardBus bus grant. CGNT is driven by the controller to grant a CardBus PC Card access to the CardBus
bus after the current data transaction has been completed.
CardBus interrupt. CINT is asserted low by a CardBus PC Card to request interrupt servicing from the
host.
CardBus initiator ready. CIRDY indicates the ability of the CardBus initiator to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY
CTRDY
CardBus parity error. CPERR reports parity errors during CardBus transactions, except during special
cycles. It is driven low by a target two clocks following the data cycle during which a parity error is
detected.
CardBus request. CREQ indicates to the arbiter that the CardBus PC Card desires use of the CardBus
bus as an initiator.
CardBus system error. CSERR reports address parity errors and other system errors that could lead to
catastrophic results. CSERR
pullup; deassertion may take several CCLK periods. The controller can report CSERR
assertion of SERR
CardBus stop. CSTOP is driven by a CardBus target to request the initiator to stop the current CardBus
transaction. CSTOP
not support burst data transfers.
CardBus status change. CSTSCHG alerts the system to a change in the card status, and is used as a
wake-up mechanism.
CardBus target ready. CTRDY indicates the ability of the CardBus target to complete the current data
phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY
CTRDY
CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with
CCD1
I/O
and CCD2 to identify card insertion and interrogate cards to determine the operating voltage and
card type.
is deasserted, the CardBus bus transaction is in the final data phase.
are asserted. Until CIRDY and CTRDY are both sampled asserted, wait states are inserted.
is driven by the card synchronous to CCLK, but deasserted by a weak
on the PCI interface.
is used for target disconnects, and is commonly asserted by target devices that do
are asserted; until this time, wait states are inserted.
until a target responds. If no target
and
to the system by
and
18
December 2004SCPS114
3 Principles of Operation
The following sections give an overview of the PCI1510R controller. Figure 3−1 shows a simplified block
diagram of the controller. The PCI interface includes all address/data and control signals for PCI protocol. The
interrupt interface includes terminals for parallel PCI, parallel ISA, and serialized PCI and ISA signaling.
Miscellaneous system interface terminals include multifunction terminals: SUSPEND
management control signal), and SPKROUT.
PCI Bus
Activity LED
Principles of Operation
, RI_OUT/PME (power
INTA
Interrupt
Controller
TPS2211A
Power
Switch
PC Card
Socket
External ZV Port
NOTE: The PC Card interface is 68 terminals for CardBus and 16-bit PC Cards. In ZV mode, 23 terminals are used for routing the ZV signals
to the VGA controller and audio subsystem.
4
PCI1510R
68
23
IRQSER
3
Multiplexer
PCI950
IRQSER
Deserializer
Zoomed Video
19
Zoomed Video
4
IRQ2−15
VGA
Controller
Audio
Subsystem
Figure 3−1. PCI1510R Simplified Block Diagram
3.1 Power Supply Sequencing
The controller contains 3.3-V I/O buffers with 5-V tolerance requiring an I/O power supply and an LDO-VR
power supply for core logic. The core power supply, which is always 2.5 V, can be supplied through the
VR_PORT terminal (when VR_EN
supply via the V
terminals. The clamping voltages (V
CC
on the interface. The following power-up and power-down sequences are recommended.
is high) or from the integrated LDO-VR. The LDO-VR needs a 3.3-V power
CCCB
and V
) can be either 3.3 V or 5 V , depending
CCP
The power-up sequence is:
1. Assert GRST
to the device to disable the outputs during power up. Output drivers must be powered up
in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V clamping
rails (V
2. Apply 3.3-V power to V
CCCB
and V
CCP
).
CC
.
3. Apply the clamp voltage.
December 2004 SCPS114
19
Principles of Operation
The power-down sequence is:
1. Assert GRST
to the device to disable the outputs during power down. Output drivers must be powered
down in the high-impedance state to prevent high current levels through the clamp diodes to the 5-V
clamping rails (V
CCCB
2. Remove the clamp voltage.
3. Remove the 3.3-V power from V
NOTE: The clamp voltage can be ramped up or ramped down along with the 3.3-V power. The
voltage difference between V
3.2 I/O Characteristics
Figure 3−2 shows a 3-state bidirectional buffer. Section 7.2, Recommended Operating Conditions, provides
the electrical characteristics of the inputs and outputs.
NOTE: The controller meets the ac specifications of the PC Card Standard and PCI Local Bus
Specification.
and V
Tied for Open Drain
).
CCP
.
CC
and the clamp voltage must remain within 3.6 V.
CC
V
CCP
OE
Pad
Figure 3−2. 3-State Bidirectional Buffer
NOTE: Unused terminals (input or I/O) must be held high or low to prevent them from floating.
3.3 Clamping Voltages
The clamping voltages are set to match whatever external environment the controller is interfaced with, 3.3 V
or 5 V. The I/O sites can be pulled through a clamping diode to a voltage rail that protects the core from external
signals. The core power supply is always 3.3 V and is independent of the clamping voltages. For example,
PCI signaling can be either 3.3 V or 5 V, and the controller must reliably accommodate both voltage levels.
This is accomplished by using a 3.3-V I/O buffer that is 5-V tolerant, with the applicable clamping voltage
applied. If a system designer desires a 5-V PCI bus, then V
can be connected to a 5-V power supply.
CCP
The controller requires three separate clamping voltages because it supports a wide range of features. The
three voltages are listed and defined in Section 7.2, Recommended Operating Conditions. GRST
PME
, and CSTSCHG are not clamped to any of them.
3.4 Peripheral Component Interconnect (PCI) Interface
The controller is fully compliant with the PCI Local Bus Specification. The controller provides all required
signals for PCI master or slave operation, and may operate in either a 5-V or 3.3-V signaling environment by
connecting the V
controller provides the optional interrupt signal INTA
terminal to the desired voltage level. In addition to the mandatory PCI signals, the
CCP
.
3.4.1 PCI GRST Signal
During the power-up sequence, GRST and PRST must be asserted. GRST can only be deasserted 100 µs
after PCLK is stable. PRST
can be deasserted at the same time as GRST or any time thereafter.
, SUSPEND,
20
December 2004SCPS114
3.4.2 PCI Bus Lock (LOCK)
The bus-locking protocol defined in the PCI Local Bus Specification is not highly recommended, but is
provided on the controller as an additional compatibility feature. The PCI LOCK
MFUNC4 terminal by setting the appropriate values in bits 19−16 of the multifunction routing register. See
Section 4.30, Multifunction Routing Register,
PCI-to-CardBus bridges in the downstream direction (away from the processor).
PCI LOCK indicates an atomic operation that may require multiple transactions to complete. When LOCK is
asserted, nonexclusive transactions can proceed to an address that is not currently locked. A grant to start
a transaction on the PCI bus does not guarantee control of LOCK
protocol. It is possible for different initiators to use the PCI bus while a single master retains ownership of
LOCK
. Note that the CardBus signal for this protocol is CBLOCK to avoid confusion with the bus clock.
An agent may need to do an exclusive operation because a critical access to memory might be broken into
several transactions, but the master wants exclusive rights to a region of memory . The granularity of the lock
is defined by PCI to be 16 bytes, aligned. The LOCK
a resource lock without interfering with nonexclusive real-time data transfer, such as video.
Principles of Operation
signal can be routed to the
for details. Note that the use of LOCK is only supported by
; control of LOCK is obtained under its own
protocol defined by the PCI Local Bus Specification allows
The PCI bus arbiter may be designed to support only complete bus locks using the LOCK
scenario, the arbiter does not grant the bus to any other agent (other than the LOCK
asserted. A complete bus lock may have a significant impact on the performance of the video. The arbiter that
supports complete bus lock must grant the bus to the cache to perform a writeback due to a snoop to a modified
line when a locked operation is in progress.
The controller supports all LOCK
protocol associated with PCI-to-PCI bridges, as also defined for
PCI-to-CardBus bridges. This includes disabling write posting while a locked operation is in progress, which
can solve a potential deadlock when using devices such as PCI-to-PCI bridges. The potential deadlock can
occur if a CardBus target supports delayed transactions and blocks access to the target until it completes a
delayed read. This target characteristic is prohibited by the PCI Local Bus Specification, and the issue is
resolved by the PCI master using LOCK
.
3.4.3 Loading Subsystem Identification
The subsystem vendor ID register (PCI offset 40h, see Section 4.26) and subsystem ID register (PCI offset
42h, see Section 4.27) make up a doubleword of PCI configuration space for function 0. This doubleword
register is used for system and option card (mobile dock) identification purposes and is required by some
operating systems. Implementation of this unique identifier register is a PC 99/PC 2001 requirement.
The controller offers two mechanisms to load a read-only value into the subsystem registers. The first
mechanism relies upon the system BIOS providing the subsystem ID value. The default access mode to the
subsystem registers is read-only, but can be made read/write by clearing bit 5 (SUBSYSRW) in the system
control register (PCI offset 80h, see Section 4.29). Once this bit is cleared, the BIOS can write a subsystem
identification value into the registers at PCI offset 40h. The BIOS must set the SUBSYSRW bit such that the
subsystem vendor ID register and subsystem ID register is limited to read-only access. This approach saves
the added cost of implementing the serial electrically erasable programmable ROM (EEPROM).
protocol. In this
master) while LOCK is
In some conditions, such as in a docking environment, the subsystem vendor ID register and subsystem ID
register must be loaded with a unique identifier via a serial EEPROM. The controller loads the data from the
serial EEPROM after a reset of the primary bus. Note that the SUSPEND
input gates the PCI reset from the
entire controller core, including the serial-bus state machine (see Section 3.8.5, Suspend Mode, for details
on using SUSPEND
).
The controller provides a two-line serial-bus host controller that can interface to a serial EEPROM. See
Section 3.6, Serial-Bus Interface, for details on the two-wire serial-bus controller and applications.
December 2004 SCPS114
21
Principles of Operation
3.5 PC Card Applications
This section describes the PC Card interfaces of the controller.
• Card insertion/removal and recognition
• Zoomed video support
• Speaker and audio applications
• LED socket activity indicators
• CardBus socket registers
3.5.1 PC Card Insertion/Removal and Recognition
The PC Card Standard (release 7.2) addresses the card-detection and recognition process through an
interrogation procedure that the socket must initiate on card insertion into a cold, nonpowered socket. Through
this interrogation, card voltage requirements and interface (16-bit versus CardBus) are determined.
The scheme uses the card-detect and voltage-sense signals. The configuration of these four terminals
identifies the card type and voltage requirements of the PC Card interface. The encoding scheme is defined
in the PC Card Standard (release 7.2) and in Table 3−1.
Table 3−1. PC Card Card-Detect and Voltage-Sense Connections
CD2//CCD2 CD1//CCD1 VS2//CVS2 VS1//CVS1 KEY INTERFACE VOLTAGE
Ground Ground Open Open 5 V 16-bit PC Card 5 V
Ground Ground Open Ground 5 V 16-bit PC Card 5 V and 3.3 V
Ground Ground Ground Ground 5 V 16-bit PC Card 5 V, 3.3 V, and X.X V
Ground Ground Open Ground LV 16-bit PC Card 3.3 V
Ground Connect to CVS1 Open Connect to CCD1 LV CardBus PC Card 3.3 V
Ground Ground Ground Ground LV 16-bit PC Card 3.3 V and X.X V
Connect to CVS2 Ground Connect to CCD2 Ground LV CardBus PC Card 3.3 V and X.X V
Connect to CVS1 Ground Ground Connect to CCD2 LV CardBus PC Card 3.3 V, X.X V, and Y.Y V
Ground Ground Ground Open LV 16-bit PC Card X.X V
Connect to CVS2 Ground Connect to CCD2 Open LV CardBus PC Card X.X V
Ground Connect to CVS2 Connect to CCD1 Open LV CardBus PC Card X.X V and Y.Y V
Connect to CVS1 Ground Open Connect to CCD2 LV CardBus PC Card Y.Y V
Ground Connect to CVS1 Ground Connect to CCD1 Reserved
Ground Connect to CVS2 Connect to CCD1 Ground Reserved
3.5.2 Parallel Power-Switch Interface (TPS2211A)
The controller provides a parallel interface for control of the PC Card power switch. The VCCD and VPPD
terminals are used with the TI TPS2211A single-slot PC Card power-switch interface to provide power-switch
support. Figure 3−3 illustrates a typical application, where the controller represents the PC Card controller.
22
December 2004SCPS114
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