TEXAS INSTRUMENTS ONET4291VA Technical data

www.ti.com

查询ONET4291VA供应商

1 GBPS TO 4.25 GBPS MULTI-RATE VCSEL DRIVER

ONET4291VA

SLLS674 – SEPTEMBER 2005

FEATURES

• Operating Temperature –40 ° C to 85 ° C

• Multi-Rate Operation from 1 Gbps Up • Small Footprint Surface Mount 4 mm × 4 mm,

To 4.25 Gbps 20-Pin QFN Package

• 2-Wire Digital Interface

• Digitally Selectable Modulation Current

• Digitally Selectable Bias Current

• Automatic Power Control (APC) Loop

• Supports Transceiver Management

APPLICATIONS

• Multirate SFP/SFF Modules

• 1.0625 Gbps, 2.125 Gbps, and 4.25 Gbps Fibre

Channel Transmitters

• Gigabit Ethernet Transmitters

System (TMS)

• Includes Laser Safety Features

• Analog Temperature Sensor Output

• Single 3.3-V Supply

DESCRIPTION

The ONET4291VA is a versatile high-speed multi-rate VCSEL driver for fiber optic applications with data rates up to 4.25 Gbps.

The device provides a 2-wire interface which allows digital control of the modulation and bias currents, eliminating the need for of external components.

The ONET4291VA includes an integrated automatic power control loop as well as circuitry to support laser safety and transceiver management systems.

The part is available in a small footprint 4 mm × 4 mm 20-pin QFN package and it requires a single 3.3-V supply. This power efficient multi-rate VCSEL driver is characterized for operation from –40 ° C to 85 ° C ambient

temperature.

BLOCK DIAGRAM

A simplified block diagram of the ONET4291VA is shown in Figure 1 . This compact, low power 1-Gbps to 4.25-Gbps multi-rate VCSEL driver consists of a high-speed current

modulator, a modulation current generator, power-on reset circuitry, a 2-wire interface and control logic block, a bias current generator and automatic power control loop, and an analog reference block.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com

DIN+

DIN−

Limiting

Gain Stage

GND

DOUT+

DOUT−

Power-On Reset

GND VCC

RESET

Modulation

Current

Generator

MODC

IMOD

MODR

ENA

MODC MODR ENA

FLT

VCC

SCK

SDA

DIS

SCK

SDA

DIS

FLT

Bias Current Generator

and Automatic Power

Control Loop (APC)

BIAS

MONB

MONP

BIAS

MONB

MONP

COMP

RZTC

2-Wire Interface and Control Logic Clock

FAULTPDPBIASCOLEENA

High-Speed Current Modulator

100 Ω

60 Ω60 Ω

FAULTPDPBIASCOLEENA

Analog Reference

B0072-01

ONET4291VA

SLLS674 – SEPTEMBER 2005

Figure 1. Simplified Block Diagram of the ONET4291VA

www.ti.com

ONET4291VA

SLLS674 – SEPTEMBER 2005

HIGH-SPEED CURRENT MODULATOR

The data signal is applied to the high-speed current modulator by means of the input signal pins DIN+/DIN–, which provide on-chip differential 100- Ω line-termination. The succeeding limiting gain stage ensures sufficient drive amplitude and edge-speed for driving the current modulator differential pair.

The modulation current is sunk from the common emitter node of the differential pair by means of a modulation current generator, which is digitally controlled by the 2-wire interface and control logic block.

The collector nodes of the differential pair are connected to the output pins DOUT+/DOUT–, which include on-chip 2 × 60- Ω back-termination to VCC. The 60- Ω back-termination helps to sufficiently suppress signal distortion caused by double reflections for VCSEL diodes with impedances ranging from 50 Ω through 75 Ω .

MODULATION CURRENT GENERATOR

The modulation current generator provides the current for the current modulator described above. The circuit is digitally controlled by the 2-wire interface and control logic block.

An 8-bit wide control bus, MODC, is used to set the desired modulation current. Furthermore, two modulation current ranges are selected by means of the MODR signal. The ENA signal enables or disables the modulation current generator. The modulation current can be disabled by setting the DIS input pin to a high level. The modulation current is

also disabled in a fault condition if the fault detection enable register flag FLTEN is set. For more information about the register functionality, see the register mapping description.

2-WIRE SERIAL INTERFACE AND CONTROL LOGIC

The ONET4291VA uses a 2-wire serial interface for digital control. A simplified block diagram of this interface is shown in Figure 2 .

The two circuit inputs, SDA and SCK, are driven, respectively, by the serial data and serial clock from a microprocessor, for example. Both inputs include 100-k Ω pullup resistors to VCC. For driving these inputs, an open drain output is recommended.

A write cycle consists of a START command, three address bits with MSB first, eight data bits with MSB first, and a STOP command. In idle mode, both SDA and SCK lines are at a high level.

A START command is initiated by the falling edge of SDA with SCK at a high level, transitioning to a low level. Bits are clocked into an 11-bit wide shift register during the high level of the system clock SCK. A STOP command is detected on the rising edge of SDA after SCK has changed from a low to a high level. At the time of detection of a STOP command, the eight data bits from the shift register are copied to a selected

8-bit register. Register selection occurs according to the three address bits in the shift register, which are decoded to eight independent select signals using a 3 to 8 decoder block.

In the ONET4291VA, only addresses 0 (000b) through 3 (011b) are used.

www.ti.com

Start/Stop

Detector

Logic

111

110

101

100

011

010

001

000

START

STOP

SDA SCK

8 Bit Register

Control Functions (6 Bit)

Unused (2 Bit)

8 Bit Register

Modulation Current (8 Bit)

11 Bit Shift Register

8 Bits Data 3 Bits Addr

3 to 8 Decoder

B0068-02

8 Bit Register

Bias Current (8 Bit)

8 Bit Register

Unused (8 Bit)

ONET4291VA

SLLS674 – SEPTEMBER 2005

Figure 2. Simplified 2-Wire Interface Block Diagram

The timing definition for the serial data signal SDA and the serial clock signal SCK is shown in Figure 3 . The corresponding timing requirements are listed in Table 1 .

www.ti.com

START STOP1 0 1 0 1 1

SDA

SCK

DTA

STRT

HLD

CLK

DTA

STP

DTA

HLD

STOP

STP

T0077-01

ONET4291VA

SLLS674 – SEPTEMBER 2005

Figure 3. 2-Wire Interface Timing Diagram

Table 1. 2-Wire Interface Timing

PARAMETER DESCRIPTION MIN MAX UNIT

STRT

HLD

CLK

, DTA

CLK

, DTA

CLK

DTA

STP

DTA

HLD

STOP

STP

The register mapping for the register addresses 0 (000b) through 3 (011b) are shown in Table 2 to Table 5 . Register 3 is included for future enhancements. It is not used in the current device.

Table 6 describes the circuit functionality based on the register settings.

START hold time Time required from data falling edge to clock falling edge at START 10 ns Clock and data rise time Clock and data rise time 10 ns

Clock and data fall time Clock and data fall time 10 ns

Clock high time Minimum clock high period 50 ns Data high time Minimum data high period 100 ns Data setup time Minimum time from data rising edge to clock rising edge 10 ns Data wait time Minimum time from data falling edge to data rising edge 50 ns Data hold time Minimum time from clock falling edge to data falling edge 10 ns STOP setup time Minimum time from clock rising edge to data rising edge at STOP 10 ns

Table 2. Register 0 (000b) Mapping

address 0 (000b)

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

ENA PDP PDR OLE FLTEN MODR – –

www.ti.com

ONET4291VA

SLLS674 – SEPTEMBER 2005

Table 3. Register 1 (001b) Mapping

address 1 (001b)

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

MODC7 MODC6 MODC5 MODC4 MODC3 MODC2 MODC1 MODC0

Table 4. Register 2 (010b) Mapping

address 2 (010b)

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

BIASC7 BIASC6 BIASC5 BIASC4 BIASC3 BIASC2 BIASC1 BIASC0

Table 5. Register 3 (011b) Mapping

address 3 (011b)

bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0

– – – – – – – –

Table 6. Register Functionality

Symbol Register Function

ENA Enable Enables chip when set to 1. Can be toggled to reset a fault condition. PDP Photodiode polarity Photodiode polarity bit:

PDR Photodiode current range Photodiode current range bit:

OLE Open loop enable Open loop enable bit:

FLTEN Fault detection enable Fault detection enable bit:

MODR Modulation current range Laser modulation current range:

MODC7 Modulation current bit 7 (MSB) Modulation current setting: MODC6 Modulation current bit 6 MODC5 Modulation current bit 5 MODR = 1 (see above): MODC4 Modulation current bit 4 Modulation current: 100 µ A – 15.4 mA with 68 µ A step size MODC3 Modulation current bit 3 MODC2 Modulation current bit 2 MODR = 0 (see above): MODC1 Modulation current bit 1 Modulation current: 100 µ A – 12 mA with 51 µ A step size MODC0 Modulation current bit 0 (LSB) BIASC7 Bias current bit 7 (MSB) closed loop (APC): BIASC6 Bias current bit 6 Coupling ratio CR between VCSEL bias current and photodiode current is: BIASC5 Bias current bit 5 CR = I BIASC4 Bias current bit 4 PDR = 0 (see above), BIASC = 0 .. 255, I BIASC3 Bias current bit 3 I BIASC2 Bias current bit 2 PDR = 1 (see above), BIASC = 0 .. 255, I BIASC1 Bias current bit 1 I BIASC0 Bias current bit 0 (LSB) open loop: I

1 = common anode 0 = common cathode

1 = 0 µ A – 500 µ A with 2- µ A resolution 0 = 0 µ A – 250 µ A with 1- µ A resolution

1 = open loop bias current control 0 = closed loop bias current control

1 = fault detection on 0 = fault detection off

1 = 0 mA – 15 mA 0 = 0 mA – 12 mA

BIAS-VCSEL

/ I

= 100 µ A + (1 µ A × CR × BIASC)

= 100 µ A + (2 µ A × CR × BIASC)

BIAS-VCSEL

= 100 µ A + (47 µ A × BIASC)

BIAS-VCSEL

≤ 12 mA:

www.ti.com

ONET4291VA

SLLS674 – SEPTEMBER 2005

BIAS CURRENT GENERATION AND APC LOOP

The bias current generation and APC loop are controlled by means of the 2-wire interface. In open loop operation, selected by setting OLE = 1 (bit 4 of register 0), the bias current is set directly by the 8-bit

wide control word BIASC[0..7] (register 2). In automatic power control mode, selected by setting OLE = 0, the bias current depends on the register settings

BIASC[0..7] and the coupling ratio (CR) between the VCSEL bias current and the photodiode current. CR = I

BIAS-VCSEL

Two photodiode current ranges can be selected by means of the PDR register (bit 5 of register 0). The photodiode range should be chosen to keep the laser bias control DAC close to the center of its range. This keeps the laser bias current setpoint resolution high and the loop settling time constant within specification.

For details regarding the bias current setting in open loop as well as in closed loop mode, see Table 6 . In closed loop mode, the photodiode polarity bit, PDP, must be set for common anode or common cathode

configuration to ensure proper operation. In open loop mode if a photodiode is still present, the photodiode polarity bit must be set to the opposite setting.

ANALOG REFERENCE

The ONET4291VA is supplied by a single 3.3-V ±10% supply voltage connected to the VCC pins. This voltage is referenced to ground (GND).

On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from which all other internally required voltages and bias currents are derived.

An external zero temperature coefficient resistor must be connected from the RZTC pin of the device to ground (GND). This resistor is used to generate a precise zero TC current which is used as a reference current for the on-chip DACs.

In order to minimize the module component count, the ONET4291VA VCSEL driver provides an on-chip temperature sensor. The output voltage of the temperature sensor is available at the TS pin.

The voltage is V Note that the voltage at TS is not buffered. As a result, TS can only drive capacitive loads.

/ IPD.

= 9.4 mV × TEMP + 1337 mV with TEMP given in ° C.

POWER-ON RESET AND REGISTER LOADING SEQUENCE

The ONET4291VA has power on reset circuitry which ensures that all registers are reset to zero during startup. After the power-on to initialize time (T

), the internal registers are ready to be loaded. It is important that the

INIT1

registers are loaded in the following order:

1. Bias current register (register 2, 010b),

2. Modulation current register (register 1, 001b),

3. Control register (register 0, 000b).

The part will be ready to transmit data after the initialize to transmit time T

, assuming that the control register

INIT2

enable bit ENA is 1 and the disable pin DIS is low. The ONET4291VA can be disabled using either the ENA control register bit or the disable pin DIS. In both cases

the internal registers are not reset. After the disable pin DIS is de-asserted and/or the enable bit ENA is re-asserted the part returns to its prior output settings.

LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE

The ONET4291VA provides built in laser safety features. The following fault conditions are detected:

1. Voltage at MONB exceeds 1.2 V,

2. Photodiode current exceeds 150% of its target value,

3. Bias control DAC drops in value by more than 33% in one step.

If one or more fault conditions occur and the fault enable bit FLTEN is set to 1, the ONET4192VA responds by:

1. Setting the VCSEL bias current to zero.

+ 14 hidden pages