TEXAS INSTRUMENTS ONET4291PA Technical data

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1-Gbps to 4.25-Gbps Rate-Selectable Limiting Amplifier

ONET4291PA

SLLS671 – SEPTEMBER 2005

FEATURES

• CML Data Outputs With On-Chip, 50- Ω

Back-Termination to V

CC• Multirate Operation from 1 Gbps up to

4.25 Gbps • Single 3.3-V Supply

• Loss-of-Signal Detection (LOS) • Surface-Mount, Small-Footprint, 4-mm ×

• Two-Wire Digital Interface

• Digitally Selectable LOS Threshold

• Digitally Selectable Bandwidth

• Digitally Selectable Output Voltage

• Low Power Consumption

• Input Offset Cancellation

4-mm, 16-Terminal QFN Package

APPLICATIONS

• Multirate SONET/SDH Transmission Systems

• 4.25-Gbps, 2.125-Gbps, and 1.0625-Gbps

Fibre-Channel Receivers

• Gigabit Ethernet Receivers

DESCRIPTION

The ONET4291PA is a versatile, high-speed, rate-selectable limiting amplifier for multiple fiber-optic applications
with data rates up to 4.25 Gbps.

The device provides a two-wire interface, which allows digital bandwidth selection, digital output amplitude
selection, and digital loss of signal threshold adjust.

This device provides a gain of about 43 dB, which ensures a fully differential output swing for input signals as low
as 5 mV

The ONET4291PA provides loss-of-signal detection with either digital or analog threshold adjust.
The part is available in a small-footprint, 4-mm × 4-mm, 16-terminal QFN package. It requires a single 3.3-V

supply.
This power-efficient, rate-selectable limiting amplifier is characterized for operation from –40 ° C to 85 ° C ambient

temperature.

.

p-p

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2005, Texas Instruments Incorporated

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DIN+
DIN−

Band-Gap Voltage

Reference and

Bias Current Generation

Bandwidth

Switch

COC+
COC−

50 Ω

Gain Stage

DC Feedback Stage

CML Output Buffer

Peak

Detector

Loss-of-Signal Detection

Two-Wire

Interface

and

Control

Logic

Programmable

Resistor

V

CC

GND

SDA

SCK

DOUT+
DOUT−

LOS
SD

RTHI

6

50 Ω

+

−

+

−

4

2

TH

+

−

Peak

Detector

Gain Stage

+

−

2

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ONET4291PA

SLLS671 – SEPTEMBER 2005

BLOCK DIAGRAM

A simplified block diagram of the ONET4291PA is shown in Figure 1 .
This compact, 3.3-V, low-power, 1-Gbps to 4.25-Gbps rate-selectable limiting amplifier consists of a high-speed

data path with offset cancellation block (dc feedback), a loss-of-signal detection block using two peak detectors,
a programmable resistor, a two-wire interface and control-logic block, and a band-gap voltage reference and
bias-current generation block.

Figure 1. Simplified Block Diagram of the ONET4291PA

HIGH-SPEED DATA PATH

The high-speed data signal is applied to the data path by means of the input signal terminals DIN+ and DIN–.
The data path consists of a digitally controllable bandwidth switch followed by two 50- Ω on-chip line termination
resistors; two gain stages, which provide a typical gain of about 37 dB; and a CML output stage, which provides
another 6-dB gain. The amplified data-output signal is available at the output terminals DOUT+ and DOUT–,
which feature on-chip 2 × 50- Ω back-termination to V

A dc feedback stage compensates for internal offset voltages and thus ensures proper operation even for small
input data signals. This stage is driven by the output signal of the second gain stage. The signal is low-pass
filtered, amplified, and fed back to the input of the first gain stage via the on-chip 50- Ω termination resistors. The
required low-frequency cutoff is determined by an external 0.1- µ F capacitor, which must be differentially
connected to the COC+ and COC– terminals.

LOSS-OF-SIGNAL DETECTION AND PROGRAMMABLE RESISTOR

The peak values of the output signals of the first and second gain stages are monitored by two peak detectors.
The peak values are compared to a predefined loss-of-signal threshold voltage inside the loss-of-signal detection
block. As a result of the comparison, the loss-of-signal detection block generates the SD signal, which indicates a
sufficient input-signal amplitude, or the LOS signal, which indicates that the input signal amplitude is below the
defined threshold level.

2

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CC

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R6
40 kΩ

RTHI

R7

8 kΩ

LOS Threshold Register

R5
20 kΩ

R4
10 kΩ

R3
5 kΩ

R2

2.5 kΩ

R1

1.25 kΩ

From 2-Wire Interface and Control Logic Block

S0098-01

ONET4291PA

SLLS671 – SEPTEMBER 2005

The threshold voltage can be set within a certain range by means of an external resistor connected between the
TH terminal and ground (GND). Alternatively, shorting the TH and RTHI terminals causes an internal, digitally
selectable resistor to be used for threshold adjustment. The resistor value is selectable using the two-wire
interface.

The principle of the digitally selectable resistor is shown in Figure 2 . The complete resistor between the RTHI
terminal and GND consists of seven series-connected resistors.

Six of the resistors have binary-weighted resistance values, and each can be shunted individually by means of a
parallel-connected MOS transistor.

The seventh resistor defines the minimum remaining resistance in case all six MOS devices are conductive.
With the resistor values shown in Figure 2 , the minimum selectable resistance is 8 k Ω , the maximum resistance

is 86.75 k Ω , and the resolution is 1.25 k Ω /step.

Figure 2. Digitally Controllable On-Chip Resistor

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Start/Stop

Detector

Logic

111

110

101

100

011

010

001

000

START

STOP

SDA
SCK

8-Bit Register

Bandwidth (4 Bits)

Unused (4 Bits)

8

8

8-Bit Register

LOS Threshold (6 Bits)

Output Amplitude (2 Bits)

8

11-Bit Shift Register

8 Bits Data 3 Bits Addr

3-to-8 Decoder

3

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ONET4291PA

SLLS671 – SEPTEMBER 2005

TWO-WIRE INTERFACE AND CONTROL LOGIC

The ONET4291PA uses a two-wire serial interface for digital control of the amplifier bandwidth, output amplitude,
and LOS threshold. A simplified block diagram of this interface is given in Figure 3 .

SDA and SCK are inputs for the serial data and the serial clock, respectively, and can be driven by a
microprocessor. Both inputs have 100-k Ω pullup resistors to V
is recommended.

A write cycle consists of a START command, 3 address bits with MSB first, 8 data bits with MSB first, and a
STOP command. In idle mode, both the SDA and SCK lines are at a high level.

A START command is initiated by a falling edge on SDA with SCK at a high level.
Bits are clocked into an 11-bit-wide shift register while the SCK level is high.
A STOP command is detected on the rising edge of SDA after SCK has changed from a low level to a high level.
At the time of detection of a STOP command, the 8 data bits from the shift register are copied to a selected 8-bit

register. Register selection occurs according to the 3 address bits in the shift register, which are decoded to 8
independent select signals using a 3-to-8 decoder block.

In the ONET4291PA, only addresses 4 (100b) and 5 (101b) are used.

. For driving these inputs, an open-drain output

CC

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Figure 3. Simplified Two-Wire Interface Block Diagram

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START STOP1 0 1 0 1 1

SDA

SCK

DTA

R

DTA

F

STRT

HLD

CLK

R

CLK

F

CLK

HI

DTA

HI

DTA

STP

DTA

WT

DTA

HLD

STOP

STP

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ONET4291PA

SLLS671 – SEPTEMBER 2005

The timing definition for the serial data signal SDA and the serial clock signal SCK is shown in Figure 4 .

PARAMETER DESCRIPTION MIN MAX UNIT

STRT

HLD

CLK

, DTA

R

CLK

, DTA

F

CLK

HI

DTA

HI

DTA

STP

DTA

WT

DTA

HLD

STOP

STP

START hold time Time required from data falling edge to clock falling edge at START 10 ns
Clock and data rise time Clock and data rise time 10 ns

R

Clock and data fall time Clock and data fall time 10 ns

F

Clock high time Minimum clock high period 50 ns
Data high time Minimum data high period 100 ns
Data setup time Minimum time from data rising edge to clock rising edge 10 ns
Data wait time Minimum time from data falling edge to data rising edge 50 ns
Data hold time Minimum time from clock falling edge to data falling edge 10 ns
STOP setup time Minimum time from clock rising edge to data rising edge at STOP 10 ns

Figure 4. Two-Wire Interface Timing Diagram

The register mapping for register addresses 4 (100b) and 5 (101b) is shown in Table 1 and Table 2 , respectively.

Table 1. Register 4 (100b) Mapping

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

BW3 BW2 BW1 BW0 – – – –

Table 2. Register 5 (101b) Mapping

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

A1 A0 R5 R4 R3 R2 R1 R0

Table 3 through Table 5 describe circuit functionality based on the register settings.

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ONET4291PA

SLLS671 – SEPTEMBER 2005

BW3 BW2 BW1 BW0 TYP UNIT

0 0 0 0 4.39 GHz
0 0 0 1 3.91 GHz
0 0 1 0 3.47 GHz
0 0 1 1 3.03 GHz
0 1 0 0 2.81 GHz
0 1 0 1 2.31 GHz
0 1 1 0 1.82 GHz
0 1 1 1 1.60 GHz
1 0 0 0 1.55 GHz
1 0 0 1 1.33 GHz
1 0 1 0 1.11 GHz
1 0 1 1 1.03 GHz
1 1 0 0 0.86 GHz
1 1 0 1 0.82 GHz
1 1 1 0 0.76 GHz
1 1 1 1 0.73 GHz

Table 3. Bandwidth Selection

Table 4. Output Amplitude Selection

A1 A0 TYP UNIT

0 0 400 mV
0 1 600 mV
1 0 800 mV
1 1 1000 mV

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Table 5. LOS-Threshold Digitally Controlled Resistor Selection

R5 R4 R3 R2 R1 R0 TYP UNIT

0 0 0 0 0 0 86.75 k Ω
0 0 0 0 0 1 85.5 k Ω
0 0 0 0 1 0 84.25 k Ω
0 0 0 0 1 1 83 k Ω
0 0 0 1 0 0 81.75 k Ω
0 0 0 1 0 1 80.5 k Ω
0 0 0 1 1 0 79.25 k Ω
0 0 0 1 1 1 78 k Ω
0 0 1 0 0 0 76.75 k Ω
0 0 1 0 0 1 75.5 k Ω
0 0 1 0 1 0 74.25 k Ω
0 0 1 0 1 1 73 k Ω
0 0 1 1 0 0 71.75 k Ω
0 0 1 1 0 1 70.5 k Ω
0 0 1 1 1 0 69.25 k Ω
0 0 1 1 1 1 68 k Ω
0 1 0 0 0 0 66.75 k Ω
0 1 0 0 0 1 65.5 k Ω
0 1 0 0 1 0 64.25 k Ω
0 1 0 0 1 1 63 k Ω
0 1 0 1 0 0 61.75 k Ω

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