TEXAS INSTRUMENTS ONET420PA Technical data

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155 Mbps to 4.25 Gbps Limiting Amplifier With LOS and RSSI

FEATURES DESCRIPTION

• Multi-Rate Operation from 155 Mbps up to

4.25 Gbps

• 89 mW Power Consumption

• Input Offset Cancellation

• High Input Dynamic Range

• Output Disable

• CML Data Outputs

• Receive Signal Strength Indicator (RSSI)

• Loss of Signal Detection

• Polarity Select

• Single 3.3-V Supply

• Surface Mount Small Footprint 3-mm × 3-mm

16-Pin QFN Package

• Pin-Compatible with the ONET2501PA and

ONET3301PA

APPLICATIONS

• Multi-Rate OC3 to OC-48 FEC SONET/SDH

Transmission Systems

• 1.0625 Gbps, 2.125 Gbps, and 4.25 Gbps Fibre

Channel Receivers

• Gigabit Ethernet Receivers

ONET4201PA

SLLS652 – NOVEMBER 2005

The ONET4201PA is a versatile high-speed, 3.3-V
limiting amplifier for multiple fiber optic applications
with data rates up to 4.25 Gbps.

This device provides a gain of about 50 dB, which
ensures a fully differential output swing for input
signals as low as 3 mV

The high input signal dynamic range ensures low
jitter output signals even when overdriven with input
signal swings as high as 1200 mV

The ONET4201PA provides a loss of signal detection
as well as a received signal strength indicator.

The part is available in a small footprint 3-mm ×
3-mm 16-pin QFN package and is pin-compatible with
the ONET2501PA and ONET3301PA.

This power efficient limiting amplifier typically
dissipates less than 89 mW and it is characterized for
operation from –40 ° C to 85 ° C.

.

p-p

.

p-p

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2005, Texas Instruments Incorporated

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Input Buffer

DOUT+
DOUT−

DIN+
DIN−

+

Gain Stage

++ +

COC2 COC1

DISABLE
LOS

TH

VCC

GND

OUTPOL

Bandgap Voltage

Reference and

Bias Current

Generation

Gain Stage Gain Stage

Loss of Signal

and

RSSI Detection

Offset

Cancellation

−

RSSI

CML

Output

Buffer

+

− − − −

B0052-01

ONET4201PA

SLLS652 – NOVEMBER 2005

BLOCK DIAGRAM

A simplified block diagram of the ONET4201PA is shown in Figure 1 .
This compact, low power 4.25 Gbps limiting amplifier consists of a high-speed data path with offset cancellation

block, a loss of signal and RSSI detection block, and a bandgap voltage reference and bias current generation
block.

Figure 1. Simplified Block Diagram of the ONET4201PA

HIGH SPEED DATA PATH

The high-speed data signal is applied to the data path by means of the input signal pins DIN+/DIN–. The data
path consists of the input stage with 2 × 50- Ω on-chip line termination to VCC, three gain stages, which provide
the required typical gain of about 50 dB, and a CML output stage. The amplified data output signal is available at
the output pins DOUT+/DOUT–, which provide 2 × 50- Ω back-termination to VCC. The output stage also includes
a data polarity switching function, which is controlled by the OUTPOL input, and a disable function, controlled by
the signal applied to the DISABLE input pin.

Offset cancellation compensates for internal offset voltages and thus ensures proper operation even for very
small input data signals.

The low frequency cutoff is typically as low as 25 kHz with the built-in filter capacitor.
For applications which require even lower cutoff frequencies, an additional external filter capacitor may be

connected to the COC1/COC2 pins.

LOSS OF SIGNAL AND RSSI DETECTION

The output signal of the input buffer is monitored by the loss of signal and RSSI detection circuitry. In this block a
signal is generated that is linearly proportional to the input amplitude over a wide input voltage range. This signal
is available at the RSSI output pin.

Furthermore, this circuit block compares the input signal to a threshold which can be programmed by means of
an external resistor connected to the TH pin. If the input signal falls below the specified threshold, a loss of signal
is indicated at the LOS pin.

The relation between the LOS assert voltage V
the TH pin can be approximated as given below:

2

(in mV

AST

) and the external resistor R

p-p

(in k Ω ) connected to

TH

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R

TH



20.8 k



V

AST

mV

pp

 1



 300 

V

AST



20.8 mV

pp

RTHk  0.3

 1 mV

pp

GND

COC2

COC1

RSSI

1
2
3
4

VCC
DIN+
DIN−

VCC

RGT PACKAGE

(TOP VIEW)

12
11
10

9

16

VCC
DOUT+
DOUT−
OUTPOL

15 14 13

5 6 7 8

TH

DISABLE

LOS

GND

P0019-01

EP

ONET4201PA

SLLS652 – NOVEMBER 2005

BANDGAP VOLTAGE AND BIAS GENERATION

The ONET4201PA limiting amplifier is supplied by a single 3.3-V ± 10% supply voltage connected to the VCC
pins. This voltage is referred to ground (GND).

An on-chip bandgap voltage circuit generates a supply voltage independent reference from which all other
internally required voltages and bias currents are derived.

PACKAGE

For the ONET4201PA a small footprint 3-mm × 3-mm 16-pin QFN package, with a lead pitch of 0,5 mm, is used.
The pin out is shown in Figure 2 .

(1)

(2)

Figure 2. Pinout of ONET4201PA in a 3mm x 3mm 16 Pin QFN Package (Top View)

TERMINAL FUNCTIONS

TERMINAL

NO. NAME

1, 4, 12 VCC supply 3.3-V ± 10% supply voltage
2 DIN+ analog-in Non-inverted data input. On-chip 50- Ω terminated to VCC.
3 DIN– analog-in Inverted data input. On-chip 50- Ω terminated to VCC.
5 TH analog-in LOS threshold adjustment with resistor to GND.
6 DISABLE CMOS-in Disables CML output stage when set to high level.
7 LOS CMOS-out High level indicates that the input signal amplitude is below the programmed threshold level.
8, 16, EP GND supply Circuit ground. Exposed die pad (EP) must be grounded.

9 OUTPOL CMOS-in
10 DOUT– CML-out Inverted data output. On-chip 50- Ω back-terminated toVCC.

11 DOUT+ CML-out Non-inverted data output. On-chip 50- Ω back-terminated to VCC.

TYPE DESCRIPTION

Output data signal polarity select (internally pulled high). Setting to a high level or leaving the pin
open selects normal polarity. Low level selects inverted polarity.

3

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ONET4201PA

SLLS652 – NOVEMBER 2005

TERMINAL FUNCTIONS (continued)

TERMINAL

NO. NAME

13 RSSI analog-out

14 COC1 analog and COC2 (pin 15).

15 COC2 analog and COC1 (pin 14).

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V

CC

V

, V

DIN+

DIN-

VTH, V
V

DOUT–

V

COC,DIFF

V

DIN,DIFF

I

LOS

I

, I

DIN+

ESD ESD rating at all pins 2 kV (HBM)
T

J(max)

T

STG

T

A

T

LEAD

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

, V

DISABLE

, V

RSSI

, I

DIN–

, V

LOS

, V

, V

COC1

, I

DOUT+

DOUT–

TYPE DESCRIPTION

Analog output voltage proportional to the input data amplitude. Indicates the strength of the
received signal (RSSI).

Offset cancellation filter capacitor terminal 1. Connect an additional filter capacitor between this pin
To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).

Offset cancellation filter capacitor terminal 2. Connect an additional filter capacitor between this pin
To disable the offset cancellation loop connect COC1 and COC2 (pins 14 and 15).

(1)

VALUE/UNIT

Supply voltage
Voltage at DIN+, DIN–

, V

OUTPOL

COC2

, Voltage at TH, DISABLE, LOS, OUTPOL, DOUT+, DOUT-, RSSI, –0.3 V to 4.0 V

DOUT+

COC1, COC2

(2)

(2)

(2)

–0.3 V to 4.0 V

0.5 V to 4.0 V

Differential voltage between COC1 and COC2 ±1 V
Differential voltage between DIN+ and DIN– ±2.5 V
Current into LOS -1 to 9 mA
Continuous current at inputs and outputs –25 mA to 25 mA

Maximum junction temperature 125°C
Storage temperature range –65 to 85°C
Characterized free-air operating temperature range –40 to 85°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

RECOMMENDED OPERATING CONDITIONS

V

CC

T

A

V

IH

V

IL

4

Supply voltage 3 3.3 3.6 V
Operating free-air temperature –40 85 ° C
CMOS input high voltage 2.1 V
CMOS input low voltage 0.6 V

MIN TYP MAX UNIT