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This serial synchronous interface can drive two serial external components.
For the external devices, this interface is compatible with the MicroWire
standard and is seen as the master.
Notational Conventions
This document uses the following conventions.
- Hexadecimal numbers are shown with the suffix h. For example, the
Preface
Read This First
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the OMAP5910 device and related
peripherals. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at
This serial synchronous interface can drive two serial external components.
For the external devices, this interface is compatible with the MicroWire
standard and is seen as the master (see Figure 1).
A transmit DMA mode is available.
Figure 1.Block Diagram
MicroWire Interface
Clock register
MPUXOR_CK
IPB
Clock
enable
Setup registers
Control−and−status
register
Clock
divider
UWIRE.CS[3:0]
1.1MicroWire Registers
The starting address in the peripheral range (hex) is FFFB:3000
Table 1 lists the MicroWire registers. Table 2 through Table 9
describe the individual registers.
Control
logic
2
UWIRE.SCLK
DMA_REQ to system DMA_REQ[6:0]
Inth lvl2 (2,3) - edge
Transmit data register
(16 bits)
Receive data register
(16 bits)
UWIRE.SDO
UWIRE.SDI
Table 1.MicroWire Registers
RegisterDescriptionR/WSizeAddressOffset
TDRTransmit data registerW16 bitsFFFB:30000x00
RDRReceive data registerR16 bitsFFFB:30000x00
9MicroWire InterfaceSPRU686
MicroWire Interface
Table 1.MicroWire Registers (Continued)
RegisterOffsetAddressSizeR/WDescription
CSRControland status registerR/W16 bitsFFFB:30000x04
SR1Setup register 1R/W16 bitsFFFB:30000x08
SR2Setup register 2R/W16 bitsFFFB:30000x0C
SR3Setup register 3R/W16 bitsFFFB:30000x10
SR4Setup register 4R/W16 bitsFFFB:30000x14
SR5
Setup register 5R/W16 bitsFFFB:30000x18
Table 2.Transmit-Data Register (TDR)
BitsFieldDescription
15−0TDData to transmitUndefined
Whatever its size, the word must be aligned on the most significant bit (MSB)
side.
Note:
The MSB (bit 15) is the first transmitted bit.
Reset
Value
Table 3.Receive-Data Register (RDR)
BitsFieldDescription
15−0RDReceived dataUndefined
Whatever its size, the word is aligned on the least significant bit (LSB) side.
Note:
The LSB (bit 0) is the last received bit.
MicroWire Interface10SPRU686
Reset
Value
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