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This serial synchronous interface can drive two serial external components.
For the external devices, this interface is compatible with the MicroWire
standard and is seen as the master.
Notational Conventions
This document uses the following conventions.
- Hexadecimal numbers are shown with the suffix h. For example, the
Preface
Read This First
following number is 40 hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
The following documents describe the OMAP5910 device and related
peripherals. Copies of these documents are available on the Internet at
www.ti.com. Tip: Enter the literature number in the search box provided at
This serial synchronous interface can drive two serial external components.
For the external devices, this interface is compatible with the MicroWire
standard and is seen as the master (see Figure 1).
A transmit DMA mode is available.
Figure 1.Block Diagram
MicroWire Interface
Clock register
MPUXOR_CK
IPB
Clock
enable
Setup registers
Control−and−status
register
Clock
divider
UWIRE.CS[3:0]
1.1MicroWire Registers
The starting address in the peripheral range (hex) is FFFB:3000
Table 1 lists the MicroWire registers. Table 2 through Table 9
describe the individual registers.
Control
logic
2
UWIRE.SCLK
DMA_REQ to system DMA_REQ[6:0]
Inth lvl2 (2,3) - edge
Transmit data register
(16 bits)
Receive data register
(16 bits)
UWIRE.SDO
UWIRE.SDI
Table 1.MicroWire Registers
RegisterDescriptionR/WSizeAddressOffset
TDRTransmit data registerW16 bitsFFFB:30000x00
RDRReceive data registerR16 bitsFFFB:30000x00
9MicroWire InterfaceSPRU686
MicroWire Interface
Table 1.MicroWire Registers (Continued)
RegisterOffsetAddressSizeR/WDescription
CSRControland status registerR/W16 bitsFFFB:30000x04
SR1Setup register 1R/W16 bitsFFFB:30000x08
SR2Setup register 2R/W16 bitsFFFB:30000x0C
SR3Setup register 3R/W16 bitsFFFB:30000x10
SR4Setup register 4R/W16 bitsFFFB:30000x14
SR5
Setup register 5R/W16 bitsFFFB:30000x18
Table 2.Transmit-Data Register (TDR)
BitsFieldDescription
15−0TDData to transmitUndefined
Whatever its size, the word must be aligned on the most significant bit (MSB)
side.
Note:
The MSB (bit 15) is the first transmitted bit.
Reset
Value
Table 3.Receive-Data Register (RDR)
BitsFieldDescription
15−0RDReceived dataUndefined
Whatever its size, the word is aligned on the least significant bit (LSB) side.
Note:
The LSB (bit 0) is the last received bit.
MicroWire Interface10SPRU686
Reset
Value
Table 4.Control-and-Status Register (CSR)
BitsFieldValueDescription
MicroWire Interface
Reset
Value
15RDRBRDRB bit = 1 indicates that the receive (RDR) area is full.
When the controller reads the content of the RDR, this bit
is cleared.
This bit is read only.
14CSRBCSRB bit = 0 indicates that the control and status register
(CSR) is ready to receive new data.
After starting a MicroWire transfer with the CSR, this bit is
set to 1. When the corresponding action has been done,
the CSRB is reset. This bit is controlled by a MicroWire
internal state machine running on the F_INT internal clock
(12 MHz/N). If the CSR is read just after being written and
the MPU is running at a high frequency (60 MHz or 120
MHz, for instance) compared to the internal clock, the
CSRB status bit may still be low for the first read access.
The CSRB latency is 0 if the transfer was initiated by
modifying the CS_CMD bit, but it can be 0−3 cycles if
initiated by the START bit. Some suggested work-arounds
are to: (a) have a few NOPs between initiating a MicroWire
transfer and checking the CSRB status or( b) check that
the CSRB first has a high value on an initial read before it
goes low on a subsequent read.
This bit is read only.
0
0
13START1Start a write and/or a read process.
This bit is automatically reset by the internal logic when a
write or a read process is activated.
Send the NB_BITS_WR bits (contained in TDR) to the
serial output DO. If the NB_BITS_WR is equal to zero,
then the write process is not started.
Receive the NB_BITS_RD bits from the serial input DI and
store them in the RDR.
12CS_CMD1Set the chip-select of the selected device to its active level.0
This register sets up the serial interface for the first and the second external
components.
Table 5.Setup Register 1 (SR1)
BitsFieldValueDescription
11−6Reserved
Reset
Value
5CS0_CHKBefore activating a write process, determines if the
external device is ready.
0No check is done and the write process is immediately
executed.
1If the DI signal is low, the interface considers the
external component busy; if the DI is high, the interface
considers that the first external component is ready and
starts the write process.
Used when the CS0 is selected.
4−3CS0_FRQDefines the frequency of the serial clock, SCLK, when
the CS0 is selected (F_INT is the frequency of the
internal clock to the MicroWire control logic as defined in
register SR3).
00F_INT/2
01F_INT/4
10F_INT/8
11Reserved
Undefined
Undefined
2
CS0CS_LVLDefines the active level of the chip-select by CS00
MicroWire Interface12SPRU686
Table 5.Setup Register 1 (SR1) (Continued)
Bits
DescriptionValueField
MicroWire Interface
Reset
Value
1CS0_EDGE_WRWhen the CS0 is selected, this bit defines the active
edge of the serial clock, SCLK, used to write data to the
serial input D0. (Output data is generated on this edge)
0Falling (the serial clock is not inverted)
0Rising (when the serial clock is inverted)
1Rising (the serial clock is not inverted)
1Falling (when the serial clock is inverted)
0CS0_EDGE_RDWhen the CS0 is selected, this bit defines the active
edge of the serial clock, SCLK, used to read data from
the serial input DI. (Input data is strobed on this edge)
0Falling (the serial clock is not inverted)
0Rising (when the serial clock is inverted)
1Rising (the serial clock is not inverted)
1Falling (when the serial clock is inverted)
Note:
Undefined
Undefined
The content of this register must not be changed when a read or write process is running.
This register sets up the serial interface for the first and the second external
components.
13MicroWire InterfaceSPRU686
MicroWire Interface
Table 6.Setup Register 2 (SR2)
BitsFieldValueDescription
Reset
Value
11CS3_CHKBefore activating a write process, determines
if the external device is ready.
0No check is done and the write process is
immediately executed.
1If the DI signal is low, the interface considers
the external component busy; if the DI is high,
the interface considers that the first external
component is ready and starts the write
process.
Used when the CS3 is selected.
10−9CS3_FRQDefines the frequency of the serial clock,
SCLK, when the CS3 is selected
00F_INT/2
01F_INT/4
10F_INT/8
11Undefined
8CS3CS_LVLDefines the active level of the CS3 chip-select0
Undefined
Undefined
7CS3_EDGE_WRWhen the CS3 is selected, this bit defines the
active edge of the serial clock, SCLK, used to
write data to the serial input D0. (Output data
is generated on this edge)
0Falling (the serial clock is not inverted)
0Rising (when the serial clock is inverted)
1Rising (the serial clock is not inverted)
1Falling (when the serial clock is inverted)
MicroWire Interface14SPRU686
Undefined
Table 6.Setup Register 2 (SR2)
Bits
MicroWire Interface
Reset
DescriptionValueField
Value
6CS3_EDGE_RDWhen the CS3 is selected, this bit defines the
active edge of the serial clock, SCLK, used to
read data from the serial input DI. (Input data
is strobed on this edge)
0Falling (the serial clock is not inverted)
0Rising (when the serial clock is inverted)
1Rising (the serial clock is not inverted)
1Falling (when the serial clock is inverted)
5−0
Reserved
Note:
The content of this register must not be changed when a read or write process is running.
This register sets up the serial interface for the internal clock.
Table 7.Setup Register 3 (SR3)
Undefined
BitsFieldValueDescription
2−1CK_FREQDefines the frequency of the internal clock, F_INT, when
the CLK_EN = 1. All the internal logic is controlled by
F_INT (F is the frequency of the external input clock).
00MPUOXR_CK/2
01MPUOXR_CK/4
10MPUOXR_CK/7
11MPUOXR_CK/10
0CLK_EN0Switch off the clock0
1Switch on the clock
Note:
The content of this register must not be changed when a read or write process is running.
Reset
Value
00
15MicroWire InterfaceSPRU686
MicroWire Interface
This register sets up the serial-clock polarity.
Table 8.Setup Register 4 (SR4) (Read/Write)
BitsFieldValueDescription
Reset
Value
0CLK_IN0
The serial clock is not inverted
1
The serial clock is inverted
Note:
Content of this register must not be changed when a read or write process is running.
Table 9.Setup Register 5 (SR5) (Read/Write)
BitsFieldValueDescription
3CS_TOGGLE_TX_ENCS_TOGGLE_TX_EN is possible only in the
autotransmit mode.
When in the autotransmit mode with
CS_TOGGLE_TX_EN inactive, the CS does not
go to its active level automatically. Control the CS
with the CS_CMD bit of the control and status
register (CSR) in the software.
0
Reset
Value
0
2AUTO_TX_ENIn the autotransmit mode, the CS_CMD and
MicroWire Interface16SPRU686
0The CS_toggle transmit mode is disabled.
1The CS_toggle transmit mode is enabled.
0
START bits of the control and status register
(CSR) are not used. A hardware state machine
detects a TXD write and automatically sets the
programmed CS to its active value, then starts
the transmission.
The CS_CMD and the START bits in the control
and status register (CSR) are not updated during
the autotransmit mode.
0The autotransmit mode is disabled.
1The autotransmit mode is enabled.
Table 9.Setup Register 5 (SR5) (Read/Write)
Bits
DescriptionValueField
MicroWire Interface
Reset
Value
1IT_ENIn the IT mode, an interrupt is generated each
time a word has been transferred or received.
This interrupt is a negative edge-triggered
interrupt. A status register (IST) allows the CPU
to know which interrupt (receive or/and transmit)
occurred.
0The IT mode is disabled.
1The IT mode is enabled.
0DMA_TX_EN0The DMA transmit mode is disabled.0
1The DMA transmit mode is enabled.
Note:
The content of this register must not be changed when a read or write
process is running.
Set up the DMA, IT, AUTO_TX, and CS_TOGGLE modes in this register.
In the DMA mode, a DMA request is initiated each time a transmission slot is
available.
0
The maximum word size in the DMA mode is 16 bits.
Notes:
Another CS cannot be used in the normal or DMA mode when a DMA mode
is active on one specific CS.
To use the MicroWire in the DMA transmit modes, the DMA_EN and
AUTO_TX_EN must be enabled, and IT_EN is best disabled. The
AUTO_TX_EN can be active when the DMA_EN is disabled.
1.2Protocol Description
The serial port must be configured in order to use the setup registers.
This interface can only drive one device at a given time. Therefore, the
chip-select of the selected device must be set to its active level before starting
any read or write process.
17MicroWire InterfaceSPRU686
MicroWire Interface
After the loading of the transmit data register (TDR), a write process is
activated by setting the START bit to 1 and by writing a value different from zero
to the NB_BITS_WR field.
A read process is always simultaneous with a write process, which means that
at every serial clock, SCLK, cycle data is read. After having finished a write
process (if necessary), a number (defined by the NB_BITS_RD) of SCLK
cycles is generated to allow the storage of data from the serial input DI.
The transmitted data word is shifted out on the rising or falling edge of the serial
clock (according to the value of the CSx_EDGE_WR bits of the setup
registers). The received data word is shifted in on the falling or rising edge of
the serial clock (according to the value of the CSx_EDGE_RD bits of the setup
registers). When the CSx_EDGE_WR and CSx_EDGE_RD bits have the
same value, it is assumed that the device behavior is the one shown in
Figure 2. Otherwise, the required behavior of the external device is shown in
Figure 3.
Figure 2.Behavior of a X25C02 EEPROM Read Cycle
WIRE_NCS
UWIRE.SCLK
UWIRE.SDO
UWIRE.SDI
000000A7
1 1A6 A5 A4 A3 A2 A1 A0
On the DO line, data is generated from the MicroWire interface on the SLCK
falling edge and read by the EEPROM interface on the SCLK rising edge.
On the DI line, data is generated from the EEPROM interface on the SCLK
falling edge and read by the MicroWire interface on the SCLK falling edge.
Figure 3.Behavior of a XL93LC66 EEPROM Read Cycle
WIRE_NCS
UWIRE_SCLK
UWIRESDO
UWIRE_SDI
110
A7 A6 A5 A4 A3 A2 A1 A0
D15
D6 D5 D4D1 D0
D7
D14 D13D1 D0
On the DO line, data is generated from the MicroWire interface on the SLCK
falling edge and read by the EEPROM interface on the SCLK rising edge.
MicroWire Interface18SPRU686
MicroWire Interface
On the DI line, data is generated from the EEPROM interface on the SCLK
rising edge and read by the MicroWire interface on the SCLK rising edge.
1.3Example of Protocol Using a Serial EEPROM (XL93LC66)
Set up the interface by writing the following values in setup register 1 (SR1):
- CS_EDGE_RD = 1
- CS_EDGE_WR = 0
- CSCS_LVL = 1
- CS_FRQ = 00
- CS_CHK = 1
In this example, only two cycles (read and write) are described.
1.3.1Read Cycle
1)Set the following fields of the control and status register (CSR):
11) Wait for CSRB to go low, which indicates the CSR is ready to receive new
data. It is advised to read the bit before and after every write access to the
CSR to check the status.
12) Set the following fields of the control and status register (CSR):
JINDEX: 01
JCS_CMD: 0
JSTART: 0
1.5Example of Protocol Using the Autotransmit Mode
The autotransmit mode is controlled by the setup register 5 (SR5). The
following example configures the MicroWire for a read access on the CS0 with
the serial clock out inverted, the CS autotoggle enabled, the DMA request
disabled, and the interrupt enabled:
MicroWire Interface22SPRU686
MicroWire Interface
1)SR5 = DMA_TX_EN: 0
IT_EN: 1
AUTO_TX_EN: 1
CS_TOGGLE_TX_EN: 1
2)SR1 = CS0_EDGE_RD: 0
CS0_EDGE_WR: 1
CS0CS_LVL: 0
CS0_FREQ: 00
CS0_CHK: 1
Note:
The data out is latched on the falling edge of the serial clock. The data in is
sampled on the rising edge.
3)SR3 = CLK_EN: 1
CK_FREQ: 00 (must wait for 1 external clock + 1 F_INT cycle before any
other register access)
4)SR4 = CLK_IN: 1
5)Set the following fields of the control and status register (CSR):
6)Wait for the CSRB = 0 of the control and status register (CSR).
7)Load the transmit data register (TDR) with:
J A6 A5 A4 A3 A2 A1 A0 x x x x x x x x x x: Don’t care
JA6 ... A0: Address of the selected memory register
The transfer is automatically started.
8)Wait until the CSRB = 0 and RDRB = 1 (status bits of CSR).
9)Read the content of the receive data register (RDR).
10) To continue reading the data external component, go to 5 else go to 11.
23MicroWire InterfaceSPRU686
MicroWire Interface
11) Release the autotransmit mode: SR5 = AUTO_TX_EN: 0.
12) END
The corresponding behavior of the serial interface is described in Figure 4.
Figure 4.Read Cycle in the Autotransmit Mode
WIRE_NCS
UWIRE_SCCLK
UWIRE_SDO
UWIRE_SDI
A6A5A4A3A2A1A0
D4D3D2D1D0
1.6Example of the Autotransmit Mode With DMA Support
The autotransmit mode and DMA mode are controlled by the setup register 5
(SR5). The following example configures the MicroWire for a 16-bit write
access on the CS1 with the serial clock out not inverted, the CS auto toggle
enabled, the DMA request enabled, and the interrupt disabled:
1)Set up and enable the DMA channel.
2)Program the configuration registers SR1, SR3, and SR4.
3)Check the CSRB status to ensure that the peripheral is ready to receive
(low).
4)Program the control and status register (CSR) as follows: