Texas Instruments MSP430G2533, MSP430G2433, MSP430G2333, MSP430G2233, MSP430G2403 Datasheet

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MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233

MSP430G2x33, MSP430G2x03 Mixed-Signal Microcontrollers

1 Device Overview

1.1 Features

• Low Supply-Voltage Range: 1.8 V to 3.6 V

• Ultra-Low Power Consumption – Active Mode: 230 µA at 1 MHz, 2.2 V – Standby Mode: 0.5 µA – Off Mode (RAM Retention): 0.1 µA

• Five Power-Saving Modes

• Ultra-Fast Wake up From Standby Mode in Less Than 1 µs

• 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time

• Basic Clock Module Configurations – Internal Frequencies up to 16 MHz With Four

Calibrated Frequencies

– Internal Very-Low-Power Low-Frequency (LF)

Oscillator – 32-kHz Crystal – External Digital Clock Source

• Two 16-Bit Timer_A With Three Capture/Compare Registers

• Up to 24 Capacitive-Touch Enabled I/O Pins

MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

• Universal Serial Communication Interface (USCI) – Enhanced UART Supports Automatic Baud-

Rate Detection (LIN) – IrDA Encoder and Decoder – Synchronous SPI – I2C

• 10-Bit 200-ksps Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold, and Autoscan (See Table 3-1)

• Brownout Detector

• Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse

• On-Chip Emulation Logic With Spy-Bi-Wire Interface

• Section 3 Summarizes Available Family Members

• Package Options – TSSOP: 20 Pin, 28 Pin – PDIP: 20 Pin – QFN: 32 Pin

• For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide (SLAU144)

1.2 Applications

• Power Management

• Sensor Interface

1.3 Description

The TI MSP family of ultra-low-power microcontrollers consists of several devices that feature different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in less than 1 µs.

The MSP430G2x03 and MSP430G2x33 devices are ultra-low-power mixed-signal microcontrollers with built-in 16-bit timers, up to 24 I/O capacitive-touch enabled pins, and built-in communication capability using the USCI. In addition, the MSP430G2x33 family members have a 10-bit ADC. See Section 3 for configuration details.

Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system.

• Capacitive Touch

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Clock

System

Brownout

Protection

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15-Bit

Timer0_A3

3 CC

registers

16-MHz

CPU

including

16 registers

Emulation

2BP

JTAG

interface

SMCLK

ACLK

Port P1

8 I/Os,

interrupt

capability,

pullup or pulldown resistors

P1.x

P2.x

Port P2

8 I/Os,

interrupt

capability,

pullup or pulldown resistors

Spy-Bi-

Wire

Timer1_A3

3 CC

registers

XIN

XOUT

Port P3

8 I/Os, pullup or pulldown resistors

P3.x

8 8

RAM

512B 256B

Flash

16KB

8KB 4KB 2KB

USCI A0

UART,

LIN, IrDA,

SPI

USCI B0

SPI, I C

ADC

10 bit,

8 channel,

autoscan, 1-channel

DMA

MDB

MAB

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

www.ti.com

PART NUMBER PACKAGE BODY SIZE

MSP430G2533IRHB VQFN (32) 5 mm × 5 mm

MSP430G2533IPW

MSP430G2533IN PDIP (20) 24.33 mm × 6.35 mm

(1) For the most current part, package, and ordering information, see the Package Option Addendum in

Section 8, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 8.

1.4 Functional Block Diagrams

Figure 1-1 shows the functional block diagram of the MSP430G2x33 MCUs.

Device Information

(1)

TSSOP (28) 9.7 mm × 4.4 mm TSSOP (20) 6.5 mm × 4.4 mm

(2)

NOTE: Port P3 is available on 28-pin and 32-pin devices only.

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

Figure 1-1. Functional Block Diagram, MSP430G2x33

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MSP430G2203

Clock

System

Brownout

Protection

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15-Bit

Timer0_A3

3 CC

registers

16-MHz

CPU

including

16 registers

Emulation

2BP

JTAG

interface

SMCLK

ACLK

Port P1

8 I/Os,

interrupt

capability,

pullup or pulldown resistors

P1.x

P2.x

Port P2

8 I/Os,

interrupt

capability,

pullup or pulldown resistors

Spy-Bi-

Wire

Timer1_A3

3 CC

registers

XIN

XOUT

Port P3

8 I/Os, pullup or pulldown resistors

P3.x

8 8

RAM

256B

Flash

8KB 4KB 2KB

USCI A0

UART,

LIN, IrDA,

SPI

USCI B0

SPI, I C

MDB

MAB

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Figure 1-2 shows the functional block diagram of the MSP430G2x03 MCUs.

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233

MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

NOTE: Port P3 is available on 28-pin and 32-pin devices only.

Figure 1-2. Functional Block Diagram, MSP430G2x03

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

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MSP430G2203

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

Table of Contents

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1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagrams........................... 2

2 Revision History ......................................... 5

3 Device Comparison ..................................... 6

3.1 Related Products ..................................... 7

4 Terminal Configuration and Functions.............. 8

4.1 Pin Diagrams ......................................... 8

4.2 Signal Descriptions.................................. 10

5 Specifications........................................... 13

5.1 Absolute Maximum Ratings ........................ 13

5.2 ESD Ratings ........................................ 13

5.3 Recommended Operating Conditions............... 13

5.4 Active Mode Supply Current Into VCCExcluding

External Current..................................... 14

5.5 Typical Characteristics, Active Mode Supply Current (Into V

5.6 Low-Power Mode Supply Currents (Into VCC)

Excluding External Current.......................... 16

5.7 Typical Characteristics, Low-Power Mode Supply

Currents ............................................. 17

5.8 Thermal Resistance Characteristics ................ 18

5.9 Schmitt-Trigger Inputs, Ports Px .................... 19

5.10 Leakage Current, Ports Px.......................... 19

5.11 Outputs, Ports Px ................................... 19

5.12 Output Frequency, Ports Px ........................ 19

5.13 Typical Characteristics – Outputs................... 20

5.14 Pin-Oscillator Frequency – Ports Px ................ 21

5.15 Typical Characteristics – Pin-Oscillator Frequency. 21

5.16 POR, BOR .......................................... 22

5.17 Main DCO Characteristics .......................... 24

5.18 DCO Frequency..................................... 24

5.19 Calibrated DCO Frequencies, Tolerance ........... 25

5.20 Wake-up Times From Lower-Power Modes (LPM3,

LPM4) .............................................. 26

5.21 Typical Characteristics, DCO Clock Wake-up Time

From LPM3 or LPM4................................ 26

5.22 Crystal Oscillator, XT1, Low-Frequency Mode ..... 27

5.23 Internal Very-Low-Power Low-Frequency Oscillator

(VLO)................................................ 27

5.24 Timer_A ............................................. 27

)............................................ 15

5.25 USCI (UART Mode)................................. 28

5.26 USCI (SPI Master Mode)............................ 28

5.27 USCI (SPI Slave Mode)............................. 29

5.28 USCI (I

5.29 10-Bit ADC, Power Supply and Input Range

5.30 10-Bit ADC, Built-In Voltage Reference

5.31 10-Bit ADC, External Reference (MSP430G2x33

5.32 10-Bit ADC, Timing Parameters (MSP430G2x33

5.33 10-Bit ADC, Linearity Parameters (MSP430G2x33

5.34 10-Bit ADC, Temperature Sensor and Built-In V

5.35 Flash Memory ....................................... 34

5.36 RAM................................................. 35

5.37 JTAG and Spy-Bi-Wire Interface.................... 35

5.38 JTAG Fuse .......................................... 35

C Mode) .................................... 30

Conditions (MSP430G2x33 Only)................... 31

(MSP430G2x33 Only)............................... 32

Only)................................................. 33

(MSP430G2x33 Only)............................... 34

MID

6 Detailed Description ................................... 36

6.1 CPU ................................................. 36

6.2 Instruction Set....................................... 37

6.3 Operating Modes.................................... 38

6.4 Interrupt Vector Addresses.......................... 39

6.5 Special Function Registers (SFRs) ................. 40

6.6 Memory Organization ............................... 41

6.7 Bootloader (BSL).................................... 41

6.8 Flash Memory ....................................... 42

6.9 Peripherals .......................................... 42

6.10 I/O Port Diagrams................................... 48

7 Device and Documentation Support ............... 64

7.1 Getting Started and Next Steps..................... 64

7.2 Device Nomenclature ............................... 64

7.3 Tools and Software ................................. 66

7.4 Documentation Support ............................. 68

7.5 Related Links........................................ 70

7.6 Community Resources .............................. 71

7.7 Trademarks.......................................... 71

7.8 Electrostatic Discharge Caution..................... 71

7.9 Glossary............................................. 71

8 Mechanical, Packaging, and Orderable

Information .............................................. 72

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

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MSP430G2203

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233

MSP430G2403, MSP430G2303, MSP430G2203

www.ti.com

SLAS734G –APRIL 2011–REVISED APRIL 2016

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from May 2, 2013 to April 27, 2016 Page

• Document format and organization changes throughout, including addition of section numbering........................ 1

• Added Device Information table .................................................................................................... 2

• Added Section 3.1, Related Products ............................................................................................. 7

• Moved Section 5, Specifications .................................................................................................. 13

• Added Section 5.2, ESD Ratings.................................................................................................. 13

• Added Section 5.8, Thermal Resistance Characteristics ...................................................................... 18

• Throughout document, changed all instances of "bootstrap loader" to "bootloader"....................................... 39

• Changed all instances of "INCHx = 0x1010" to "INCHx = 1010b" in Table 6-11, Labels Used by the ADC

Calibration Tags ..................................................................................................................... 43

• Moved and renamed Section 6.10, I/O Port Diagrams......................................................................... 48

• Added notes to UCB0STE and UCA0CLK in Table 6-18 ...................................................................... 53

• Added notes to UCB0CLK and UCA0STE in Table 6-19 ...................................................................... 55

• Added "and PW28" to title of Section 6.10.8 .................................................................................... 62

• Added "and PW28" to title of Table 6-23......................................................................................... 63

• Added Section 7, Device and Documentation Support......................................................................... 64

• Added Section 8, Mechanical, Packaging, and Orderable Information ...................................................... 72

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

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MSP430G2203

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

3 Device Comparison

Table 3-1 compares the available family members.

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Table 3-1. Device Comparison

DEVICE BSL EEM

MSP430G2533 1 1 16 512 2x TA3 8 1

MSP430G2433 1 1 8 512 2x TA3 8 1

MSP430G2333 1 1 4 256 2x TA3 8 1

MSP430G2233 1 1 2 256 2x TA3 8 1

MSP430G2403 1 1 8 512 2x TA3 – 1

MSP430G2303 1 1 4 256 2x TA3 – 1

MSP430G2203 1 1 2 256 2x TA3 – 1

(1) For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI website

at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

FLASH

(KB)

RAM

(B)

Timer_A

ADC10

CHANNELS

(1)(2)

USCI_A0,

USCI_B0

CLOCK I/O PACKAGE

24 32-QFN

LF, DCO,

VLO

LF, DCO,

VLO

LF, DCO,

VLO

LF, DCO,

VLO

LF, DCO,

VLO

LF, DCO,

VLO

LF, DCO,

VLO

24 28-TSSOP 16 20-TSSOP 16 20-PDIP 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

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MSP430G2203

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3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for MSP 16-Bit and 32-Bit MCUs Low-power mixed-signal processors with smart analog and

digital peripherals for a wide range of industrial and consumer applications.

Products for Ultra-low Power MCUs MSP Ultra-Low-Power microcontrollers (MCUs) from Texas

Instruments (TI) offer the lowest power consumption and the perfect mix of integrated peripherals for a wide range of low-power and portable applications.

Products for MSP430G2x/i2x Low-Cost Industrial MCUs MSP430G2x microcontrollers (MCUs) from

the MSP ultra-low-power MCU series, offers the low power and performance of 16-bit MSP microcontrollers with a feature set targeted at cost sensitive applications.

Companion Products for MSP430G2533 Review products that are frequently purchased or used in

conjunction with this product.

Reference Designs for MSP430G2533 TI Designs Reference Design Library is a robust reference

design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233

MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

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MSP430G2203

PW28

(TOP VIEW)

DVCC

P1.0/TA0CLK/ACLK/A0

P1.3/ADC10CLK/VREF-/VEREF-/A3

P3.0/TA0.2

P3.1/TA1.0

P2.0/TA1.0

P3.5/TA0.1

P3.6/TA0.2

P3.7/TA1CLK

RST/NMI/SBWTDIO

TEST/SBWTCK

XOUT/P2.7

XIN/P2.6/TA0.1

DVSS

P1.6/TA0.1/ TDI/TCLKUCB0SOMI/UCB0SCL/A6/

P1.7/ /A7/TDO/TDIUCB0SIMO/UCB0SDA

P1.1/TA0.0/ A1/UCA0RXD/UCA0SOMI

P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO

P1.4/SMCLK/ TCK/VREF+/VEREF+/A4/UCB0STE/UCA0CLK

P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE

P2.2/TA1.1

P3.2/TA1.1

P3.3/TA1.2

P3.4/TA0.0

P2.3/TA1.0

P2.4/TA1.2

P2.5/TA1.2

P2.1/TA1.1

DVCC

P1.0/TA0CLK/ACLK/A0

P1.3/ADC10CLK/VREF-/VEREF-/A3

P2.0/TA1.0

P2.1/TA1.1

P2.2/TA1.1

P2.3/TA1.0

P2.4/TA1.2

P2.5/TA1.2

RST/NMI/SBWTDIO

TEST/SBWTCK

XOUT/P2.7

XIN/P2.6/TA0.1

DVSS

P1.6/TA0.1/ /TDI/TCLKUC

B0SOMI/UCB0SCL/A6

P1.7/ /A7/TDO/TDIUCB0SIMO/UCB0SDA

P1.1/TA0.0/ A1/UCA0RXD/UCA0SOMI

P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO

P1.4/SMCLK/ /TCK/VREF+/VEREF+/A4UCB0STE/UCA0CLK

P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE

N20

PW20

(TOP VIEW)

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 20-pin N or PW

package.

NOTE: ADC10 is available on MSP430G2x33 devices only. NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.

Figure 4-1. 20-Pin N or PW Package (Top View), MSP430G2x03 and MSP430G2x33

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Figure 4-2 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 28-pin PW

package.

NOTE: ADC10 is available on MSP430G2x33 devices only.

Figure 4-2. 28-Pin PW Package (Top View), MSP430G2x03 and MSP430G2x33

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

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MSP430G2203

RHB32

(TOP VIEW)

P2.1/TA1.1

8NC

P2.2/TA1.1

P3.0/TA0.2

P3.1/TA1.0

P3.2/TA1.1

131415

P3.5/TA0.1

P2.5/TA1.2

P3.6/TA0.2

P3.7/TA1CLK

23 RST/NMI/SBWTDIO

24 TEST/SBWTCK

XOUT/P2.7

XIN/P2.6/TA0.1

AVSS

DVSS

AVCC

DVCC

P1.0/TA0CLK/ACLK/A0/CA0

P1.3/ADC10CLK/VREF-/VEREF-/A3

P1.1/TA0.0/ A1/

UCA0RXD/UCA0SOMI

P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO

P1.4/SMCLK/ /TCK/VREF+/VEREF+/A4UCB0STE/UCA0CLK

P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE

P1.6/TA0.1/ /TDI/TCLKUCB0SOMI/UCB0SCL/A6

P1.7 /TDO/TDI/UCB0SIMO/UCB0SDA/A7

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Figure 4-3 shows the pinout for the MSP430G2x03 and MSP430G2x33 devices in the 32-pin RHB

package.

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233

MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

NOTE: ADC10 is available on MSP430G2x33 devices only.

Figure 4-3. 32-Pin RHB Package (Top View), MSP430G2x03 and MSP430G2x33

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

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MSP430G2203

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233 MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1. Terminal Functions

TERMINAL

NO.

NAME

PW20,

N20

PW28 RHB32

P1.0/ TA0CLK/ Timer0_A, clock signal TACLK input ACLK/ ACLK signal output

2 2 31 I/O

A0 ADC10 analog input A0 P1.1/ TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit UCA0RXD/ USCI_A0 receive data input in UART mode

3 3 1 I/O UCA0SOMI/ USCI_A0 slave data out/master in SPI mode A1 ADC10 analog input A1 P1.2/ TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output UCA0TXD/ USCI_A0 transmit data output in UART mode

4 4 2 I/O UCA0SIMO/ USCI_A0 slave data in/master out in SPI mode A2 ADC10 analog input A2 P1.3/ ADC10CLK/ ADC10, conversion clock output A3/ ADC10 analog input A3

5 5 3 I/O

VREF-/VEREF- ADC10 negative reference voltage P1.4/ SMCLK/ SMCLK signal output UCB0STE/ USCI_B0 slave transmit enable UCA0CLK/ USCI_A0 clock input/output

6 6 4 I/O A4/ ADC10 analog input A4 VREF+/VEREF+ ADC10 positive reference voltage TCK JTAG test clock, input terminal for device programming and test P1.5/ TA0.0/ Timer0_A, compare: Out0 output / BSL receive UCB0CLK/ USCI_B0 clock input/output UCA0STE/ USCI_A0 slave transmit enable

7 7 5 I/O

A5/ ADC10 analog input A5 TMS JTAG test mode select, input terminal for device programming and test P1.6/ TA0.1/ Timer0_A, compare: Out1 output A6/ ADC10 analog input A6 UCB0SOMI/ USCI_B0 slave out/master in SPI mode,

14 22 21 I/O

UCB0SCL/ USCI_B0 SCL I2C clock in I2C mode TDI/TCLK JTAG test data input or test clock input during programming and test

I/O DESCRIPTION

General-purpose digital I/O pin

(1)

General-purpose digital I/O pin

(1)

General-purpose digital I/O pin

(1)

General-purpose digital I/O pin

(1)

General-purpose digital I/O pin

(1)

General-purpose digital I/O pin

(1)

General-purpose digital I/O pin

(1)

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(1) MSP430G2x33 devices only 10

Product Folder Links: MSP430G2533 MSP430G2433 MSP430G2333 MSP430G2233 MSP430G2403 MSP430G2303

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MSP430G2203

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233

MSP430G2403, MSP430G2303, MSP430G2203

www.ti.com

SLAS734G –APRIL 2011–REVISED APRIL 2016

Table 4-1. Terminal Functions (continued)

TERMINAL

NO.

NAME

PW20,

N20

PW28 RHB32

P1.7/ A7/ ADC10 analog input A7 UCB0SIMO/ USCI_B0 slave in/master out in SPI mode

15 23 22 I/O

UCB0SDA/ USCI_B0 SDA I2C data in I2C mode TDO/TDI P2.0/

TA1.0 Timer1_A, capture: CCI0A input, compare: Out0 output P2.1/ TA1.1 Timer1_A, capture: CCI1A input, compare: Out1 output P2.2/ TA1.1 Timer1_A, capture: CCI1B input, compare: Out1 output P2.3/ TA1.0 Timer1_A, capture: CCI0B input, compare: Out0 output P2.4/ TA1.2 Timer1_A, capture: CCI2A input, compare: Out2 output P2.5/ TA1.2 Timer1_A, capture: CCI2B input, compare: Out2 output

8 10 9 I/O

9 11 10 I/O

10 12 11 I/O

11 16 15 I/O

12 17 16 I/O

13 18 17 I/O

XIN/ P2.6/ General-purpose digital I/O pin

19 27 26 I/O TA0.1 Timer0_A, compare: Out1 output XOUT/ P2.7 General-purpose digital I/O pin P3.0/ TA0.2 Timer0_A, capture: CCI2A input, compare: Out2 output P3.1/ TA1.0 Timer1_A, compare: Out0 output P3.2/ TA1.1 Timer1_A, compare: Out1 output P3.3/ TA1.2 Timer1_A, compare: Out2 output P3.4/ TA0.0 Timer0_A, compare: Out0 output P3.5/ TA0.1 Timer0_A, compare: Out1 output P3.6/ TA0.2 Timer0_A, compare: Out2 output P3.7/ TA1CLK Timer1_A, clock signal TACLK input

18 26 25 I/O

- 9 7 I/O

- 8 6 I/O

- 13 12 I/O

- 14 13 I/O

- 15 14 I/O

- 19 18 I/O

- 20 19 I/O

- 21 20 I/O

RST/ NMI/ Nonmaskable interrupt input

16 24 23 I SBWTDIO Spy-Bi-Wire test data input/output during programming and test

I/O DESCRIPTION

General-purpose digital I/O pin

(1)

JTAG test data output terminal or test data input during programming and

(2)

test General-purpose digital I/O pin

General-purpose digital I/O pin

Input terminal of crystal oscillator

Output terminal of crystal oscillator

(3)

General-purpose digital I/O pin

General-purpose digital I/O

Reset

(2) TDO or TDI is selected by JTAG instruction. (3) If XOUT/P2.7 is used as an input, excess current flows until P2SEL.7 is cleared. This is due to the oscillator output driver connection to

this pad after reset.

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Table 4-1. Terminal Functions (continued)

TERMINAL

NO.

NAME

TEST/ SBWTCK Spy-Bi-Wire test clock input during programming and test

AVCC NA NA 29 NA Analog supply voltage DVCC 1 1 30 NA Digital supply voltage DVSS 20 28 27, 28 NA Ground reference NC NA NA 8, 32 NA Not connected QFN Pad NA NA Pad NA QFN package pad connection to VSS recommended.

PW20,

N20

17 25 24 I

PW28 RHB32

I/O DESCRIPTION

Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST.

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5 Specifications

MSP430G2533,MSP430G2433,MSP430G2333,MSP430G2233

MSP430G2403, MSP430G2303, MSP430G2203

SLAS734G –APRIL 2011–REVISED APRIL 2016

5.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage applied at VCCto V Voltage applied to any pin

(2)

–0.3 4.1 V –0.3 VCC+ 0.3 V

Diode current at any device pin ±2 mA

Storage temperature, T

(3)

stg

Unprogrammed device –55 150 Programmed device –55 150

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT

Electrostatic discharge

(ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

(1)

(2)

±1000

±250

5.3 Recommended Operating Conditions

Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)

MIN NOM MAX UNIT

SYSTEM

Supply voltage

Supply voltage 0 V Operating free-air temperature –40 85 °C

Processor frequency (maximum MCLK frequency using the USART module)

(1)(2)

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phases of MCLK must not exceed the pulse duration of the

specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

During program execution 1.8 3.6 During flash programming or erase 2.2 3.6

VCC= 1.8 V, Duty cycle = 50% ±10%

VCC= 2.7 V, Duty cycle = 50% ±10%

VCC= 3.3 V, Duty cycle = 50% ±10%

DC 6

DC 12

DC 16

MHz

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Supply voltage range, during flash memory programming

Supply voltage range, during program execution

Legend:

16 MHz

System Frequency - MHz

12 MHz

6 MHz

1.8 V Supply Voltage - V

3.3 V

2.7 V

2.2 V

3.6 V

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Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V

of 2.2 V.

Figure 5-1. Safe Operating Area

5.4 Active Mode Supply Current Into VCCExcluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

AM,1MHz

PARAMETER TEST CONDITIONS V

= f

Active mode (AM) current at 1 MHz

MCLK

= 0 Hz,

= f

DCO

ACLK

Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ,

SMCLK

= 1 MHz,

2.2 V 230

3 V 330 420

CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

MIN TYP MAX UNIT

(1)(2)

µA

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0.0

1.0

2.0

3.0

4.0

5.0

1.5 2.0 2.5 3.0 3.5 4.0

VCC− Supply Voltage − V

Active Mode Current − mA

DCO

= 1 MHz

DCO

= 8 MHz

DCO

= 12 MHz

DCO

= 16 MHz

0.0

1.0

2.0

3.0

4.0

0.0 4.0 8.0 12.0 16.0

DCO

− DCO Frequency − MHz

Active Mode Current − mA

TA= 25 °C

TA= 85 °C

VCC= 2.2 V

VCC= 3 V

TA= 25 °C

TA= 85 °C

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5.5 Typical Characteristics, Active Mode Supply Current (Into VCC)

Figure 5-2. Active Mode Current vs VCC, TA= 25°C Figure 5-3. Active Mode Current vs DCO Frequency

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5.6 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LPM0,1MHz

PARAMETER TEST CONDITIONS T

= 0 MHz,

MCLK

= f

= 1 MHz,

DCO

= 32768 Hz,

Low-power mode 0 (LPM0) current

(3)

SMCLK

ACLK

BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ,

25°C 2.2 V 56 µA

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0

LPM2

Low-power mode 2 (LPM2) current

(4)

= f

MCLK

= 1 MHz,

DCO

= 32768 Hz,

ACLK

BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ,

SMCLK

= 0 MHz,

25°C 2.2 V 22 µA

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0

= f

LPM3,LFXT1

Low-power mode 3 (LPM3) current

(4)

DCO

ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

= f

MCLK

= 32768 Hz,

SMCLK

= 0 MHz,

25°C 2.2 V 0.7 1.5 µA OSCOFF = 0 f

= f

LPM3,VLO

Low-power mode 3 current, (LPM3)

(4)

DCO

ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1,

= f

MCLK

from internal LF oscillator (VLO),

SMCLK

= 0 MHz,

25°C 2.2 V 0.5 0.7 µA OSCOFF = 0 f

= f

LPM4

Low-power mode 4 (LPM4) current

(5)

MCLK

= 0 Hz,

= f

DCO

ACLK

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1

SMCLK

= 0 MHz,

25°C

85°C 0.8 1.7

load capacitance is chosen to closely match the required 9 pF. (3) Current for brownout and WDT clocked by SMCLK included. (4) Current for brownout and WDT clocked by ACLK included. (5) Current for brownout included.

2.2 V

(1) (2)

MIN TYP MAX UNIT

0.1 0.5 µA

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0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

-40

I – Low-Power Mode Current – µA

LPM3

V = 3.6 V

T – Temperature – °C

VCC= 1.8 V

VCC= 3 V

VCC= 2.2 V

-20

40 60 80

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

-40

I – Low-Power Mode Current – µA

LPM4

V = 3.6 V

T – Temperature – °C

VCC= 1.8 V

VCC= 3 V

VCC= 2.2 V

-20

40 60 80

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5.7 Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Figure 5-4. LPM3 Current vs Temperature

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Figure 5-5. LPM4 Current vs Temperature

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5.8 Thermal Resistance Characteristics

PARAMETER VALUE

VQFN (RHB-32) 32.1

Rθ

Junction-to-ambient thermal resistance, still air

(2)

TSSOP (PW-28) 72.2 TSSOP (PW-20) 86.5 PDIP (N-20) 49.3 VQFN (RHB-32) 22.3

Rθ

JC(TOP)

Junction-to-case (top) thermal resistance

(3)

TSSOP (PW-28) 18.3 TSSOP (PW-20) 20.8 PDIP (N-20) 41 VQFN (RHB-32) 1.4

Rθ

JC(BOTTOM)

Junction-to-case (bottom) thermal resistance

TSSOP (PW-28) N/A TSSOP (PW-20) N/A PDIP (N-20) N/A VQFN (RHB-32) 6.1

Junction-to-board thermal resistance

(4)

TSSOP (PW-28) 30.4 TSSOP (PW-20) 39 PDIP (N-20) 30.2 VQFN (RHB-32) 0.3

Junction-to-package-top characterization parameter

TSSOP (PW-28) 0.7 TSSOP (PW-20) 0.8 PDIP (N-20) 18.1 VQFN (RHB-32) 6.1

Junction-to-board characterization parameter

TSSOP (PW-28) 29.9 TSSOP (PW-20) 38.1 PDIP (N-20) 30.1

(1) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(1)

UNIT

°C/W

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5.9 Schmitt-Trigger Inputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Positive-going input threshold voltage

IT+

Negative-going input threshold voltage

IT–

Input voltage hysteresis (V

hys

Pullup or pulldown resistor

Pull

Input capacitance VIN= VSSor V

IT+

– V

) 3 V 0.3 1 V

IT–

For pullup: VIN= V For pulldown: VIN= V

3 V 1.35 2.25

3 V 0.75 1.65

3 V 20 35 50 kΩ

MIN TYP MAX UNIT

0.45 V

0.25 V

0.75 V

0.55 V

5 pF

5.10 Leakage Current, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

lkg(Px.y)

PARAMETER TEST CONDITIONS V

High-impedance leakage current See

(1) (2)

3 V ±50 nA

(1) The leakage current is measured with VSSor VCCapplied to the corresponding pins, unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

MIN MAX UNIT

5.11 Outputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

V V

High-level output voltage I

Low-level output voltage I

(1) The maximum total current, I

specified.

(OHmax)

and I

= –6 mA

(OHmax)

= 6 mA

(OLmax)

, for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

(OLmax)

(1)

3 V VCC– 0.3 V 3 V VSS+ 0.3 V

MIN TYP MAX UNIT

5.12 Output Frequency, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Px.y

Port_CLK

PARAMETER TEST CONDITIONS V

Port output frequency (with load) Px.y, CL= 20 pF, RL= 1 kΩ Clock output frequency Px.y, CL= 20 pF

(2)

(1) (2)

3 V 12 MHz 3 V 16 MHz

(1) A resistive divider with two 50-kΩ resistors between VCCand VSSis used as load. The output is connected to the center tap of the

divider.

(2) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.

MIN TYP MAX UNIT

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VOH− High-Level Output Voltage − V

−25

−20

−15

−10

−5

0 0.5 1 1.5 2 2.5

VCC= 2.2 V P1.7

TA= 25°C

TA= 85°C

I − Typical High-Level Output Current − mA

VOH− High-Level Output Voltage − V

−50

−40

−30

−20

−10

0 0.5 1 1.5 2 2.5 3 3.5

VCC= 3 V P1.7

TA= 25°C

TA= 85°C

I − Typical High-Level Output Current − mA

VOL− Low-Level Output Voltage − V

0 0.5 1 1.5 2 2.5

VCC= 2.2 V P1.7

TA= 25°C

TA= 85°C

I − Typical Low-Level Output Current − mA

VOL− Low-Level Output Voltage − V

0 0.5 1 1.5 2 2.5 3 3.5

VCC= 3 V P1.7

TA= 25°C

TA= 85°C

I − Typical Low-Level Output Current − mA

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5.13 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

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Figure 5-6. Typical Low-Level Output Current vs Low-Level

Figure 5-8. Typical High-Level Output Current vs High-Level

Output Voltage

Figure 5-7. Typical Low-Level Output Current vs Low-Level

Figure 5-9. Typical High-Level Output Current vs High-Level

Output Voltage

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C − External Capacitance − pF

LOAD

0.00

0.15

0.30

0.45

0.60

0.75

0.90

1.05

1.20

1.35

1.50

10 50 100

P1.y

P2.0 to P2.5

P2.6, P2.7

V = 3.0 V

f − Typical Oscillation Frequency − MHz

osc

C − External Capacitance − pF

LOAD

0.00

0.15

0.30

0.45

0.60

0.75

0.90

1.05

1.20

1.35

1.50

10 50 100

P1.y

P2.0 to P2.5

P2.6, P2.7

V = 2.2 V

f − Typical Oscillation Frequency − MHz

osc

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5.14 Pin-Oscillator Frequency – Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Port output oscillation frequency

P1.x

Port output oscillation frequency

P2.x

Port output oscillation frequency

P2.6/7

Port output oscillation frequency

P3.x

P1.y, CL= 10 pF, RL= 100 kΩ P1.y, CL= 20 pF, RL= 100 kΩ P2.0 to P2.5, CL= 10 pF, RL= 100 kΩ P2.0 to P2.5, CL= 20 pF, RL= 100 kΩ P2.6 and P2.7, CL= 20 pF, RL= 100

(1)(2)

kΩ P3.y, CL= 10 pF, RL= 100 kΩ P3.y, CL= 20 pF, RL= 100 kΩ

(1)(2) (1)(2)

3 V

3 V 700 kHz

3 V

(1) A resistive divider with two 50-kΩ resistors between VCCand VSSis used as load. The output is connected to the center tap of the

divider.

(2) The output voltage reaches at least 10% and 90% VCCat the specified toggle frequency.

MIN TYP MAX UNIT

1400

900 1800 1000

1800 1000

5.15 Typical Characteristics – Pin-Oscillator Frequency

kHz

Figure 5-10. Typical Oscillating Frequency vs Load Capacitance

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One output active at a time.

Figure 5-11. Typical Oscillating Frequency vs Load Capacitance

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One output active at a time.

CC(drop)

3 V

0.5

1.5

0.001 1 1000

Typical Conditions

1 ns 1 ns

tpw− Pulse Width − µs

CC(drop)

− V

tpw− Pulse Width − µs

VCC= 3 V

d(BOR)

(B_IT−)

hys(B_IT−)

CC(s tar t)

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5.16 POR, BOR

(1)(2)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

CC(start)

(B_IT–)

hys(B_IT–)

d(BOR)

(reset)

See Figure 5-12 dVCC/dt ≤ 3 V/s 0.7 V See Figure 5-12 through Figure 5-14 dVCC/dt ≤ 3 V/s 1.35 V See Figure 5-12 dVCC/dt ≤ 3 V/s 140 mV See Figure 5-12 2000 µs Pulse duration needed at RST/NMI pin to accepted

reset internally

(1) The current consumption of the brownout module is already included in the ICCcurrent consumption data. The voltage level V

hys(B_IT–)

(2) During power up, the CPU begins code execution following a period of t

must not be changed until VCC≥ V

is ≤ 1.8 V.

CC(min)

, where V

is the minimum supply voltage for the desired operating frequency.

CC(min)

TEST

CONDITIONS

d(BOR)

MIN TYP MAX UNIT

(B_IT--)

2.2 V 2 µs

after VCC= V

(B_IT–)

+ V

. The default DCO settings

hys(B_IT–)

(B_IT–)

Figure 5-12. POR and BOR vs Supply Voltage

Figure 5-13. V

CC(drop)

Level With a Square Voltage Drop to Generate a POR or BOR Signal

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0.5

1.5

CC(drop)

tpw− Pulse Width − µs

CC(drop)

− V

3 V

0.001 1 1000

tpw− Pulse Width − µs

tf= t

Typical Conditions

VCC= 3 V

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Figure 5-14. V

CC(drop)

Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

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DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

average

DCO(RSEL,DCO) DCO(RSEL,DCO+1)

32 × f × f

f =

MOD × f + (32 – MOD) × f

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5.17 Main DCO Characteristics

• All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15.

• DCO control bits DCOx have a step size as defined by parameter S

• Modulation control bits MODx select how often f f

DCO(RSEL,DCO)

is used for the remaining cycles. The frequency is an average equal to:

DCO(RSEL,DCO+1)

DCO

is used within the period of 32 DCOCLK cycles. The frequency

5.18 DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

RSELx < 14 1.8 3.6

Supply voltage

RSELx = 15 3 3.6

DCO(0,0)

DCO(0,3)

DCO(1,3)

DCO(2,3)

DCO(3,3)

DCO(4,3)

DCO(5,3)

DCO(6,3)

DCO(7,3)

DCO(8,3)

DCO(9,3)

DCO(10,3)

DCO(11,3)

DCO(12,3)

DCO(13,3)

DCO(14,3)

DCO(15,3)

DCO(15,7)

RSEL

DCO

DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3 V 0.06 0.14 MHz DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3 V 0.07 0.17 MHz DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3 V 0.15 MHz DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3 V 0.21 MHz DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3 V 0.30 MHz DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3 V 0.41 MHz DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3 V 0.58 MHz DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3 V 0.54 1.06 MHz DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3 V 0.80 1.50 MHz DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3 V 1.6 MHz DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3 V 2.3 MHz DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3 V 3.4 MHz DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3 V 4.25 MHz DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3 V 4.30 7.30 MHz DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3 V 6.00 9.60 MHz DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3 V 8.60 13.9 MHz DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 12.0 18.5 MHz DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 16.0 26.0 MHz Frequency step between

range RSEL and RSEL+1 Frequency step between

tap DCO and DCO+1

= f

RSEL

DCO(RSEL+1,DCO)/fDCO(RSEL,DCO)

= f

DCO

DCO(RSEL,DCO+1)/fDCO(RSEL,DCO)

3 V 1.35 ratio

3 V 1.08 ratio

Duty cycle Measured at SMCLK output 3 V 50%

MIN TYP MAX UNIT

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VRSELx = 14 2.2 3.6

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5.19 Calibrated DCO Frequencies, Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS T

1-MHz tolerance over temperature

(1)

BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V

0°C to 85°C 3 V –3% ±0.5% +3%

BCSCTL1 = CALBC1_1MHZ,

1-MHz tolerance over V

DCOCTL = CALDCO_1MHZ, calibrated at 30°C and 3 V

30°C 1.8 V to 3.6 V –3% ±2% +3%

BCSCTL1 = CALBC1_1MHZ,

1-MHz tolerance overall

DCOCTL = CALDCO_1MHZ,

–40°C to 85°C 1.8 V to 3.6 V –6% ±3% +6%

calibrated at 30°C and 3 V

8-MHz tolerance over temperature

(1)

BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V

0°C to 85°C 3 V –3% ±0.5% +3%

BCSCTL1 = CALBC1_8MHZ,

8-MHz tolerance over V

DCOCTL = CALDCO_8MHZ, calibrated at 30°C and 3 V

30°C 2.2 V to 3.6 V –3% ±2% +3%

BCSCTL1 = CALBC1_8MHZ,

8-MHz tolerance overall

DCOCTL = CALDCO_8MHZ,

–40°C to 85°C 2.2 V to 3.6 V –6% ±3% +6%

calibrated at 30°C and 3 V

12-MHz tolerance over temperature

(1)

BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3 V

0°C to 85°C 3 V –3% ±0.5% +3%

BCSCTL1 = CALBC1_12MHZ,

12-MHz tolerance over V

DCOCTL = CALDCO_12MHZ, calibrated at 30°C and 3 V

30°C 2.7 V to 3.6 V –3% ±2% +3%

BCSCTL1 = CALBC1_12MHZ,

12-MHz tolerance overall

DCOCTL = CALDCO_12MHZ,

–40°C to 85°C 2.7 V to 3.6 V –6% ±3% +6%

calibrated at 30°C and 3 V

16-MHz tolerance over temperature

(1)

BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V

0°C to 85°C 3 V –3% ±0.5% +3%

BCSCTL1 = CALBC1_16MHZ,

16-MHz tolerance over V

DCOCTL = CALDCO_16MHZ, calibrated at 30°C and 3 V

30°C 3.3 V to 3.6 V –3% ±2% +3%

BCSCTL1 = CALBC1_16MHZ,

16-MHz tolerance overall

DCOCTL = CALDCO_16MHZ,

–40°C to 85°C 3.3 V to 3.6 V –6% ±3% +6%

calibrated at 30°C and 3 V

(1) This is the frequency change from the measured frequency at 30°C over temperature.

MIN TYP MAX UNIT

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DCO Frequency − MHz

0.10

1.00

10.00

0.10 1.00 10.00

DCO Wake Time − µs

RSELx = 0...11

RSELx = 12...15

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5.20 Wake-up Times From Lower-Power Modes (LPM3, LPM4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

DCO,LPM3/4

CPU,LPM3/4

PARAMETER TEST CONDITIONS V

DCO clock wake-up time from LPM3 or

(1)

LPM4 CPU wake-up time from LPM3 or

(2)

LPM4

BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz

3 V 1.5 µs

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt) to the first clock

edge observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

MIN TYP MAX UNIT

1/f

MCLK

Clock,LPM3/4

5.21 Typical Characteristics, DCO Clock Wake-up Time From LPM3 or LPM4

Figure 5-15. DCO Wake-up Time From LPM3 vs DCO Frequency

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5.22 Crystal Oscillator, XT1, Low-Frequency Mode

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

LFXT1,LF

PARAMETER TEST CONDITIONS V

LFXT1 oscillator crystal frequency, LF mode 0, 1

XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz

LFXT1 oscillator logic level

LFXT1,LF,logic

square-wave input frequency, LF mode

XTS = 0, XCAPx = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz

XTS = 0, LFXT1Sx = 0,

Oscillation allowance for LF crystals

f XTS = 0, LFXT1Sx = 0,

LFXT1,LF

= 32768 Hz, C

L,eff

= 6 pF

= 12 pF

XTS = 0, XCAPx = 0 1

L,eff

Integrated effective load capacitance, LF mode

(2)

XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 XTS = 0, Measured at P2.0/ACLK,

LFXT1,LF

= 32768 Hz

XTS = 0, XCAPx = 0, LFXT1Sx = 3

2.2 V 30% 50% 70%

(4)

2.2 V 10 10000 Hz

Fault,LF

Duty cycle, LF mode Oscillator fault frequency,

LF mode

(3)

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

• Keep the trace between the device and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.

• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Because the PCB adds additional capacitance, verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal.

(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(4) Measured with logic-level input frequency but also applies to operation with crystals.

MIN TYP MAX UNIT

500

200

kΩ

5.23 Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER T

VLO

VLO/dT

VLO

VLO frequency –40°C to 85°C 3 V 4 12 20 kHz VLO frequency temperature drift –40°C to 85°C 3 V 0.5 %/°C

/dVCCVLO frequency supply voltage drift 25°C 1.8 V to 3.6 V 4 %/V

5.24 Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

TA,cap

Timer_A input clock frequency SMCLK, duty cycle = 50% ±10% f Timer_A capture timing TA0, TA1 3 V 20 ns

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MIN TYP MAX UNIT

SYSTEM

MHz

SU,MI

HD,MI

UCLK

SOMI

SIMO

VALID,MO

CKPL = 0

CKPL = 1

1/f

UCxCLK

HD,MO

LO/HI

SU,MI

HD,MI

UCLK

SOMI

SIMO

VALID,MO

HD,MO

CKPL = 0

CKPL = 1

LO/HI

1/f

UCxCLK

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5.25 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

USCI

max,BITCLK

USCI input clock frequency SMCLK, duty cycle = 50% ±10% f Maximum BITCLK clock frequency

(equals baud rate in MBaud) UART receive deglitch time

(1)

(2)

3 V 2 MHz 3 V 50 100 600 ns

(1) The DCO wake-up time must be considered in LPM3 and LPM4 for baud rates above 1 MHz. (2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

MIN TYP MAX UNIT

SYSTEM

MHz

5.26 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16 and Figure 5-17)

USCI

SU,MI

HD,MI

VALID,MO

PARAMETER TEST CONDITIONS V

USCI input clock frequency SMCLK, duty cycle = 50% ±10% f SOMI input data setup time 3 V 75 ns SOMI input data hold time 3 V 0 ns SIMO output data valid time UCLK edge to SIMO valid, CL= 20 pF 3 V 20 ns

MIN MAX UNIT

SYSTEM

MHz

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Figure 5-16. SPI Master Mode, CKPH = 0

Figure 5-17. SPI Master Mode, CKPH = 1

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