Texas Instruments MSP430FG47x User Manual

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

D Low Supply-Voltage Range: 1.8 V to 3.6 V
D Ultra-Low Power Consumption:

Active Mode: 262 Aat1MHz,2.2V
Standby Mode: 1.1 A
Off Mode (RAM Retention): 0.1 A

D Five Power-Saving Modes
D Wake-Up From Standby Mode in

Less Than 6 s

D 16-Bit RISC Architecture,

125-ns Instruction Cycle Time

D 16-Bit Sigma-Delta Analog-to-Digital (A/D)

Converter With Internal Reference and Five
Differential Analog Inputs

D Dual 12-Bit Digital-to-Analog (D/A)

Converter

D Dual Configurable Operational Amplifiers
D 16-Bit Timer_A With Three

Capture/Compare Registers

D 16-Bit Timer_B With Three

Capture/Compare-With-Shadow Registers

D Two Universal Serial Communication

Interfaces (USCI)
USCI_A0

-- Enhanced UART Supporting
Auto-Baudrate Detection

-- IrDA Encoder and Decoder

-- Synchronous SPI

USCI_B0

2

C

-- I

-- Synchronous SPI

D Integrated LCD Driver With Contrast

Control for Up to 128 Segments

D Brownout Detector
D Basic Timer With Real-Time Clock Feature
D Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D On-Chip Comparator
D Serial Onboard Programming,

No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse

D Bootstrap Loader
D On-Chip Emulation Module
D MSP430FG47x Family Members Include

MSP430FG477: 32KB+256B Flash Memory

2KB RAM

MSP430FG478: 48KB+256B Flash Memory

2KB RAM

MSP430FG479: 60KB+256B Flash Memory

2KB RAM

D Available in 113-Ball BGA (ZQW) and

80-Pin QFP (PN) Packages (see Available
Options)

D For Complete Module Descriptions, See the

MSP430x4xx Family User’s Guide,
Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes, is optimized to achieve extended battery life in portable measurement applications. The device features
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 6 s.

The MSP430FG47x is a microcontroller configuration with two 16-bit timers, a basic timer with a real-time clock,
a high performance 16-bit sigma-delta A/D converter, dual 12-bit D/A converters, two configurable operational
amplifiers, two universal serial communication interface, 48 I/O pins, and a liquid crystal display driver.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote
controls, thermostats, digital timers, hand-held meters, etc.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  2011, Texas Instruments Incorporated

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

1

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

AVAILABLE OPTIONS

T

A

-- 4 0 Cto85C

†

For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.

‡

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PLASTIC 113-BALL BGA (ZQW) PLASTIC 80-PIN QFP (PN)

MSP430FG477IZQW
MSP430FG478IZQW
MSP430FG479IZQW

PACKAGED DEVICES

DEVELOPMENT TOOL SUPPORT

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging
and programming through easy to use development tools. Recommended hardware options include the
following:

D Debugging and Programming Interface

-- MSP--FET430UIF (USB)

-- MSP--FET430PIF (Parallel Port)

D Debugging and Programming Interface with Target Board

†

‡

MSP430FG477IPN
MSP430FG478IPN
MSP430FG479IPN

-- MSP--FET430U80 (PN package)

D Production Programmer

-- MSP--GANG430

2

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

pin designation, MSP430FG47xIZQW

A1

A2

A3 A4 A5 A6 A7 A8 A9 A10

B1

B2

B3 B4 B5 B6 B7 B8 B9 B10

C1

C2

C3

D1

D2

E1

E2

F1

F2

G1

G2

MIXED SIGNAL MICROCONTROLLER

D4 D5 D6 D7 D8 D9

E5

E4

F4

F5

G4

G5

E7

E6

E8

F8

G8

MSP430FG47x

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

A11

A12

B11

B12

C11

C12

D11

D12

E11

F11

G11

E12

F12

G12

E9

F9

G9

H1

H2

J1

J2

K1

K2

L1

L2

L3 L4 L5 L6 L7 L8 L9 L10

M1

M2

H5 H6 H7 H8

H4

J4 J5 J6 J7 J8 J9

H9

H11

J11

K11

L11

M11

H12

J12

K12

L12

M12M3 M4 M5 M6 M7 M8 M9 M10

Note: For terminal assignments, see the MSP430xG47x Terminal Functions table.

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

3

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

pin designation, MSP430FG47xIPN

SS2

CC2DVSS1

DV

DV

P2.3/TB2

RST/NMI

TCK

P2.5/UCA0RXD/UCA0SOMI

P2.4/UCA0TXD/UCA0SIMO

TMS

TDI/TCLK

XT2OUT

XT2IN

TDO/TDI

P6.0/A0+/OA0O

P6.2/OA0I1 (SW0A)

P6.1/A0-/OA0FB

P6.3/A1+/OA1O

P6.4/A1-/OA1FB

P6.5/OA0I2 (SW0B)

P6.6/OA1I1 (SW1A)

DV

CC1

P2.2/TB1

P2.1/TB0/S0

P2.0/TA2/S1

P2.6/CAOUT/S2

P2.7/S3

GND

XIN

XOUT

GND

P4.7/S4

P4.6/S5

P4.5/S6

P4.4/S7

P4.3/S8

P4.2/S9

P4.1/S10

P4.0/S11

S12

S13

80 79

78 77 76 75 74 73 72 71 70 69 68 67 66 65

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

S16

S14

S15

S17

S18

S19

80-pin

IPN PACKAGE

(TOP VIEW)

S22

S23

P5.0/S20

P5.1/S21

S24

S25

64

63 62 61

60

V

REF

P6.7/OA1I2/SVSIN (SW1B)

59

P1.0/TA0/OA0RFB

58

P1.1/TA0/MCLK/OA1RFB

57

P1.2/TA1/A4-/OA0I3 (SW0C)

56

P1.3/TBOUTH/SVSOUT/A4+/OA1I3 (SW1C)

55

P1.4/TBCLK/SMCLK/A3-/OA1I0/DAC1

54

AV

53

52

51

50

49

48

47

46

45

44

43

42

41

37

38 39 40

COM0

P5.2/COM1

P5.3/COM2

P5.5/R23

P5.4/COM3

LCDCAP/R33

P5.7/R03

P5.6/LCDREF/R13

SS

AV

CC

P1.5/TACLK/ACLK/A3+

P1.6/CA0/A2-/OA0I0/DAC0

P1.7/CA1/A2+

P3.7/S31

P3.6/S30

P3.5/S29

P3.4/S28

P3.3/UCB0CLK/UCA0STE

P3.2/UCB0SOMI/UCB0SCL/S27

P3.1/UCB0SIMO/UCB0SDA/S26

P3.0/UCB0STE/UCA0CLK

4

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

functional block diagram

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

XIN/

XT2IN

Oscillators

FLL+

CPU

64kB

incl. 16

Registers

EEM

JTAG

Interface

XOUT/

XT2OUT

22

MCLK

ACLK

SMCLK

DVCC1/2 DVSS1/2

Flash

60kB
48kB
32kB

MAB

MDB

Brownout

Protection

SVS,
SVM

RST/NMI

RAM

2kB
2kB
2kB

LCD_A

128

Segments

1,2,3,4

Mux

AVCC AVSS P1.x/P2.x

SD16_A

with

Buffer

1 Channel

Sigma­Delta A/D
Converter

DAC12

12-Bit

2

Channels

Voltage

Out

Watchdog

WDT+

15-Bit

OA0, OA1

2 OpAmps

Timer_A3

3 CC

Registers

Comparator

_A

Timer_B3

3 CC

Registers,

Shadow

Reg

capability

Timer &

2x8

Ports

P1/P2

2x8 I/O

Interrupt

Basic

Real-

Time

Clock

P3.x/P4.x
P5.x/P6.x

Ports
P3/P4
P5/P6

4x8 I/O

USCI A0

UART/

LIN,

IrDA, SPI

USCI B0
SPI, I2C

4x8

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

5

MSP430FG47x

I/ODESCRIPTIO

N

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

TERMINAL

NO.

NAME

AV

CC

AV

SS

DV

CC1

DV

SS1

DV

CC2

DV

SS2

P1.0/TA0/
OA0RFB

P1.1/TA0/MCLK/
OA1RFB

P1.2/TA1/A4--/
OA0I3 (SW0C)

P1.3/TBOUTH/
SVSOUT/A4+/
OA1I3 (SW1C)

P1.4/TBCLK/
SMCLK/A3--/
OA1I0/DAC1

P1.5/TACLK/
ACLK/A3+

P1.6/CA0/A2--/
OA0I0/DAC0

P1.7/CA1/A2+ 49 G11 I/O

P2.0/TA2/S1 4

P2.1/TB0/S0 3 C1 I/O

80

113

PIN

PIN

52 F12 Analog supply voltage, positive terminal.

53 E12 Analog supply voltage, negative terminal.

1 A1 Digital supply voltage, positive terminal. Supplies all digital parts.

79 A3 Digital supply voltage, negative terminal. Supplies all digital parts.

80 A2 Digital supply voltage, positive terminal. Supplies all digital parts.

B2

78

B3

58 C11 I/O

57 C12 I/O

56 D11 I/O

55 D12 I/O

54 E11 I/O

51 F11 I/O

50 G12 I/O

C2
C3

Digital supply voltage, negative terminal. Supplies all digital parts.

General-purpose digital I/O pin
Timer_A, capture: CCI0A input, compare: Out0 output
Range switch to OA0 output
BSL transmit

General-purpose digital I/O pin
Timer_A, capture: CCI0B input, compare: Out0 output
MCLK signal output
Range switch to OA1 output
BSL receive

General-purpose digital I/O pin
Timer_A, capture: CCI1A input, compare: Out1 output
SD16 negative analog input A4
OA0, analog input I3

General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB2
SVS comparator output
SD16 positive analog input A4
OA1, analog input I3

General-purpose digital I/O pin/
Timer_B, clock signal TBCLK input
SMCLK signal output
SD16 negative analog input A3
OA1, analog input I0
DAC12.1 output

General-purpose digital I/O pin
Timer_A, clock signal TACLK input
ACLK signal output
SD16 positive analog input A3

General-purpose digital I/O pin
Comparator_A input 0
SD16 negative analog input A2
OA0, analog input I0
DAC12.0 output

General-purpose digital I/O pin
Comparator_A input 1
SD16 positive analog input A2

General-purpose digital I/O pin
Timer_A, capture: CCI2A/B input, compare: Out2 output

I/O

LCD segment output 1

General-purpose digital I/O pin
Timer_B, capture: CCI0A/B input, compare: Out0 output
LCD segment output 0

Terminal Functions

6

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TERMINAL

I/ODESCRIPTIO

N

NO.

NAME

P2.2/TB1 2 B1 I/O

P2.3/TB2 77 B4 I/O

P2.4/UCA0TXD/
UCA0SIMO

P2.5/UCA0RXD/
UCA0SOMI

P2.6/CAOUT/S2 5 D1 I/O

P2.7/S3 6 D2 I/O

P3.0/UCB0STE/
UCA0CLK

P3.1/UCB0SIMO/
UCB0SDA/S26

P3.2/UCB0SOMI/
UCB0SCL/S27

P3.3/UCB0CLK/
UCA0STE

P3.4/S28 45 J11 I/O

P3.5/S29 46 J12 I/O

P3.6/S30 47 H11 I/O

P3.7/S31 48 H12 I/O

P4.0/S11 18 K2 I/O

P4.1/S10 17 K1 I/O

P4.2/S9 16 J2 I/O

P4.3/S8 15 J1 I/O

P4.4/S7 14 H2 I/O

P4.5/S6 13 H1 I/O

P4.6/S5 12 G2 I/O

P4.7/S4 11 G1 I/O

80

113

PIN

PIN

76 A4 I/O

75 D4 I/O

41 M12 I/O

42 L12 I/O

43 K11 I/O

44 K12 I/O

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Terminal Functions (continued)

General-purpose digital I/O pin
Timer_B, capture: CCI1A/B input, compare: Out1 output

General-purpose digital I/O pin
Timer_B, capture: CCI2A/B input, compare: Out2 output

General-purpose digital I/O pin
USCIA transmit data output in UART mode, slave data in/master out in SPI mode

General-purpose digital I/O pin
USCI A0 receive data input in UART mode, slave data out/master in in SPI mode

General-purpose digital I/O pin
Comparator_A output
LCD segment output 2

General-purpose digital I/O pin
LCD segment output 3

General-purpose digital I/O pin
USCI B0 slave transmit enable/USCI A0 clock input/output

General-purpose digital I/O pin
USCI B0 slave in/master out in SPI mode, SDA I
LCD segment output 26

General-purpose digital I/O pin
USCI B0 slave out/master in in SPI mode, SCL I
LCD segment output 27

General-purpose digital I/O
USCI B0 clock i nput/output, USCI A0 slave transmit enable

General-purpose digital I/O pin
LCD segment output 28

General-purpose digital I/O pin
LCD segment output 29

General-purpose digital I/O pin
LCD segment output 30

General-purpose digital I/O pin
LCD segment output 31

General-purpose digital I/O pin
LCD segment output 11

General-purpose digital I/O pin
LCD segment output 10

General-purpose digital I/O pin
LCD segment output 9

General-purpose digital I/O pin
LCD segment output 8

General-purpose digital I/O pin
LCD segment output 7

General-purpose digital I/O pin
LCD segment output 6

General-purpose digital I/O pin
LCD segment output 5

General-purpose digital I/O pin
LCD segment output 4

2

CdatainI2C mode

2

C clock in I2C mode

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

7

MSP430FG47x

I/ODESCRIPTIO

N

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Terminal Functions (continued)

TERMINAL

NO.

NAME

COM0 33 L8 O Common output, COM0--3 are used for LCD backplanes

P5.0/S20 27 L5 I/O

P5.1/S21 28 M5 I/O

P5.2/COM1 34 M8 I/O

P5.3/COM2 35 L9 I/O

P5.4/COM3 36 M9 I/O

LCDCAP/R33 37 J9 I/O

P5.5/R23 38 M10 I/O

80

PIN

113
PIN

General-purpose digital I/O pin
LCD segment output 20

General-purpose digital I/O pin
LCD segment output 21

General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes

General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes

General-purpose digital I/O pin
common output, COM0--3 are used for LCD backplanes

Capacitor connection for LCD charge pump
input port of most positive analog LCD level (V4)

General-purpose digital I/O pin
input port of the second most positive analog LCD level (V3)

P5.6/LCDREF/
R13

P5.7/R03 40 M11 I/O

P6.0/A0+/OA0O 67 B8 I/O

P6.1/A0--/OA0FB 66 B9 I/O

P6.2/OA0I1
(SW0A)

P6.3/A1+/OA1O 64 D9 I/O

P6.4/A1--/OA1FB 63 A10 I/O

P6.5/OA0I2
(SW0B)

P6.6/OA1I1
(SW1A)

P6.7/OA1I2/
SVSIN (SW1B)

S12 19 L1 O LCD segment output 12

S13 20 M1 O LCD segment output 13

S14 21 M2 O LCD segment output 14

S15 22 M3 O LCD segment output 15

S16 23 L3 O LCD segment output 16

39 L10 I/O

65 A9 I/O

62 B10 I/O

61 A11 I/O

59 B12 I/O

General-purpose digital I/O pin
External LCD reference voltage input
input port of the third most positive analog LCD level (V3 or V2)

General-purpose digital I/O pin
input port of the fourth most positive analog LCD level (V1)

General-purpose digital I/O pin
SD16 positive analog input A0
OA0, output

General-purpose digital I/O pin
SD16 positive negative input A0
OA0, analog input feedback

General-purpose digital I/O pin
OA0, analog input I1

General-purpose digital I/O pin
SD16 positive analog input A1
OA1, output

General-purpose digital I/O pin
SD16 positive negative input A1
OA1, analog input feedback

General-purpose digital I/O pin
OA0, analog input I2

General-purpose digital I/O pin
OA1, analog input I1

General-purpose digital I/O pin
OA1, analog input I2
SVS input

8

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

I/ODESCRIPTIO

N

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Terminal Functions (continued)

TERMINAL

NO.

NAME

S17 24 L4 O LCD segment output 17

S18 25 M4 O LCD segment output 18

S19 26 J4 O LCD segment output 19

S22 29 L6 O LCD segment output 22

S23 30 M6 O LCD segment output 23

S24 31 L7 O LCD segment output 24

S25 32 M7 O LCD segment output 25

GND 7 E2 Ground. It is used to shield the oscillator. See Note 1.

XIN 8 E1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

XOUT 9 F1 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.

GND 10 F2 Ground. It is used to shield the oscillator. See Note NO TAG.

V

REF

RST/NMI 74 B5 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).

TCK 73 A5 I

TDI/TCLK 71 A6 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.

TDO/TDI 70 B7 I/O Test data output port. TDO/TDI data output or programming data input terminal.

TMS 72 B6 I Test mode select. TMS is used as an input port for device programming and test.

XT2OUT 68 A8 O Output terminal of crystal oscillator XT2

XT2IN 69 A7 I Input port for crystal oscillator XT2

Reserved NA B11,

NOTE 1: It is recommended to connect GND externally to DVss.

80

PIN

113
PIN

60 A12 O Input for an external reference voltage/internal reference voltage output

Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader
start.

BGA package unused balls. Connection to DVSS/AVSSrecommended.
D6, D7,
D8, E4,
E5, E6,
E7, E8,
E9, F4,
F5, F8,
F9, G4,
G5,G8,

G9, H4,

H5, H6,
H7, H8,
H9, J5,

J6, J7,
J8, L2,

L11

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9

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

short-form description

CPU

The MSP430 CPU has a 16--bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in
conjunction with seven addressing modes for
source operand and four addressing modes for
destination operand.

The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator, respectively. The
remaining registers are general-purpose
registers.

Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.

instruction set

The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats, and Table 2 lists the address
modes.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5

Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Register F

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)

Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)

Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)

Indirect

autoincrement

Immediate F MOV #X,TONI MOV #45,TONI #45 —> M(TONI)

NOTE: S = source D = destination

F

F MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 —> R11

M(R10) —> R11
R10 + 2—> R10

10

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MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request, and restore back to
the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

-- All clocks are active

D Low-power mode 0 (LPM0)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control remains active

D Low-power mode 1 (LPM1)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control is disabled

D Low-power mode 2 (LPM2)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator remains enabled

-- ACLK remains active

D Low-power mode 3 (LPM3)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- ACLK remains active

D Low-power mode 4 (LPM4)

-- CPU is disabled

-- ACLK is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- Crystal oscillator is stopped

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11

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU goes
into LPM4 immediately after power--up.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT

Power-Up

External Reset

Watchdog

PC Out--of--Range (see Note 4)

Flash Memory Access Violation

NOTES: 1. Multiple source flags

Flash Memory

NMI

Oscillator Fault

Timer_B3 TBCCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13

Timer_B3

Comparator_A CAIFG Maskable 0xFFF6 11

Watchdog Timer+ WDTIFG Maskable 0xFFF4 10

USCI_A0/USCI_B0 receive

USCI_B0 I2C status

USCI_A0/USCI_B0 transmit

USCI_B0 I2C receive/transmit

SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG

Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0xFFEC 6

Timer_A3

I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 4

DAC12 DAC12_0IFG, DAC12_1IFG Maskable 0xFFE6 3

I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1

Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowest

2. Interrupt flags are located in the module.

3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh).
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

4. Access and key violations, KEYV and ACCVIFG.

5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1, 2 and 4)

TBCCR1 CCIFG1 ... TBCCR3 CCIFG3,

TBIFG (see Notes 1 and 2)

UCA0RXIFG, UCB0RXIFG

UCA0TXIFG, UCB0TXIFG

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

PORIFG
RSTIFG
WDTIFG

KEYV

(see Note 1)

(see Notes 1 and 5)

(see Note 1 and 6)

(see Notes 1 and 2)

Reset 0xFFFE 15, highest

(Non)maskable
(Non)maskable
(Non)maskable

Maskable 0xFFF8 12

Maskable 0xFFF2 9

Maskable 0xFFF0 8

Maskable 0xFFEE 7

Maskable 0xFFEA 5

Maskable 0xFFE4 2

WORD

ADDRESS

0xFFFC 14

PRIORITY

12

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MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.

interrupt enable 1 and 2

Address76543210

00h

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog

timer is configured in interval timer mode.

OFIE Oscillator fault enable
NMIIE (Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable

Address76543210

01h

BTIE

rw--0 rw--0 rw--0 rw--0 rw--0

ACCVIE NMIIE OFIE WDTIE

rw--0 rw--0 rw--0 rw--0

UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

UCA0RXIE USCI_A0 receive interrupt enable
UCA0TXIE USCI_A0 transmit interrupt enable
UCB0RXIE USCI_B0 receive interrupt enable
UCB0TXIE USCI_B0 transmit interrupt enable
BTIE Basic timer interrupt enable

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13

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

interrupt flag register 1 and 2

Address76543210

02h

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V

power-up or a reset condition at RST/NMI pin in reset mode.

CC

OFIFG Flag set on oscillator fault.
RSTIFG External reset interrupt flag. Set on a reset condition at RST

on V

power-up.

CC

PORIFG Power-on interrupt flag. Set on V
NMIIFG Set via RST

Address76543210

03h

BTIFG

rw--0 rw--1 rw--0 rw--1 rw--0

/NMI pin.

NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw--0 rw--(0) rw--(1) rw-- 1 rw--(0)

/NMI pin in reset mode. Reset

power-up.

CC

UCB0

TXIFG

UCB0

RXIFG

UCA0
TXIFG

UCA0

RXIFG

UCA0RXIFG USCI_A0 receive interrupt flag
UCA0TXIFG USCI_A0 transmit interrupt flag
UCB0RXIFG USCI_B0 receive interrupt flag
UCB0TXIFG USCI_B0 transmit interrupt flag
BTIFG Basic Timer1 interrupt flag

Legend rw:

rw-0,1:
rw-(0,1):

Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device

14

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MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

memory organization

MSP430FG477 MSP430FG478 MSP430FG479

Memory
Main: interrupt vector
Main: code memory

Information memory Size

Boot memory Size

RAM Size 2KB

Peripherals 16-bit

bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access
to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the
features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap
Loader, literature number SLAA089.

Size
Flash
Flash

Flash

ROM

8-bit

8-bit SFR

32KB

0FFFFh to 0FFE0h

0FFFFh to 08000h

256 Byte

010FFh to 01000h

1KB

0FFFh to 0C00h

09FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

48KB
0FFFFh to 0FFE0h
0FFFFh to 04000h

256 Byte

010FFh to 01000h

1KB

0FFFh to 0C00h

2KB

09FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

60KB

0FFFFh to 0FFE0h

0FFFFh to 01100h

256 Byte

010FFh to 01000h

1KB

0FFFh to 0C00h

2KB

09FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

BSL FUNCTION PN PACKAGE PINS ZQW PACKAGE PINS

Data Transmit 58 - P1.0 C11 - P1.0

Data Receive 57 - P1.1 C12 - P1.1

flash memory (Flash)

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.

D Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

D Segment A might contain calibration data. After reset, segment A is protected against programming or

erasing. It can be unlocked, but care should be taken not to erase this segment if this calibration data is
required.

D Flash content integrity check with marginal read modes.

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15

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all
instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number
SLAU056.

oscillator and system clock

The clock system in the MSP430FG47x is supported by the FLL+ module, which includes support for a
32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency
crystal oscillator (XT1), plus a 8-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is
designed to meet the requirements of both low system cost and low power consumption. The FLL+ features
digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO
frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on
clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
D Main clock (MCLK), the system clock used by the CPU
D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules
D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user
selectable level and supports both supply voltage supervision (the device is automatically reset) and supply
voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V
have ramped to V
reaches V

CC(min)

CC(min)

. If desired, the SVS circuit can be used to determine when VCCreaches V

at that time. The user must ensure the default FLL+ settings are not changed until V

CC(min)

digital I/O

There are six 8-bit I/O ports implemented, ports P1 through P6.

D All individual I/O bits are independently programmable.
D Any combination of input, output, and interrupt conditions is possible.
D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
D Read/write access to port-control registers is supported by all instructions.

CC

.

may not

CC

16

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

DEVICEINPUT

MODULEINPUT

MODUL

E

A

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

watchdog timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed
in an application, the module can be configured as an interval timer and can generate interrupts at selected time
intervals.

Basic Timer1 and Real-Time Clock

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both
timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time
clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year
correction.

LCD_A driver with regulated charge pump

The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A
controller has dedicated data memory to hold segment drive information. Common and segment signals are
generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral.
The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump.
Furthermore, it is possible to control the level of the LCD v oltage and, thus, contrast in software.

Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.

TIMER_A3 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PN ZQW

P1.5 -- 51 F11 TAC L K TAC L K

P1.5 -- 51 F11 TAINCLK INCLK

P1.0 -- 58 C11 TA0 CCI0A

P1.1 -- 57 C12 TA0 CCI0B

P1.2 -- 56 D11 TA1 CCI1A

P2.0 -- 4 C2 TA 2 CCI2A

DEVICE INPUT MODULE INPUT MODULE

SIGNAL

ACLK ACLK

SMCLK SMCLK

DV

SS

DV

CC

CAOUT (internal) CCI1B

DV

SS

DV

CC

ACLK (internal) CCI2B

DV

SS

DV

CC

NAME

GND

V

CC

GND

V

CC

GND

V

CC

BLOCK

Timer N

CCR0 TA0

CCR1 TA1

CCR2 TA2

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PN ZQW

P1.0 -- 58 C11

P1.1 -- 57 C12

P1.2 -- 56 D11

P2.0 -- 4 C2

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17

MSP430FG47x

DEVICEINPUT

MODULEINPUT

MODUL

E

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.

TIMER_B3 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PN ZQW

P1.4 -- 54 E11 TBCLK TBCLK

P1.4 -- 54 E11 TBCLK

P2.1 -- 3 C1 TB0 CCI0A

P2.1 -- 3 C1 TB0 CCI0B

P2.2 -- 2 B1 TB1 CCI1A

P2.2 -- 2 B1 TB1 CCI1B

P2.3 -- 77 B4 TB2 CCI2A

NOTE 1: The inversion of TBCLK is done inside the module.

DEVICE INPUT MODULE INPUT MODULE

SIGNAL

ACLK ACLK

SMCLK SMCLK

(See Note 1)

V

SS

V

CC

V

SS

V

CC

ACLK (internal) CCI2B

V

SS

V

CC

NAME

INCLK

GND

V

CC

GND

V

CC

GND

V

CC

BLOCK

Timer NA

CCR0 TB0

CCR1 TB1

CCR2 TB2

MODULE
OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PN ZQW

P2.1 -- 3 C1

P2.2 -- 2 B1

P2.3 -- 77 B4

universal serial communication interfaces (USCIs) (USCI_A0, USCI_B0)

The USCI module is used for serial data communication. The USCI module supports synchronous
communication protocols such as SPI (3 pin or 4 pin), I2C, and asynchronous communication protocols such
as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 pin or 4 pin), UART, enhanced UART and IrDA.

USCI_B0 provides support for SPI (3 pin or 4 pin) and I2C.

Comparator_A

The primary function of the comparator_A module is to support precision slope analog-to-digital conversions,
battery-voltage supervision, and monitoring of external analog signals.

18

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MSP430FG47x

MODUL

E

MODUL

E

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

SD16_A

The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit
sigma-delta core and a reference generator. In addition to external analog inputs, an internal V
temperature sensor are also available.

DAC12

The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 may be used in 8-bit or 12-bit mode.
When multiple DAC12 modules are present, they may be grouped together for synchronous operation.

OA

The MSP430FG47x has two configurable low-current general-purpose operational amplifiers. Each OA input
and output terminal is software-selectable and offer a flexible choice of connections for various applications.
The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

OA0 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PN ZQW

P1.6 -- 50 G12 OA0I0 OAxI0

P6.2 -- 65 A9 OA0I1 OAxI1

P6.5 -- 62 B10 OA0I2 OAxIA

P1.2 -- 56 D11 OA0I3 OAxIB

P1.4 -- 54 E11 OA1I0 OAxI0

P6.6 -- 61 A11 OA1I1 OAxI1

P6.7 -- 59 B12 OA1I2 OAxIA

P1.3 -- 55 D12 OA1I3 OAxIB

DEVICE

INPUT

SIGNAL

MODULE MODULE

INPUT NAME

BLOCK

OA0 OA0OUT OA0O

OA1 OA1OUT OA1O

MODULE

OUTPUT

SIGNAL

CC

OUTPUT PIN NUMBER

PN ZQW

P6.0 -- 67 B8

P6.4 -- 64 A10

sense and

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19

MSP430FG47x

Timer_B3Capture/compareregister

2

TBCCR

2

0196h

Capture/compareregister

1

TBCCR

1

0194h

p/p

g

_

g

p

p

Timer_A3Capture/compareregister

2

TACCR

2

0176h

Capture/compareregister

1

TACCR

1

0174h

p/p

g

_

g

p

p

F

lash

l

2

FCTL2

012Ah

DAC12DAC12_1dat

a

DAC12_1DA

T

01CAh

DAC12_1contro

l

DAC12_1CT

L

01C2h

_

_

SD16_

A

Generalcontro

l

SD16CTL

0100h

Channel0control

SD16CCTL0

0102h

B

)

y

ppg

ppg

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

peripheral file map

PERIPHERALS WITH WORD ACCESS

Watchdog Watchdog timer control WDTCTL 0120h

Timer_B3 Capture/compare register 2 TBCCR2 0196h

Capture/compare register 1
Capture/compare register 0
Timer_B register TBR 0190h
Capture/compare control 2 TBCCTL2 0186h
Capture/compare control 1 TBCCTL1 0184h
Capture/compare control 0 TBCCTL0 0182h
Timer_B control TBCTL 0180h
Timer_B interrupt vector TBIV 011Eh

Timer_A3 Capture/compare register 2 TACCR2 0176h

Capture/compare register 1
Capture/compare register 0
Timer_A register TAR 0170h
Capture/compare control 2 TACCTL2 0166h
Capture/compare control 1 TACCTL1 0164h
Capture/compare control 0 TACCTL0 0162h
Timer_A control TACTL 0160h
Timer_A interrupt vector TAI V 012Eh

Flash Flash c ontrol 4

Flash control 3

contro

Flash control 1

DAC12 DAC12_1 data DAC12_1DAT 01CAh

DAC12_1 control
DAC12_0 data
DAC12_0 control

SD16_A General control SD16CTL 0100h
(see also:
Peripherals with

yteAccess

OA switches Switch control register 1 SWCTL_1 00CEh

OA switches Switch control register

OA1 Operational amplifier 1 control register 1 OA1CTL1 00C3h

OA0 Operational amplifier 0 control register 1 OA0CTL1 00C1h

SD16_A
(see also:
Peripherals with
Word Access)

Channel 0 control
Channel 0 conversion memory
Interrupt vector word register SD16IV 0110h

PERIPHERALS WITH BYTE ACCESS

Switch control register 1

Operational amplifier 1 control register 0 OA1CTL0 00C2h

Operational amplifier 0 control register 0 OA0CTL0 00C0h

Channel 0 input control
Analog enable

TBCCR1
TBCCR0

TACCR1
TACCR0

FCTL4
FCTL3

FCTL1

DAC12_1CTL
DAC12_0DAT
DAC12_0CTL 01C0h

SD16CCTL0
SD16MEM0

SWCTL
SWCTL1

SD16INCTL0
SD16AE

0194h
0192h

0174h
0172h

01BEh
012Ch

0128h

01C2h
01C8h

0102h
0112h

00CFh
00CEh

0B0h
0B7h

20

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peripheral file map (continued)

/

p

_

LCD_A LCD voltage control 1

USCI A0/B0

Comparator_A

Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 056h

FLL+ Clock FLL+ control 1 FLL_CTL1 054h

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

LCDAVCTL1
LCD voltage control 0
LCD voltage port control 1
LCD voltage port control 0
LCD memory 20
:
LCD memory 16
LCD memory 15
:
LCD memory 1
LCD control and mode

USCI A0 auto baud rate control UCA0ABCTL 0x005D

USCI A0 transmit buffer UCA0TXBUF 0x0067

USCI A0 receive buffer UCA0RXBUF 0x0066

USCI A0 status UCA0STAT 0x0065

USCI A0 modulation c ontrol UCA0MCTL 0x0064

USCI A0 baud rate control 1 UCA0BR1 0x0063

USCI A0 baud rate control 0 UCA0BR0 0x0062

USCI A0 control 1 UCA0CTL1 0x0061

USCI A0 control 0 UCA0CTL0 0x0060

USCI A0 IrDA receive control UCA0IRRCTL 0x005F

USCI A0 IrDA transmit control UCA0IRTCTL 0x005E

USCI B0 transmit buffer UCB0TXBUF 0x006F

USCI B0 receive buffer UCB0RXBUF 0x006E

USCI B0 status UCB0STAT 0x006D

USCI B0 I2C Interrupt enable UCB0CIE 0x006C

USCI B0 baud rate control 1 UCB0BR1 0x006B

USCI B0 baud rate control 0 UCB0BR0 0x006A

USCI B0 control 1 UCB0CTL1 0x0069

USCI B0 control 0 UCB0CTL0 0x0068

USCI B0 I2C slave address UCB0SA 0x011A

USCI B0 I2C own address UCB0OA 0x0118

Comparator_A port disable CAPD 05Bh

Comparator_A control2 CACTL2 05Ah

Comparator_A control1 CACTL1 059h

FLL+ control 0 FLL_CTL0 053h

System clock frequency control SCFQCTL 052h

System clock frequency integrator SCFI1 051h

System clock frequency integrator SCFI0 050h

LCDAVCTL0

LCDAPCTL1

LCDAPCTL0

LCDM20

:

LCDM16

LCDM15

:

LCDM1

LCDACTL

0AFh
0AEh
0ADh
0ACh
0A4h
:
0A0h
09Fh
:
091h
090h

MSP430FG47x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

21

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS

RTC
(Basic Timer1)

Port P6

Port P5

Port P4

Port P3

Port P2

Real-time clock year high byte
Real-time clock year low byte
Real-time clock month
Real-time clock day of month
Basic Timer1 counter
Basic Timer1 counter
Real-time counter 4
(Real-time clock day of week)
Real-time counter 3
(Real-time clock hour)
Real-time counter 2
(Real-time clock minute)
Real-time counter 1
(Real-time clock second)
Real-time clock control
Basic Timer1 control

Port P6 selection P6SEL 037h

Port P6 direction P6DIR 036h

Port P6 output P6OUT 035h

Port P6 input P6IN 034h

Port P5 selection P5SEL 033h

Port P5 direction P5DIR 032h

Port P5 output P5OUT 031h

Port P5 input P5IN 030h

Port P4 selection P4SEL 01Fh

Port P4 direction P4DIR 01Eh

Port P4 output P4OUT 01Dh

Port P4 input P4IN 01Ch

Port P3 selection P3SEL 01Bh

Port P3 direction P3DIR 01Ah

Port P3 output P3OUT 019h

Port P3 input P3IN 018h

Port P2 selection P2SEL 02Eh

Port P2 interrupt enable P2IE 02Dh

Port P2 interrupt-edge select P2IES 02Ch

Port P2 interrupt flag P2IFG 02Bh

Port P2 direction P2DIR 02Ah

Port P2 output P2OUT 029h

Port P2 input P2IN 028h

RTCYEARH
RTCYEARL
RTCMON
RTCDAY
BTCNT2
BTCNT1
RTCNT4
(RTCDOW)
RTCNT3
(RTCHOUR)
RTCNT2
(RTCMIN)
RTCNT1
(RTCSEC)
RTCCTL
BTCTL

04Fh
04Eh
04Dh
04Ch
047h
046h
045h

044h

043h

042h

041h
040h

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peripheral file map (continued)

S

l

f

t

i

SFR

int

tflag2IFG2003h

p

g

SFRinterruptenable2IE2001hS

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P1

pecia

unc

ons

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Port P1 selection 2 register
Port P1 selection

Port P1 interrupt enable P1IE 025h

Port P1 interrupt-edge select P1IES 024h

Port P1 interrupt flag P1IFG 023h

Port P1 direction P1DIR 022h

Port P1 output P1OUT 021h

Port P1 input P1IN 020h

errup
SFR interrupt flag 1 IFG1 002h
SFR interrupt enable 2 IE2 001h

FR interrupt enable 1 IE1 000h

P1SEL2
P1SEL

057h
026h

MSP430FG47x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

23

MSP430FG47x

(seeNote1

)

f

f

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

absolute maximum ratings over operating free-air temperature (see Note 1)

Voltage applied at VCCto V

SS

Voltage applied to any pin (see Note 2) --0.3 V to V

Diode current at any device terminal . 2mA......................................................

Storage temperature, T

: (unprogrammed device, see Note 3) --55C to 150C.......................

stg

(programmed device, see Note 3) --40Cto85C..........................

NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.

2. All voltages referenced to V
is applied to the TDI/TCLK pin when blowing the JTAG fuse.

3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage

SS

recommended operating conditions

MIN NOM MAX UNITS

Supply voltage during program execution,
V

(AVCC=DVCC=VCC)

CC

Supply voltage during flash memory programming,
V

(AVCC=DVCC=VCC)

CC

Supply voltage, VSS(AVSS=DVSS=VSS) 0 0 V

Operating free-air temperature range, T

LFXT1 crystal frequency, f
(see Note 1)

XT2 crystalfrequency,

Systemfrequency, MCLK,ACLK, SMCLK ,

NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

(LFXT1)

(XT2)

A

LF selected,
XTS_FLL = 0

XT1 selected,
XTS_FLL = 1

XT1 selected,
XTS_FLL = 1

(System)

Watch crystal 32.768 kHz

Ceramic resonator 0.45 6 MHz

Crystal 1 6 MHz

Ceramic resonator 0.45 8

Crystal 1 8

VCC=1.8V dc 4.15

VCC=2.5V dc 8

1.8 3.6 V

2.2 3.6 V

-- 4 0 85 C

--0.3 V to 4.1 V......................................................

+0.3V.......................................

CC

MHz

MHz

f

System

8 MHz

4.15 MHz

Figure 1. Frequency vs Supply Voltage, Typical Characteristics

24

(MHz)

Supply voltage range,
MSP430FG47x, during
program execution

1.8
Supply Voltage - V

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

2.2 2.5 3.6

Supply voltage range , MSP430FG47x,
during flash memory programming

MSP430FG47x

f=f

f

(MCLK

)

=

f

(SMCLK)

=1MHz

A

)

Lowpowermode(LPM0

)

A

f

A

Low-powermode(LPM3)

V

f

(MCLK

)f(SMCLK)

0MHz,

A

ALCD_Aenabled,LCDCPEN=0

:

(

,

LCD(ACLK)

/

)

V

Low-powermode(LPM3)

f

(MCLK

)f(SMCLK)

0MHz,

2.2

V

A

ALCD_Aenabled,LCDCPEN=0

:

(

,

LCD(ACLK)

/

)

3

V

V

f

f

A

f

0Hz,SCG

0=1(seeNote2)

V

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise
noted)

supply current into AVCC+DVCCexcluding external current

PARAMETER TEST CONDITIONS V

Active mode (see Note 1)

I

(AM)

f

(ACLK)

= 32,768 Hz

=1MHz,

XTS = 0, SELM = (0,1)

I

(LPM0)

Low-power mode(LPM0
(see Note 1)

Low-power mode (LPM2),

I

(LPM2)

(MCLK) =f(SMCLK) = 0 MHz,

f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2)

-

I

(LPM3)

f

(MCLK)=f(SMCLK)

f

= 32,768 Hz, SCG0 = 1

(ACLK)

Basic Timer1 enabled ,ACLK selected
LCD

enabled,LCDCPEN = 0:

(static mode , f

=0MHz,

LCD=f(ACLK)

(see Note 2 and Note 3)

-

I

(LPM3)

f

(MCLK)=f(SMCLK)

f

= 32,768 Hz, SCG0 = 1

(ACLK)

Basic Timer1 enabled ,ACLK selected
LCD

enabled,LCDCPEN = 0:

(4-mux mode, f

=0MHz,

LCD=f(ACLK)

(see Note 2 and Note 3)

Low-power mode (LPM4)

I

(LPM4)

(MCLK)
(ACLK)

=0MHz,

=

=

(SMCLK)

=

NOTES: 1. Timer_Aisclockedbyf

2. All inputs are tied to 0 V or to V

3. The LPM3 currents are characterized with a Micro Crystal CC4V--T1A (9pF) crystal and OSCCAPx = 01h.

,

/32)

/32)

=0MHz,

(DCOCLK)

CC

2.2 V 262 295

=--40Cto85C

T

A

3V 420 460

=--40Cto85C

T

A

2.2 V 32 62

3V 51 77

2.2 V 5 9

T

=--40Cto85C

A

3V 7 13

TA=--40C 1.0 1.8

TA=25C

T

A

=60C

2.2

TA=85C 2.3 4.0

=--40C 1.2 2.0

T

A

=25C

T

A

T

A

=60C

3

TA=85C 2.7 4.5

TA=--40C 1.0 3.0

T

=25C

A

2.2 V

TA=85C

=--40C 1.8 3.3

T

A

=25C

T

A

T

A

=85C

3V

TA=--40C 0.1 0.5

TA=25C

TA=60C

2.2

TA=85C 1.7 3.0

TA=--40C 0.1 0.8

TA=25C

TA=60C

3

TA=85C 1.5 3.5

= 1 MHz. All i nputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

. Outputs do not source or sink any current.

CC

MIN TYP MAX UNIT







1.0 1.8

1.1 2.0



1.2 2.0

1.4 2.2

1.1 3.2

3.5 6.0



2.0 4.0

4.2 7.5

0.1 0.5

0.7 1.1



0.1 0.8

0.8 1.2

Current consumption of active mode versus system frequency

I

(AM)=I(AM)

[1 MHz]  f

Current consumption of active mode versus supply voltage

I

(AM)=I(AM) [3 V]

+ 200 A/V  (VCC–2.2V)

(System)

[MHz]

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

25

MSP430FG47x
MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

typical characteristics -- LPM4 current

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

-- Low-Power Mode 4 Current -- A

0.4

LPM4

I

0.2

0.0

--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0

Vcc=3.6V

Vcc=3.0V

Vcc=2.2V

Vcc=1.8V

TA-- Temperature -- C

TA-- Temperature -- C

Figure 2. I

-- LPM4 Current vs Temperature

LPM4

26

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

V

V

V

PortP1,P2:P1.xtoP2.x,externaltriggersigna

l

_

A

_

A

y

f

Timer_Aclockfrequencyexternally

f

_

A

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)

Schmitt-trigger inputs -- Ports P1, P2, P3, P4, P5, and P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)

PARAMETER TEST CONDITIONS MIN MAX UNIT

V

IT+

V

IT--

V

hys

Positive-going input threshold voltage

Negative-going input threshold voltage

Input voltage hysteresis (V

IT+

-- V

IT--

)

inputs Px.y, TAx

PARAMETER TEST CONDITIONS V

t

(int)

t

(cap)

(TAext)

(TAint)

External interrupt timing

Timer

Timer

capture timing TA0, TA1, TA2

clockfrequencyexternall

applied to pin

Timer

,clockfrequency SMCLK orACLK signal selected

NOTES: 1. The external signal sets the interrupt flag every time the minimum t

shorter than t

(int)

.

Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag (see Note 1)

TACLK, INCLK: t

(H)=t(L)

(int)

leakage current -- Ports P1, P2, P3, P4, P5, and P6 (see Note 1)

PARAMETER TEST CONDITIONS MIN MAX UNIT

I

lkg(Px.y)

NOTES: 1. The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.

Leakage current Port Px V

2. The port pin must be selected as input.

(see Note 2) VCC=2.2V/3V 50 nA

(Px.y)

VCC=2.2V 1.1 1.55

V

=3V 1.5 1.98

CC

VCC=2.2V 0.4 0.9

V

=3V 0.9 1.3

CC

VCC=2.2V 0.3 1.1

VCC=3V 0.5 1

CC

2.2 V 62

3V 50

2.2 V 62

3V 50

2.2 V 8

3V 10

2.2 V 8

3V 10

MIN MAX UNIT

ns

ns

MHz

MHz

parameters are met. It may be set even with trigger signals

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

27

MSP430FG47x

V

V

,

P

1.1/TA0/MCL

K

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise
noted) (continued)

outputs -- Ports P1, P2, P3, P4, P5, and P6

PARAMETER TEST CONDITIONS MIN MAX UNIT

V

High-level output voltage

OH

V

Low-level output voltage

OL

NOTES: 1. The maximum total current, I

specified voltage drop.

2. The maximum total current, I
specified voltage drop.

output frequency

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

(Px.y)

f

(MCLK)

t

(Xdc)

(x=1,2,3,4,5,6,0 y  7)

P1.1/TA0/MCLK CL=20pF f

Duty cycle of output frequency

I

OH(max) =

I

OH(max) =

I

OH(max) =

I

OH(max) =

I

OL(max) =

I

OL(max) =

I

OL(max) =

I

OL(max) =

and I

OH(max)

and I

OH(max)

CL=20pF,
I

= 1.5 mA

L

P1.1/TA0/MCLK
C

=20pF,

L

V

CC

=2.2V/3V

-- 1 . 5 m A , V

-- 6 m A , V

-- 1 . 5 m A , V

-- 6 m A , V

1.5 mA, V

6mA, V

1.5 mA, V

6mA, V

for all outputs combined, should not exceed 12 mA to satisfy the maximum

OL(max),

for all outputs combined, should not exceed 48 mA to satisfy the maximum

OL(max),

V

f

,

f

2.2 V, SeeNote1 VCC--0.25 V

CC =

2.2 V, SeeNote2 VCC-- 0 . 6 V

CC =

3V, SeeNote1 VCC--0.25 V

CC =

3V, SeeNote2 VCC-- 0 . 6 V

CC =

2.2 V, SeeNote1 V

CC =

2.2 V, SeeNote2 V

CC =

3V, SeeNote1 V

CC =

3V, SeeNote2 V

CC =

2.2 V / 3 V DC f

CC =

(MCLK)=f(XT1)

(MCLK)=f(DCOCLK)

40% 60%

50%-­15 ns

SSVSS

SS

SSVSS

SS

50%

VSS+0.6

VSS+0.6

CC

CC

CC

CC

+0.25

+0.25

System

System

50%+

15 ns

MHz

MHz

28

POST OFFICE BOX 655303  DALLAS, TEXAS 75265