Texas Instruments MSP430FG47x User Manual

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MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

D Low Supply-Voltage Range: 1.8 V to 3.6 V D Ultra-Low Power Consumption:

Active Mode: 262 Aat1MHz,2.2V Standby Mode: 1.1 A Off Mode (RAM Retention): 0.1 A

D Five Power-Saving Modes D Wake-Up From Standby Mode in

Less Than 6 s

D 16-Bit RISC Architecture,

125-ns Instruction Cycle Time

D 16-Bit Sigma-Delta Analog-to-Digital (A/D)

Converter With Internal Reference and Five Differential Analog Inputs

D Dual 12-Bit Digital-to-Analog (D/A)

Converter

D Dual Configurable Operational Amplifiers D 16-Bit Timer_A With Three

Capture/Compare Registers

D 16-Bit Timer_B With Three

Capture/Compare-With-Shadow Registers

D Two Universal Serial Communication

Interfaces (USCI) USCI_A0

-- Enhanced UART Supporting Auto-Baudrate Detection

-- IrDA Encoder and Decoder

-- Synchronous SPI

USCI_B0

C

-- I

-- Synchronous SPI

D Integrated LCD Driver With Contrast

Control for Up to 128 Segments

D Brownout Detector D Basic Timer With Real-Time Clock Feature D Supply Voltage Supervisor/Monitor With

Programmable Level Detection

D On-Chip Comparator D Serial Onboard Programming,

No External Programming Voltage Needed Programmable Code Protection by Security Fuse

D Bootstrap Loader D On-Chip Emulation Module D MSP430FG47x Family Members Include

MSP430FG477: 32KB+256B Flash Memory

2KB RAM

MSP430FG478: 48KB+256B Flash Memory

2KB RAM

MSP430FG479: 60KB+256B Flash Memory

2KB RAM

D Available in 113-Ball BGA (ZQW) and

80-Pin QFP (PN) Packages (see Available Options)

D For Complete Module Descriptions, See the

MSP430x4xx Family User’s Guide, Literature Number SLAU056

description

The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 6 s.

The MSP430FG47x is a microcontroller configuration with two 16-bit timers, a basic timer with a real-time clock, a high performance 16-bit sigma-delta A/D converter, dual 12-bit D/A converters, two configurable operational amplifiers, two universal serial communication interface, 48 I/O pins, and a liquid crystal display driver.

Typical applications for this device include analog and digital sensor systems, digital motor control, remote controls, thermostats, digital timers, hand-held meters, etc.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. These devices have limited built-in ESD protection.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

AVAILABLE OPTIONS

-- 4 0 Cto85C

†

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

‡

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

PLASTIC 113-BALL BGA (ZQW) PLASTIC 80-PIN QFP (PN)

MSP430FG477IZQW MSP430FG478IZQW MSP430FG479IZQW

PACKAGED DEVICES

DEVELOPMENT TOOL SUPPORT

All MSP430 microcontrollers include an Embedded Emulation Module (EEM) allowing advanced debugging and programming through easy to use development tools. Recommended hardware options include the following:

D Debugging and Programming Interface

-- MSP--FET430UIF (USB)

-- MSP--FET430PIF (Parallel Port)

D Debugging and Programming Interface with Target Board

†

‡

MSP430FG477IPN MSP430FG478IPN MSP430FG479IPN

-- MSP--FET430U80 (PN package)

D Production Programmer

-- MSP--GANG430

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pin designation, MSP430FG47xIZQW

A3 A4 A5 A6 A7 A8 A9 A10

B3 B4 B5 B6 B7 B8 B9 B10

MIXED SIGNAL MICROCONTROLLER

D4 D5 D6 D7 D8 D9

MSP430FG47x

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

A11

A12

B11

B12

C11

C12

D11

D12

E11

F11

G11

E12

F12

G12

L3 L4 L5 L6 L7 L8 L9 L10

H5 H6 H7 H8

J4 J5 J6 J7 J8 J9

H11

J11

K11

L11

M11

H12

J12

K12

L12

M12M3 M4 M5 M6 M7 M8 M9 M10

Note: For terminal assignments, see the MSP430xG47x Terminal Functions table.

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MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

pin designation, MSP430FG47xIPN

SS2

CC2DVSS1

P2.3/TB2

RST/NMI

TCK

P2.5/UCA0RXD/UCA0SOMI

P2.4/UCA0TXD/UCA0SIMO

TMS

TDI/TCLK

XT2OUT

XT2IN

TDO/TDI

P6.0/A0+/OA0O

P6.2/OA0I1 (SW0A)

P6.1/A0-/OA0FB

P6.3/A1+/OA1O

P6.4/A1-/OA1FB

P6.5/OA0I2 (SW0B)

P6.6/OA1I1 (SW1A)

CC1

P2.2/TB1

P2.1/TB0/S0

P2.0/TA2/S1

P2.6/CAOUT/S2

P2.7/S3

GND

XIN

XOUT

GND

P4.7/S4

P4.6/S5

P4.5/S6

P4.4/S7

P4.3/S8

P4.2/S9

P4.1/S10

P4.0/S11

S12

S13

80 79

78 77 76 75 74 73 72 71 70 69 68 67 66 65

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

S16

S14

S15

S17

S18

S19

80-pin

IPN PACKAGE

(TOP VIEW)

S22

S23

P5.0/S20

P5.1/S21

S24

S25

63 62 61

REF

P6.7/OA1I2/SVSIN (SW1B)

P1.0/TA0/OA0RFB

P1.1/TA0/MCLK/OA1RFB

P1.2/TA1/A4-/OA0I3 (SW0C)

P1.3/TBOUTH/SVSOUT/A4+/OA1I3 (SW1C)

P1.4/TBCLK/SMCLK/A3-/OA1I0/DAC1

38 39 40

COM0

P5.2/COM1

P5.3/COM2

P5.5/R23

P5.4/COM3

LCDCAP/R33

P5.7/R03

P5.6/LCDREF/R13

P1.5/TACLK/ACLK/A3+

P1.6/CA0/A2-/OA0I0/DAC0

P1.7/CA1/A2+

P3.7/S31

P3.6/S30

P3.5/S29

P3.4/S28

P3.3/UCB0CLK/UCA0STE

P3.2/UCB0SOMI/UCB0SCL/S27

P3.1/UCB0SIMO/UCB0SDA/S26

P3.0/UCB0STE/UCA0CLK

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functional block diagram

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

XIN/

XT2IN

Oscillators

FLL+

CPU

64kB

incl. 16

Registers

EEM

JTAG

Interface

XOUT/

XT2OUT

MCLK

ACLK

SMCLK

DVCC1/2 DVSS1/2

Flash

60kB 48kB 32kB

MAB

MDB

Brownout

Protection

SVS, SVM

RST/NMI

RAM

2kB 2kB 2kB

LCD_A

128

Segments

1,2,3,4

Mux

AVCC AVSS P1.x/P2.x

SD16_A

with

Buffer

1 Channel

SigmaDelta A/D Converter

DAC12

12-Bit

Channels

Voltage

Out

Watchdog

WDT+

15-Bit

OA0, OA1

2 OpAmps

Timer_A3

3 CC

Registers

Comparator

Timer_B3

3 CC

Registers,

Shadow

Reg

capability

Timer &

2x8

Ports

P1/P2

2x8 I/O

Interrupt

Basic

Real-

Time

Clock

P3.x/P4.x P5.x/P6.x

Ports P3/P4 P5/P6

4x8 I/O

USCI A0

UART/

LIN,

IrDA, SPI

USCI B0 SPI, I2C

4x8

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MSP430FG47x

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

TERMINAL

NO.

NAME

CC1

SS1

CC2

SS2

P1.0/TA0/ OA0RFB

P1.1/TA0/MCLK/ OA1RFB

P1.2/TA1/A4--/ OA0I3 (SW0C)

P1.3/TBOUTH/ SVSOUT/A4+/ OA1I3 (SW1C)

P1.4/TBCLK/ SMCLK/A3--/ OA1I0/DAC1

P1.5/TACLK/ ACLK/A3+

P1.6/CA0/A2--/ OA0I0/DAC0

P1.7/CA1/A2+ 49 G11 I/O

P2.0/TA2/S1 4

P2.1/TB0/S0 3 C1 I/O

113

52 F12 Analog supply voltage, positive terminal.

53 E12 Analog supply voltage, negative terminal.

1 A1 Digital supply voltage, positive terminal. Supplies all digital parts.

79 A3 Digital supply voltage, negative terminal. Supplies all digital parts.

80 A2 Digital supply voltage, positive terminal. Supplies all digital parts.

58 C11 I/O

57 C12 I/O

56 D11 I/O

55 D12 I/O

54 E11 I/O

51 F11 I/O

50 G12 I/O

C2 C3

Digital supply voltage, negative terminal. Supplies all digital parts.

General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: Out0 output Range switch to OA0 output BSL transmit

General-purpose digital I/O pin Timer_A, capture: CCI0B input, compare: Out0 output MCLK signal output Range switch to OA1 output BSL receive

General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: Out1 output SD16 negative analog input A4 OA0, analog input I3

General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output switch all PWM digital output ports to high impedance -- Timer_B TB0 to TB2 SVS comparator output SD16 positive analog input A4 OA1, analog input I3

General-purpose digital I/O pin/ Timer_B, clock signal TBCLK input SMCLK signal output SD16 negative analog input A3 OA1, analog input I0 DAC12.1 output

General-purpose digital I/O pin Timer_A, clock signal TACLK input ACLK signal output SD16 positive analog input A3

General-purpose digital I/O pin Comparator_A input 0 SD16 negative analog input A2 OA0, analog input I0 DAC12.0 output

General-purpose digital I/O pin Comparator_A input 1 SD16 positive analog input A2

General-purpose digital I/O pin Timer_A, capture: CCI2A/B input, compare: Out2 output

I/O

LCD segment output 1

General-purpose digital I/O pin Timer_B, capture: CCI0A/B input, compare: Out0 output LCD segment output 0

Terminal Functions

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TERMINAL

I/ODESCRIPTIO

NO.

NAME

P2.2/TB1 2 B1 I/O

P2.3/TB2 77 B4 I/O

P2.4/UCA0TXD/ UCA0SIMO

P2.5/UCA0RXD/ UCA0SOMI

P2.6/CAOUT/S2 5 D1 I/O

P2.7/S3 6 D2 I/O

P3.0/UCB0STE/ UCA0CLK

P3.1/UCB0SIMO/ UCB0SDA/S26

P3.2/UCB0SOMI/ UCB0SCL/S27

P3.3/UCB0CLK/ UCA0STE

P3.4/S28 45 J11 I/O

P3.5/S29 46 J12 I/O

P3.6/S30 47 H11 I/O

P3.7/S31 48 H12 I/O

P4.0/S11 18 K2 I/O

P4.1/S10 17 K1 I/O

P4.2/S9 16 J2 I/O

P4.3/S8 15 J1 I/O

P4.4/S7 14 H2 I/O

P4.5/S6 13 H1 I/O

P4.6/S5 12 G2 I/O

P4.7/S4 11 G1 I/O

113

76 A4 I/O

75 D4 I/O

41 M12 I/O

42 L12 I/O

43 K11 I/O

44 K12 I/O

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Terminal Functions (continued)

General-purpose digital I/O pin Timer_B, capture: CCI1A/B input, compare: Out1 output

General-purpose digital I/O pin Timer_B, capture: CCI2A/B input, compare: Out2 output

General-purpose digital I/O pin USCIA transmit data output in UART mode, slave data in/master out in SPI mode

General-purpose digital I/O pin USCI A0 receive data input in UART mode, slave data out/master in in SPI mode

General-purpose digital I/O pin Comparator_A output LCD segment output 2

General-purpose digital I/O pin LCD segment output 3

General-purpose digital I/O pin USCI B0 slave transmit enable/USCI A0 clock input/output

General-purpose digital I/O pin USCI B0 slave in/master out in SPI mode, SDA I LCD segment output 26

General-purpose digital I/O pin USCI B0 slave out/master in in SPI mode, SCL I LCD segment output 27

General-purpose digital I/O USCI B0 clock i nput/output, USCI A0 slave transmit enable

General-purpose digital I/O pin LCD segment output 28

General-purpose digital I/O pin LCD segment output 29

General-purpose digital I/O pin LCD segment output 30

General-purpose digital I/O pin LCD segment output 31

General-purpose digital I/O pin LCD segment output 11

General-purpose digital I/O pin LCD segment output 10

General-purpose digital I/O pin LCD segment output 9

General-purpose digital I/O pin LCD segment output 8

General-purpose digital I/O pin LCD segment output 7

General-purpose digital I/O pin LCD segment output 6

General-purpose digital I/O pin LCD segment output 5

General-purpose digital I/O pin LCD segment output 4

CdatainI2C mode

C clock in I2C mode

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MSP430FG47x

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Terminal Functions (continued)

TERMINAL

NO.

NAME

COM0 33 L8 O Common output, COM0--3 are used for LCD backplanes

P5.0/S20 27 L5 I/O

P5.1/S21 28 M5 I/O

P5.2/COM1 34 M8 I/O

P5.3/COM2 35 L9 I/O

P5.4/COM3 36 M9 I/O

LCDCAP/R33 37 J9 I/O

P5.5/R23 38 M10 I/O

113 PIN

General-purpose digital I/O pin LCD segment output 20

General-purpose digital I/O pin LCD segment output 21

General-purpose digital I/O pin common output, COM0--3 are used for LCD backplanes

Capacitor connection for LCD charge pump input port of most positive analog LCD level (V4)

General-purpose digital I/O pin input port of the second most positive analog LCD level (V3)

P5.6/LCDREF/ R13

P5.7/R03 40 M11 I/O

P6.0/A0+/OA0O 67 B8 I/O

P6.1/A0--/OA0FB 66 B9 I/O

P6.2/OA0I1 (SW0A)

P6.3/A1+/OA1O 64 D9 I/O

P6.4/A1--/OA1FB 63 A10 I/O

P6.5/OA0I2 (SW0B)

P6.6/OA1I1 (SW1A)

P6.7/OA1I2/ SVSIN (SW1B)

S12 19 L1 O LCD segment output 12

S13 20 M1 O LCD segment output 13

S14 21 M2 O LCD segment output 14

S15 22 M3 O LCD segment output 15

S16 23 L3 O LCD segment output 16

39 L10 I/O

65 A9 I/O

62 B10 I/O

61 A11 I/O

59 B12 I/O

General-purpose digital I/O pin External LCD reference voltage input input port of the third most positive analog LCD level (V3 or V2)

General-purpose digital I/O pin input port of the fourth most positive analog LCD level (V1)

General-purpose digital I/O pin SD16 positive analog input A0 OA0, output

General-purpose digital I/O pin SD16 positive negative input A0 OA0, analog input feedback

General-purpose digital I/O pin OA0, analog input I1

General-purpose digital I/O pin SD16 positive analog input A1 OA1, output

General-purpose digital I/O pin SD16 positive negative input A1 OA1, analog input feedback

General-purpose digital I/O pin OA0, analog input I2

General-purpose digital I/O pin OA1, analog input I1

General-purpose digital I/O pin OA1, analog input I2 SVS input

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MSP430FG47x

I/ODESCRIPTIO

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Terminal Functions (continued)

TERMINAL

NO.

NAME

S17 24 L4 O LCD segment output 17

S18 25 M4 O LCD segment output 18

S19 26 J4 O LCD segment output 19

S22 29 L6 O LCD segment output 22

S23 30 M6 O LCD segment output 23

S24 31 L7 O LCD segment output 24

S25 32 M7 O LCD segment output 25

GND 7 E2 Ground. It is used to shield the oscillator. See Note 1.

XIN 8 E1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected.

XOUT 9 F1 O Output port for crystal oscillator XT1. Standard or watch crystals can be connected.

GND 10 F2 Ground. It is used to shield the oscillator. See Note NO TAG.

REF

RST/NMI 74 B5 I Reset input, nonmaskable interrupt input port, or bootstrap loader start (in flash devices).

TCK 73 A5 I

TDI/TCLK 71 A6 I Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.

TDO/TDI 70 B7 I/O Test data output port. TDO/TDI data output or programming data input terminal.

TMS 72 B6 I Test mode select. TMS is used as an input port for device programming and test.

XT2OUT 68 A8 O Output terminal of crystal oscillator XT2

XT2IN 69 A7 I Input port for crystal oscillator XT2

Reserved NA B11,

NOTE 1: It is recommended to connect GND externally to DVss.

113 PIN

60 A12 O Input for an external reference voltage/internal reference voltage output

Test clock (JTAG). TCK is the clock input port for device programming test and bootstrap loader start.

BGA package unused balls. Connection to DVSS/AVSSrecommended. D6, D7, D8, E4, E5, E6, E7, E8, E9, F4, F5, F8, F9, G4, G5,G8,

G9, H4,

H5, H6, H7, H8, H9, J5,

J6, J7, J8, L2,

L11

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MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

short-form description

CPU

The MSP430 CPU has a 16--bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.

The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers.

Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions.

instruction set

The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 1 shows examples of the three types of instruction formats, and Table 2 lists the address modes.

Program Counter

Stack Pointer

Status Register

Constant Generator

General-Purpose Register

PC/R0

SP/R1

SR/CG1/R2

CG2/R3

R10

R11

R12

R13

R14

R15

Table 1. Instruction Word Formats

Dual operands, source-destination e.g., ADD R4,R5 R4 + R5 ------> R5

Single operands, destination only e.g., CALL R8 PC ---->(TOS), R8----> PC

Relative jump, un/conditional e.g., JNE Jump-on-equal bit = 0

Table 2. Address Mode Descriptions

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed F F MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5)—> M(6+R6)

Symbolic (PC relative) F F MOV EDE,TONI M(EDE) —> M(TONI)

Absolute F F MOV&MEM,&TCDAT M(MEM) —> M(TCDAT)

Indirect F MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) —> M(Tab+R6)

Indirect

autoincrement

Immediate F MOV #X,TONI MOV #45,TONI #45 —> M(TONI)

NOTE: S = source D = destination

F MOV @Rn+,Rm MOV @R10+,R11

MOV Rs,Rd MOV R10,R11 R10 —> R11

M(R10) —> R11 R10 + 2—> R10

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MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

operating modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the five low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

D Active mode (AM)

-- All clocks are active

D Low-power mode 0 (LPM0)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control remains active

D Low-power mode 1 (LPM1)

-- CPU is disabled

-- ACLK and SMCLK remain active

-- FLL+ loop control is disabled

D Low-power mode 2 (LPM2)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator remains enabled

-- ACLK remains active

D Low-power mode 3 (LPM3)

-- CPU is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- ACLK remains active

D Low-power mode 4 (LPM4)

-- CPU is disabled

-- ACLK is disabled

-- MCLK, FLL+ loop control, and DCOCLK are disabled

-- DCO’s dc generator is disabled

-- Crystal oscillator is stopped

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MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

interrupt vector addresses

The interrupt vectors and the power-up starting address are located in the address range 0xFFFF to 0xFFC0. The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.

If the reset vector (located at address 0xFFFE) contains 0xFFFF (e.g., flash is not programmed) the CPU goes into LPM4 immediately after power--up.

INTERRUPT SOURCE INTERRUPT FLAG SYSTEM INTERRUPT

Power-Up

External Reset

Watchdog

PC Out--of--Range (see Note 4)

Flash Memory Access Violation

NOTES: 1. Multiple source flags

Flash Memory

NMI

Oscillator Fault

Timer_B3 TBCCR0 CCIFG0 (see Note 2) Maskable 0xFFFA 13

Timer_B3

Comparator_A CAIFG Maskable 0xFFF6 11

Watchdog Timer+ WDTIFG Maskable 0xFFF4 10

USCI_A0/USCI_B0 receive

USCI_B0 I2C status

USCI_A0/USCI_B0 transmit

USCI_B0 I2C receive/transmit

SD16_A SD16CCTLx SD16OVIFG, SD16CCTLx SD16IFG

Timer_A3 TACCR0 CCIFG0 (see Note 2) Maskable 0xFFEC 6

Timer_A3

I/O Port P1 (Eight Flags) P1IFG.0 to P1IFG.7 (see Notes 1 and 2) Maskable 0xFFE8 4

DAC12 DAC12_0IFG, DAC12_1IFG Maskable 0xFFE6 3

I/O Port P2 (Eight Flags) P2IFG.0 to P2IFG.7 (see Notes 1 and 2) Maskable 0xFFE2 1

Basic Timer1/RTC BTIFG Maskable 0xFFE0 0, lowest

2. Interrupt flags are located in the module.

3. A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh). (Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.

4. Access and key violations, KEYV and ACCVIFG.

5. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

6. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.

NMIIFG (see Notes 1 and 3)

OFIFG (see Notes 1 and 3)

ACCVIFG (see Notes 1, 2 and 4)

TBCCR1 CCIFG1 ... TBCCR3 CCIFG3,

TBIFG (see Notes 1 and 2)

UCA0RXIFG, UCB0RXIFG

UCA0TXIFG, UCB0TXIFG

TACCR1 CCIFG1 and TACCR2 CCIFG2,

TAIFG (see Notes 1 and 2)

PORIFG RSTIFG WDTIFG

KEYV

(see Note 1)

(see Notes 1 and 5)

(see Note 1 and 6)

(see Notes 1 and 2)

Reset 0xFFFE 15, highest

(Non)maskable (Non)maskable (Non)maskable

Maskable 0xFFF8 12

Maskable 0xFFF2 9

Maskable 0xFFF0 8

Maskable 0xFFEE 7

Maskable 0xFFEA 5

Maskable 0xFFE4 2

WORD

ADDRESS

0xFFFC 14

PRIORITY

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special function registers

Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits not allocated to a functional purpose are not physically present in the device. This arrangement provides simple software access.

interrupt enable 1 and 2

Address76543210

00h

WDTIE Watchdog timer interrupt enable. Inactive if watchdog mode is selected. Active if watchdog

timer is configured in interval timer mode.

OFIE Oscillator fault enable NMIIE (Non)maskable interrupt enable ACCVIE Flash access violation interrupt enable

Address76543210

01h

BTIE

rw--0 rw--0 rw--0 rw--0 rw--0

ACCVIE NMIIE OFIE WDTIE

rw--0 rw--0 rw--0 rw--0

UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

UCA0RXIE USCI_A0 receive interrupt enable UCA0TXIE USCI_A0 transmit interrupt enable UCB0RXIE USCI_B0 receive interrupt enable UCB0TXIE USCI_B0 transmit interrupt enable BTIE Basic timer interrupt enable

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interrupt flag register 1 and 2

Address76543210

02h

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on V

power-up or a reset condition at RST/NMI pin in reset mode.

OFIFG Flag set on oscillator fault. RSTIFG External reset interrupt flag. Set on a reset condition at RST

on V

power-up.

PORIFG Power-on interrupt flag. Set on V NMIIFG Set via RST

Address76543210

03h

BTIFG

rw--0 rw--1 rw--0 rw--1 rw--0

/NMI pin.

NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw--0 rw--(0) rw--(1) rw-- 1 rw--(0)

/NMI pin in reset mode. Reset

power-up.

UCB0

TXIFG

UCB0

RXIFG

UCA0 TXIFG

UCA0

RXIFG

UCA0RXIFG USCI_A0 receive interrupt flag UCA0TXIFG USCI_A0 transmit interrupt flag UCB0RXIFG USCI_B0 receive interrupt flag UCB0TXIFG USCI_B0 transmit interrupt flag BTIFG Basic Timer1 interrupt flag

Legend rw:

rw-0,1: rw-(0,1):

Bit can be read and written. Bit can be read and written. It is Reset or Set by PUC. Bit can be read and written. It is Reset or Set by POR.

SFR bit is not present in device

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MSP430FG47x

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memory organization

MSP430FG477 MSP430FG478 MSP430FG479

Memory Main: interrupt vector Main: code memory

Information memory Size

Boot memory Size

RAM Size 2KB

Peripherals 16-bit

bootstrap loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the application report Features of the MSP430 Bootstrap Loader, literature number SLAA089.

Size Flash Flash

Flash

ROM

8-bit

8-bit SFR

32KB

0FFFFh to 0FFE0h

0FFFFh to 08000h

256 Byte

010FFh to 01000h

1KB

0FFFh to 0C00h

09FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

48KB 0FFFFh to 0FFE0h 0FFFFh to 04000h

256 Byte

010FFh to 01000h

1KB

0FFFh to 0C00h

2KB

09FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

60KB

0FFFFh to 0FFE0h

0FFFFh to 01100h

256 Byte

010FFh to 01000h

1KB

0FFFh to 0C00h

2KB

09FFh to 0200h

01FFh to 0100h

0FFh to 010h

0Fh to 00h

BSL FUNCTION PN PACKAGE PINS ZQW PACKAGE PINS

Data Transmit 58 - P1.0 C11 - P1.0

Data Receive 57 - P1.1 C12 - P1.1

flash memory (Flash)

The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

D Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

D Segments 0 to n may be erased in one step, or each segment may be individually erased.

D Segments A to D can be erased individually, or as a group with segments 0 to n.

Segments A to D are also called information memory.

D Segment A might contain calibration data. After reset, segment A is protected against programming or

erasing. It can be unlocked, but care should be taken not to erase this segment if this calibration data is required.

D Flash content integrity check with marginal read modes.

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peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x4xx Family User’s Guide, literature number SLAU056.

oscillator and system clock

The clock system in the MSP430FG47x is supported by the FLL+ module, which includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO), and a 8-MHz high-frequency crystal oscillator (XT1), plus a 8-MHz high-frequency crystal oscillator (XT2). The FLL+ clock module is designed to meet the requirements of both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and stabilizes in less than 6 s. The FLL+ module provides the following clock signals:

D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal D Main clock (MCLK), the system clock used by the CPU D Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules D ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8

brownout, supply voltage supervisor

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below a user selectable level and supports both supply voltage supervision (the device is automatically reset) and supply voltage monitoring (SVM, the device is not automatically reset).

The CPU begins code execution after the brownout circuit releases the device reset. However, V have ramped to V reaches V

CC(min)

. If desired, the SVS circuit can be used to determine when VCCreaches V

at that time. The user must ensure the default FLL+ settings are not changed until V

CC(min)

digital I/O

There are six 8-bit I/O ports implemented, ports P1 through P6.

D All individual I/O bits are independently programmable. D Any combination of input, output, and interrupt conditions is possible. D Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2. D Read/write access to port-control registers is supported by all instructions.

may not

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MSP430FG47x

DEVICEINPUT

MODULEINPUT

MODUL

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

watchdog timer (WDT+)

The primary function of the WDT+ module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.

Basic Timer1 and Real-Time Clock

The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter. Both timers can be read and written by software. The Basic Timer1 is extended to provide an integrated real-time clock (RTC). An internal calendar compensates for month with less than 31 days and includes leap year correction.

LCD_A driver with regulated charge pump

The LCD_A driver generates the segment and common signals required to drive an LCD display. The LCD_A controller has dedicated data memory to hold segment drive information. Common and segment signals are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this peripheral. The module can provide a LCD voltage independent of the supply voltage via an integrated charge pump. Furthermore, it is possible to control the level of the LCD v oltage and, thus, contrast in software.

Timer_A3

Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

TIMER_A3 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PN ZQW

P1.5 -- 51 F11 TAC L K TAC L K

P1.5 -- 51 F11 TAINCLK INCLK

P1.0 -- 58 C11 TA0 CCI0A

P1.1 -- 57 C12 TA0 CCI0B

P1.2 -- 56 D11 TA1 CCI1A

P2.0 -- 4 C2 TA 2 CCI2A

DEVICE INPUT MODULE INPUT MODULE

SIGNAL

ACLK ACLK

SMCLK SMCLK

CAOUT (internal) CCI1B

ACLK (internal) CCI2B

NAME

GND

BLOCK

Timer N

CCR0 TA0

CCR1 TA1

CCR2 TA2

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PN ZQW

P1.0 -- 58 C11

P1.1 -- 57 C12

P1.2 -- 56 D11

P2.0 -- 4 C2

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MSP430FG47x

DEVICEINPUT

MODULEINPUT

MODUL

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Timer_B3

Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.

TIMER_B3 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PN ZQW

P1.4 -- 54 E11 TBCLK TBCLK

P1.4 -- 54 E11 TBCLK

P2.1 -- 3 C1 TB0 CCI0A

P2.1 -- 3 C1 TB0 CCI0B

P2.2 -- 2 B1 TB1 CCI1A

P2.2 -- 2 B1 TB1 CCI1B

P2.3 -- 77 B4 TB2 CCI2A

NOTE 1: The inversion of TBCLK is done inside the module.

DEVICE INPUT MODULE INPUT MODULE

SIGNAL

ACLK ACLK

SMCLK SMCLK

(See Note 1)

ACLK (internal) CCI2B

NAME

INCLK

GND

BLOCK

Timer NA

CCR0 TB0

CCR1 TB1

CCR2 TB2

MODULE OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PN ZQW

P2.1 -- 3 C1

P2.2 -- 2 B1

P2.3 -- 77 B4

universal serial communication interfaces (USCIs) (USCI_A0, USCI_B0)

The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 pin or 4 pin), I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.

USCI_A0 provides support for SPI (3 pin or 4 pin), UART, enhanced UART and IrDA.

USCI_B0 provides support for SPI (3 pin or 4 pin) and I2C.

Comparator_A

The primary function of the comparator_A module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.

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SD16_A

The SD16_A module supports 16-bit analog-to-digital conversions. The module implements a 16-bit sigma-delta core and a reference generator. In addition to external analog inputs, an internal V temperature sensor are also available.

DAC12

The DAC12 module is a 12-bit R-ladder voltage-output DAC. The DAC12 may be used in 8-bit or 12-bit mode. When multiple DAC12 modules are present, they may be grouped together for synchronous operation.

The MSP430FG47x has two configurable low-current general-purpose operational amplifiers. Each OA input and output terminal is software-selectable and offer a flexible choice of connections for various applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-to-digital conversion.

OA0 SIGNAL CONNECTIONS

INPUT PIN NUMBER

PN ZQW

P1.6 -- 50 G12 OA0I0 OAxI0

P6.2 -- 65 A9 OA0I1 OAxI1

P6.5 -- 62 B10 OA0I2 OAxIA

P1.2 -- 56 D11 OA0I3 OAxIB

P1.4 -- 54 E11 OA1I0 OAxI0

P6.6 -- 61 A11 OA1I1 OAxI1

P6.7 -- 59 B12 OA1I2 OAxIA

P1.3 -- 55 D12 OA1I3 OAxIB

DEVICE

INPUT

SIGNAL

MODULE MODULE

INPUT NAME

BLOCK

OA0 OA0OUT OA0O

OA1 OA1OUT OA1O

MODULE

OUTPUT

SIGNAL

OUTPUT PIN NUMBER

PN ZQW

P6.0 -- 67 B8

P6.4 -- 64 A10

sense and

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MSP430FG47x

Timer_B3Capture/compareregister

TBCCR

0196h

Capture/compareregister

TBCCR

0194h

p/p

Timer_A3Capture/compareregister

TACCR

0176h

Capture/compareregister

TACCR

0174h

p/p

lash

FCTL2

012Ah

DAC12DAC12_1dat

DAC12_1DA

01CAh

DAC12_1contro

DAC12_1CT

01C2h

SD16_

Generalcontro

SD16CTL

0100h

Channel0control

SD16CCTL0

0102h

)

ppg

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

peripheral file map

PERIPHERALS WITH WORD ACCESS

Watchdog Watchdog timer control WDTCTL 0120h

Timer_B3 Capture/compare register 2 TBCCR2 0196h

Capture/compare register 1 Capture/compare register 0 Timer_B register TBR 0190h Capture/compare control 2 TBCCTL2 0186h Capture/compare control 1 TBCCTL1 0184h Capture/compare control 0 TBCCTL0 0182h Timer_B control TBCTL 0180h Timer_B interrupt vector TBIV 011Eh

Timer_A3 Capture/compare register 2 TACCR2 0176h

Capture/compare register 1 Capture/compare register 0 Timer_A register TAR 0170h Capture/compare control 2 TACCTL2 0166h Capture/compare control 1 TACCTL1 0164h Capture/compare control 0 TACCTL0 0162h Timer_A control TACTL 0160h Timer_A interrupt vector TAI V 012Eh

Flash Flash c ontrol 4

Flash control 3

contro

Flash control 1

DAC12 DAC12_1 data DAC12_1DAT 01CAh

DAC12_1 control DAC12_0 data DAC12_0 control

SD16_A General control SD16CTL 0100h (see also: Peripherals with

yteAccess

OA switches Switch control register 1 SWCTL_1 00CEh

OA switches Switch control register

OA1 Operational amplifier 1 control register 1 OA1CTL1 00C3h

OA0 Operational amplifier 0 control register 1 OA0CTL1 00C1h

SD16_A (see also: Peripherals with Word Access)

Channel 0 control Channel 0 conversion memory Interrupt vector word register SD16IV 0110h

PERIPHERALS WITH BYTE ACCESS

Switch control register 1

Operational amplifier 1 control register 0 OA1CTL0 00C2h

Operational amplifier 0 control register 0 OA0CTL0 00C0h

Channel 0 input control Analog enable

TBCCR1 TBCCR0

TACCR1 TACCR0

FCTL4 FCTL3

FCTL1

DAC12_1CTL DAC12_0DAT DAC12_0CTL 01C0h

SD16CCTL0 SD16MEM0

SWCTL SWCTL1

SD16INCTL0 SD16AE

0194h 0192h

0174h 0172h

01BEh 012Ch

0128h

01C2h 01C8h

0102h 0112h

00CFh 00CEh

0B0h 0B7h

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peripheral file map (continued)

LCD_A LCD voltage control 1

USCI A0/B0

Comparator_A

Brownout, SVS SVS control register (reset by brownout signal) SVSCTL 056h

FLL+ Clock FLL+ control 1 FLL_CTL1 054h

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

LCDAVCTL1 LCD voltage control 0 LCD voltage port control 1 LCD voltage port control 0 LCD memory 20 : LCD memory 16 LCD memory 15 : LCD memory 1 LCD control and mode

USCI A0 auto baud rate control UCA0ABCTL 0x005D

USCI A0 transmit buffer UCA0TXBUF 0x0067

USCI A0 receive buffer UCA0RXBUF 0x0066

USCI A0 status UCA0STAT 0x0065

USCI A0 modulation c ontrol UCA0MCTL 0x0064

USCI A0 baud rate control 1 UCA0BR1 0x0063

USCI A0 baud rate control 0 UCA0BR0 0x0062

USCI A0 control 1 UCA0CTL1 0x0061

USCI A0 control 0 UCA0CTL0 0x0060

USCI A0 IrDA receive control UCA0IRRCTL 0x005F

USCI A0 IrDA transmit control UCA0IRTCTL 0x005E

USCI B0 transmit buffer UCB0TXBUF 0x006F

USCI B0 receive buffer UCB0RXBUF 0x006E

USCI B0 status UCB0STAT 0x006D

USCI B0 I2C Interrupt enable UCB0CIE 0x006C

USCI B0 baud rate control 1 UCB0BR1 0x006B

USCI B0 baud rate control 0 UCB0BR0 0x006A

USCI B0 control 1 UCB0CTL1 0x0069

USCI B0 control 0 UCB0CTL0 0x0068

USCI B0 I2C slave address UCB0SA 0x011A

USCI B0 I2C own address UCB0OA 0x0118

Comparator_A port disable CAPD 05Bh

Comparator_A control2 CACTL2 05Ah

Comparator_A control1 CACTL1 059h

FLL+ control 0 FLL_CTL0 053h

System clock frequency control SCFQCTL 052h

System clock frequency integrator SCFI1 051h

System clock frequency integrator SCFI0 050h

LCDAVCTL0

LCDAPCTL1

LCDAPCTL0

LCDM20

LCDM16

LCDM15

LCDM1

LCDACTL

0AFh 0AEh 0ADh 0ACh 0A4h : 0A0h 09Fh : 091h 090h

MSP430FG47x

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peripheral file map (continued)

PERIPHERALS WITH BYTE ACCESS

RTC (Basic Timer1)

Port P6

Port P5

Port P4

Port P3

Port P2

Real-time clock year high byte Real-time clock year low byte Real-time clock month Real-time clock day of month Basic Timer1 counter Basic Timer1 counter Real-time counter 4 (Real-time clock day of week) Real-time counter 3 (Real-time clock hour) Real-time counter 2 (Real-time clock minute) Real-time counter 1 (Real-time clock second) Real-time clock control Basic Timer1 control

Port P6 selection P6SEL 037h

Port P6 direction P6DIR 036h

Port P6 output P6OUT 035h

Port P6 input P6IN 034h

Port P5 selection P5SEL 033h

Port P5 direction P5DIR 032h

Port P5 output P5OUT 031h

Port P5 input P5IN 030h

Port P4 selection P4SEL 01Fh

Port P4 direction P4DIR 01Eh

Port P4 output P4OUT 01Dh

Port P4 input P4IN 01Ch

Port P3 selection P3SEL 01Bh

Port P3 direction P3DIR 01Ah

Port P3 output P3OUT 019h

Port P3 input P3IN 018h

Port P2 selection P2SEL 02Eh

Port P2 interrupt enable P2IE 02Dh

Port P2 interrupt-edge select P2IES 02Ch

Port P2 interrupt flag P2IFG 02Bh

Port P2 direction P2DIR 02Ah

Port P2 output P2OUT 029h

Port P2 input P2IN 028h

RTCYEARH RTCYEARL RTCMON RTCDAY BTCNT2 BTCNT1 RTCNT4 (RTCDOW) RTCNT3 (RTCHOUR) RTCNT2 (RTCMIN) RTCNT1 (RTCSEC) RTCCTL BTCTL

04Fh 04Eh 04Dh 04Ch 047h 046h 045h

044h

043h

042h

041h 040h

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peripheral file map (continued)

SFR

int

tflag2IFG2003h

SFRinterruptenable2IE2001hS

PERIPHERALS WITH BYTE ACCESS (CONTINUED)

Port P1

pecia

unc

ons

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Port P1 selection 2 register Port P1 selection

Port P1 interrupt enable P1IE 025h

Port P1 interrupt-edge select P1IES 024h

Port P1 interrupt flag P1IFG 023h

Port P1 direction P1DIR 022h

Port P1 output P1OUT 021h

Port P1 input P1IN 020h

errup SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h

FR interrupt enable 1 IE1 000h

P1SEL2 P1SEL

057h 026h

MSP430FG47x

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MSP430FG47x

(seeNote1

)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

absolute maximum ratings over operating free-air temperature (see Note 1)

Voltage applied at VCCto V

Voltage applied to any pin (see Note 2) --0.3 V to V

Diode current at any device terminal . 2mA......................................................

Storage temperature, T

: (unprogrammed device, see Note 3) --55C to 150C.......................

stg

(programmed device, see Note 3) --40Cto85C..........................

NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

2. All voltages referenced to V is applied to the TDI/TCLK pin when blowing the JTAG fuse.

3. Higher temperature may be applied during board soldering process according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage

recommended operating conditions

MIN NOM MAX UNITS

Supply voltage during program execution, V

(AVCC=DVCC=VCC)

Supply voltage during flash memory programming, V

(AVCC=DVCC=VCC)

Supply voltage, VSS(AVSS=DVSS=VSS) 0 0 V

Operating free-air temperature range, T

LFXT1 crystal frequency, f (see Note 1)

XT2 crystalfrequency,

Systemfrequency, MCLK,ACLK, SMCLK ,

NOTES: 1. In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

(LFXT1)

(XT2)

LF selected, XTS_FLL = 0

XT1 selected, XTS_FLL = 1

(System)

Watch crystal 32.768 kHz

Ceramic resonator 0.45 6 MHz

Crystal 1 6 MHz

Ceramic resonator 0.45 8

Crystal 1 8

VCC=1.8V dc 4.15

VCC=2.5V dc 8

1.8 3.6 V

2.2 3.6 V

-- 4 0 85 C

--0.3 V to 4.1 V......................................................

+0.3V.......................................

MHz

System

8 MHz

4.15 MHz

Figure 1. Frequency vs Supply Voltage, Typical Characteristics

(MHz)

Supply voltage range, MSP430FG47x, during program execution

1.8 Supply Voltage - V

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2.2 2.5 3.6

Supply voltage range , MSP430FG47x, during flash memory programming

MSP430FG47x

f=f

(MCLK

)

(SMCLK)

=1MHz

)

Lowpowermode(LPM0

)

Low-powermode(LPM3)

(MCLK

)f(SMCLK)

0MHz,

ALCD_Aenabled,LCDCPEN=0

(

LCD(ACLK)

)

Low-powermode(LPM3)

(MCLK

)f(SMCLK)

0MHz,

2.2

ALCD_Aenabled,LCDCPEN=0

(

LCD(ACLK)

)

0Hz,SCG

0=1(seeNote2)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

supply current into AVCC+DVCCexcluding external current

PARAMETER TEST CONDITIONS V

Active mode (see Note 1)

(AM)

(ACLK)

= 32,768 Hz

=1MHz,

XTS = 0, SELM = (0,1)

(LPM0)

Low-power mode(LPM0 (see Note 1)

Low-power mode (LPM2),

(LPM2)

(MCLK) =f(SMCLK) = 0 MHz,

f(ACLK) = 32,768 Hz, SCG0 = 0 (see Note 2)

(LPM3)

(MCLK)=f(SMCLK)

= 32,768 Hz, SCG0 = 1

(ACLK)

Basic Timer1 enabled ,ACLK selected LCD

enabled,LCDCPEN = 0:

(static mode , f

=0MHz,

LCD=f(ACLK)

(see Note 2 and Note 3)

(LPM3)

(MCLK)=f(SMCLK)

= 32,768 Hz, SCG0 = 1

(ACLK)

Basic Timer1 enabled ,ACLK selected LCD

enabled,LCDCPEN = 0:

(4-mux mode, f

=0MHz,

LCD=f(ACLK)

(see Note 2 and Note 3)

Low-power mode (LPM4)

(LPM4)

(MCLK) (ACLK)

=0MHz,

(SMCLK)

NOTES: 1. Timer_Aisclockedbyf

2. All inputs are tied to 0 V or to V

3. The LPM3 currents are characterized with a Micro Crystal CC4V--T1A (9pF) crystal and OSCCAPx = 01h.

/32)

=0MHz,

(DCOCLK)

2.2 V 262 295

=--40Cto85C

3V 420 460

=--40Cto85C

2.2 V 32 62

3V 51 77

2.2 V 5 9

=--40Cto85C

3V 7 13

TA=--40C 1.0 1.8

TA=25C

=60C

2.2

TA=85C 2.3 4.0

=--40C 1.2 2.0

=25C

=60C

TA=85C 2.7 4.5

TA=--40C 1.0 3.0

=25C

2.2 V

TA=85C

=--40C 1.8 3.3

=25C

=85C

TA=--40C 0.1 0.5

TA=25C

TA=60C

2.2

TA=85C 1.7 3.0

TA=--40C 0.1 0.8

TA=25C

TA=60C

TA=85C 1.5 3.5

= 1 MHz. All i nputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

. Outputs do not source or sink any current.

MIN TYP MAX UNIT



1.0 1.8

1.1 2.0



1.2 2.0

1.4 2.2

1.1 3.2

3.5 6.0



2.0 4.0

4.2 7.5

0.1 0.5

0.7 1.1



0.1 0.8

0.8 1.2

Current consumption of active mode versus system frequency

(AM)=I(AM)

[1 MHz]  f

Current consumption of active mode versus supply voltage

(AM)=I(AM) [3 V]

+ 200 A/V  (VCC–2.2V)

(System)

[MHz]

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MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

typical characteristics -- LPM4 current

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

-- Low-Power Mode 4 Current -- A

0.4

LPM4

0.2

0.0

--40.0 --20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0

Vcc=3.6V

Vcc=3.0V

Vcc=2.2V

Vcc=1.8V

TA-- Temperature -- C

Figure 2. I

-- LPM4 Current vs Temperature

LPM4

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MSP430FG47x

PortP1,P2:P1.xtoP2.x,externaltriggersigna

Timer_Aclockfrequencyexternally

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Schmitt-trigger inputs -- Ports P1, P2, P3, P4, P5, and P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)

PARAMETER TEST CONDITIONS MIN MAX UNIT

IT+

IT--

hys

Positive-going input threshold voltage

Negative-going input threshold voltage

Input voltage hysteresis (V

IT+

-- V

IT--

)

inputs Px.y, TAx

PARAMETER TEST CONDITIONS V

(int)

(cap)

(TAext)

(TAint)

External interrupt timing

Timer

capture timing TA0, TA1, TA2

clockfrequencyexternall

applied to pin

Timer

,clockfrequency SMCLK orACLK signal selected

NOTES: 1. The external signal sets the interrupt flag every time the minimum t

shorter than t

(int)

Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag (see Note 1)

TACLK, INCLK: t

(H)=t(L)

(int)

leakage current -- Ports P1, P2, P3, P4, P5, and P6 (see Note 1)

PARAMETER TEST CONDITIONS MIN MAX UNIT

lkg(Px.y)

NOTES: 1. The leakage current is measured with VSSor VCCapplied to the corresponding pin(s), unless otherwise noted.

Leakage current Port Px V

2. The port pin must be selected as input.

(see Note 2) VCC=2.2V/3V 50 nA

(Px.y)

VCC=2.2V 1.1 1.55

=3V 1.5 1.98

VCC=2.2V 0.4 0.9

=3V 0.9 1.3

VCC=2.2V 0.3 1.1

VCC=3V 0.5 1

2.2 V 62

3V 50

2.2 V 62

3V 50

2.2 V 8

3V 10

2.2 V 8

3V 10

MIN MAX UNIT

MHz

parameters are met. It may be set even with trigger signals

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MSP430FG47x

1.1/TA0/MCL

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

outputs -- Ports P1, P2, P3, P4, P5, and P6

PARAMETER TEST CONDITIONS MIN MAX UNIT

High-level output voltage

Low-level output voltage

NOTES: 1. The maximum total current, I

specified voltage drop.

2. The maximum total current, I specified voltage drop.

output frequency

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(Px.y)

(MCLK)

(Xdc)

(x=1,2,3,4,5,6,0 y  7)

P1.1/TA0/MCLK CL=20pF f

Duty cycle of output frequency

OH(max) =

OL(max) =

and I

OH(max)

and I

OH(max)

CL=20pF, I

= 1.5 mA

P1.1/TA0/MCLK C

=20pF,

=2.2V/3V

-- 1 . 5 m A , V

-- 6 m A , V

-- 1 . 5 m A , V

-- 6 m A , V

1.5 mA, V

6mA, V

1.5 mA, V

6mA, V

for all outputs combined, should not exceed 12 mA to satisfy the maximum

OL(max),

for all outputs combined, should not exceed 48 mA to satisfy the maximum

OL(max),

2.2 V, SeeNote1 VCC--0.25 V

CC =

2.2 V, SeeNote2 VCC-- 0 . 6 V

CC =

3V, SeeNote1 VCC--0.25 V

CC =

3V, SeeNote2 VCC-- 0 . 6 V

CC =

2.2 V, SeeNote1 V

CC =

2.2 V, SeeNote2 V

CC =

3V, SeeNote1 V

CC =

3V, SeeNote2 V

CC =

2.2 V / 3 V DC f

CC =

(MCLK)=f(XT1)

(MCLK)=f(DCOCLK)

40% 60%

50%-15 ns

SSVSS

50%

VSS+0.6

+0.25

System

50%+

15 ns

MHz

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MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

outputs -- Ports P1, P2, P3, P4, P5, and P6 (continued)

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

VCC=2.2V P1.0

-- Typical Low-level Output Current -- mA

0.0 0.5 1.0 1.5 2.0 2.5

VOL-- Low-Level Output Voltage -- V

TA=--40C

TA=25C

TA=85C

Figure 3

TYPICAL LOW-LEVEL OUTPUT CURRENT

LOW-LEVEL OUTPUT VOLTAGE

VCC=3V

P1.0

-- Typical Low-level Output Current -- mA 5

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VOL-- Low-Level Output Voltage -- V

TA=--40C

TA=25C

TA=85C

Figure 4

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

0.0 VCC=2.2V P1.0

-- 5 . 0

--10.0

--15.0

-- Typical High-level Output Current -- m

--20.0

--25.0

--30.0

TA=85C

TA=--40C

0.0 0.5 1.0 1.5 2.0 2.5

VOH-- High-Level Output Voltage -- V

TA=25C

Figure 5

TYPICAL HIGH-LEVEL OUTPUT CURRENT

HIGH-LEVEL OUTPUT VOLTAGE

0.0

VCC=3V P1.0

TA=25CTA=85C

TA=--40C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

VOH-- High-Level Output Voltage -- V

-- Typical High-level Output Current -- mA

-- 5 . 0

--10.0

--15.0

--20.0

--25.0

--30.0

--35.0

--40.0

--45.0

--50.0

--55.0

Figure 6

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MSP430FG47x

)

d(LPM3)

Delaytime

CC=

2.2V/3V



MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

wake-up LPM3

PARAMETER TEST CONDITIONS MIN MAX UNIT

f=1MHz 6

d(LPM3

Delay time

f=2MHz

CC =

2.2 V/3 V

f=3MHz

POR/brownout reset (BOR) (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(BOR)

CC(start)

(B_IT--)

hys(B_IT--)

(reset)

Brownout (see Note 2)

dVCC/dt  3 V/s (see Figure 7) 0.7  V

(B_IT--)

dVCC/dt  3 V/s (see Figure 7 through Figure 9) 1.71 V

dVCC/dt  3 V/s (see Figure 7) mV

Pulse length needed at RST/NMI pin to accepted reset internally, V

=2.2V/3V

2 s

NOTES: 1. The current consumption of the brownout module is already included in the ICCcurrent consumption data. The voltage level V

hys(B_IT--)

2. During power up, the CPU begins code execution following a period of t FLL+ settings must not be changed until V

is  1.8V.

 V

CC(min)

, where V

after VCC=V

d(BOR)

is the minimum supply v oltage for the desired

CC(min)

(B_IT--)+Vhys(B_IT--)

operating frequency. See the MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout.

typical characteristics

s

2000 s

. The default

(B_IT--)

CC(start)

(B_IT--)

hys(B_IT--)

d(BOR)

Figure 7. POR/Brownout Reset (BOR) vs Supply Voltage

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SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

typical characteristics (continued)

1.5

-- V

=3V

Typical Conditions

CC(min)

0.5

0.001 1 1000

tpw-- Pulse Width -- s

Figure 8. V

Typical Conditions

1.5

-- V

CC(min)

0.5

0.001 1 1000

Figure 9. V

(CC)min

=3V

CC(min)

Level With a Square Voltage Drop to Generate a POR/Brownout Signal

-- Pulse Width -- s

Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

CC(min)

1ns 1ns

tpw-- Pulse Width -- s

tf=t

tpw-- Pulse Width -- s

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MSP430FG47x

)

hys(SVS_I

T--)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

SVS (supply voltage supervisor/monitor)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(SVSR)

d(SVSon)

settle

(SVSstart)

hys(SVSIT--

(SVS_IT--)

CC(SVS)

(see Note 1)

†

The recommended operating voltage range is limited to 3.6 V.

‡

is the settling time that the comparator o/p needs to have a stable level after VLD is switched VLD  0 to a different VLD value somewhere

settle

between 2 and 15. The overdrive is assumed to be > 50 mV.

NOTE 1: The current consumption of the SVS module is not included in the I

dVCC/dt > 30 V/ms (see Figure 10) 5 150 s

dVCC/dt  30 V/ms 2000 s SVSON, switch from VLD = 0 to VLD  0, VCC=3V 150 300 s

‡

VLD  0

12 s

VLD  0, VCC/dt  3 V/s (see Figure 10) 1.55 1.7 V

VLD = 1 70 120 210 mV

VCC/dt  3 V/s (see Figure 10)

VCC/dt  3 V/s (see Figure 10), External voltage applied on A7

VLD = 2 .. 14

VLD = 15 4.4 20 mV

(SVS_IT--)

x 0.001

(SVS_IT--)

x 0.016

VLD = 1 1.8 1.9 2.05

VLD = 2 1.94 2.1 2.25

VLD = 3 2.05 2.2 2.37

VLD = 4 2.14 2.3 2.48

VLD = 5 2.24 2.4 2.6

VLD = 6 2.33 2.5 2.71

dt  3V/s (see Figure 10 and Figure 11)

VLD = 7 2.46 2.65 2.86

VLD = 8 2.58 2.8 3

VLD = 9 2.69 2.9 3.13

VLD = 10 2.83 3.05 3.29

VLD = 11 2.94 3.2 3.42

3.99

†

VCC/dt  3 V/s (see Figure 10 and Figure 11), External voltage applied on A7

VLD = 12 3.11 3.35 3.61

VLD = 13 3.24 3.5 3.76

VLD = 14 3.43 3.7

†

VLD = 15 1.1 1.2 1.3

VLD  0, VCC=2.2V/3V 10 15 A

current consumption data.

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typical characteristics

(SVS_IT--)

(SVSstart)

(B_IT--)

CC(start)

Brownout

SVS out

hys(SVS_IT--)

hys(B_IT--)

Brownout

Region

d(BOR)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Software sets VLD >0:

SVS is active

SVS Circuit is Active From VLD > to VCC<V(

B_IT-- )

MSP430FG47x

Brown-

out

Region

d(BOR)

Set POR

1.5

-- V

CC(min)

0.5

undefined

d(SVSon)

Figure 10. SVS Reset (SVSR) vs Supply Voltage

Rectangular Drop

Triangular Drop

1 10 1000

-- Pulse Width -- s

100

CC(min)

d(SVSR)

1ns 1ns

Figure 11. V

CC(min)

: Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1)

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tf=t

t -- Pulse Width -- s

MSP430FG47x

StepsizebetweenadjacentDCOtaps:

Temperaturedrif

t,N

(DCO)

=01E0

h,FN_8=FN_4=FN_3=FN_2=0

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

DCO

PARAMETER TEST CONDITIONS V

= 01E0h, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,

(DCOCLK)

(DCO2)

(DCO27)

(DCO2)

(DCO27)

(DCO2)

(DCO27)

(DCO2)

(DCO27)

(DCO2)

(DCO27)

(DCO)

DCOPLUS = 0

FN_8=FN_4=FN_3=FN_2 = 0 , DCOPLUS = 1

FN_8=FN_4=FN_3=FN_2 = 0, DCOPLUS = 1 (see Note 1)

FN_8=FN_4=FN_3=0,FN_2 = 1, DCOPLUS = 1

FN_8=FN_4=FN_3=0,FN_2 = 1, DCOPLUS = 1 (see Note 1)

FN_8=FN_4=0, FN_3= 1,FN_2 = x, DCOPLUS = 1

FN_8=FN_4=0, FN_3= 1,FN_2 = x, DCOPLUS = 1 (see Note 1)

FN_8=0,FN_4= 1,FN_3= FN_2 = x, DCOPLUS = 1

FN_8=0,FN_4=1,FN_3= FN_2 = x, DCOPLUS = 1 (see Note 1)

FN_8=1,FN_4=FN_3=FN_2 = x, DCOPLUS = 1

FN_8=1,FN_4=FN_3=FN_2 = x, DCOPLUS = 1 (see Note 1)

Stepsize between adjacent DCO taps: Sn=f

DCO(Tap n+1)/fDCO(Tap n)

Temperature drift, N

(see Figure 13 for taps 21 to 27)

= 01E0h, FN_8=FN_4=FN_3=FN_2=0

D = 2, DCOPLUS = 0 (see Note 2)

Drift with VCCvariation, N

= 01E0h, FN_8 = FN_4 = FN_3 =

(DCO)

FN_2 = 0, D = 2, DCOPLUS = 0 (see Note 2)

1<TAP 20 1.06 1.11

NOTES: 1. Do not exceed the maximum system frequency.

2. This parameter is not production tested.

2.2 V/3 V 1 MHz

2.2 V 0.3 0.65 1.25

3V 0.3 0.7 1.3

2.2 V 2.5 5.6 10.5

3V 2.7 6.1 11.3

2.2 V 0.7 1.3 2.3

3V 0.8 1.5 2.5

2.2 V 5.7 10.8 18

3V 6.5 12.1 20

2.2 V 1.2 2 3

3V 1.3 2.2 3.5

2.2 V 9 15.5 25

3V 10.3 17.9 28.5

2.2 V 1.8 2.8 4.2

3V 2.1 3.4 5.2

2.2 V 13.5 21.5 33

3V 16 26.6 41

2.2 V 2.8 4.2 6.2

3V 4.2 6.3 9.2

2.2 V 21 32 46

3V 30 46 70

TAP = 27 1.07 1.17

2.2 V –0.2 –0.3 –0.4

3V –0.2 –0.3 –0.4

MIN TYP MAX UNIT

MHz

%_C

0 5 15 %/V

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SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

(DCO)

(DCO3V)

1.0

(DCO)

(DCO20C)

1.0

1.8 3.02.4 3.6

20 6040 85

0-- 2 0-- 4 00

Figure 12. DCO Frequency vs Supply Voltage VCCand vs Ambient Temperature

TA-- CVCC-- V

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SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

1.17

(DCO)

- Stepsize Ratio between DCO Taps

1.11

1.07

1.06

Max

Min

12720

DCO Tap

Figure 13. DCO Tap Step Size

Legend

Tolerance at Tap 27

DCO Frequency Adjusted by Bits

to 25in SCFI1 {N

Tol e r ance a t Tap 2

{DCO}

}

FN_2=0 FN_3=0 FN_4=0 FN_8=0

FN_2=1 FN_3=0 FN_4=0 FN_8=0

Figure 14. Five Overlapping DCO Ranges Controlled by FN_x Bits

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

FN_2=x FN_3=1 FN_4=0 FN_8=0

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FN_2=x FN_3=x FN_4=1 FN_8=0

Overlapping DCO Ranges: Uninterrupted Frequency Range

FN_2=x FN_3=x FN_4=x

FN_8=1

MSP430FG47x

ALFOscillationallowancefor

(seeNote1

)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

crystal oscillator, LFXT1, low frequency modes (see Note 4)

PARAMETER TEST CONDITIONS V

LFXT1,LF

L,eff

Fault,LF

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

LFXT1 oscillator crystal frequency, LF mode 0, 1

Oscillation allowancefor LF crystals

Integrated effective load capacitance, LF mode

Duty cycle, LF mode

Oscillator fault frequency, LF mode (see Note 3)

Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup the effective load capacitance should always match the specification of the used crystal.

2. Measured with logic level input frequency but also applies to operation with crystals.

3. Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag.

4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.

XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32,768 Hz

XTS = 0, LFXT1Sx = 0, f

LFXT1,LF

XTS = 0, LFXT1Sx = 0, f

LFXT1,LF

XTS = 0, XCAPx = 0 1

XTS = 0, XCAPx = 1 5.5

XTS = 0, XCAPx = 2 8.5

XTS = 0, XCAPx = 3 11

XTS = 0, Measured at P1.5/ACLK, f

LFXT1,LF

XTS = 0, XCAPx = 0. LFXT1Sx = 3 (see Note 2)

L,eff

= 32,768 kHz,

=6pF

= 32,768 kHz,

=12pF

2.2 V/3 V 30 50 70 %

= 32,768Hz

2.2 V/3 V 10 10,000 Hz

-- Keep the trace between the device and the crystal as short as possible.

-- Design a good ground plane around the oscillator pins.

-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

-- Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

-- If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

-- Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other

documentation. This signal is no longer required for the serial programming adapter.

MIN TYP MAX UNIT

500

kΩ

200

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MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

crystal oscillator, LFXT1, high frequency modes

PARAMETER TEST CONDITIONS V

LFXT1

L,eff

Duty cycle Measured at P1.5/ACLK, 2.2 V/3 V 40 50 60 %

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

LFXT1 oscillator c rystal frequency Ceramic resonator 1.8 V to 3.6 V 0.45 8 MHz

LFXT1 oscillator c rystal frequency Crystal resonator 1.8 V to 3.6 V 1 8 MHz

Integrated effective load capacitance, HF mode (see Note 1)

2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(see Note 2) 1 pF

crystal oscillator, XT2, high frequency modes

PARAMETER TEST CONDITIONS V

XT2

L,eff

Duty cycle Measured at P1.4/SMCLK, 2.2 V/3 V 40 50 60 %

NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).

XT2 oscillator c rystal frequency Ceramic resonator 1.8 V to 3.6 V 0.45 8 MHz

XT2 oscillator c rystal frequency Crystal resonator 1.8 V to 3.6 V 1 8 MHz

Integrated effective load capacitance, HF mode (see Note 1)

2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.

(see Note 2) 1 pF

MIN TYP MAX UNIT

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MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

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electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

RAM

PARAMETER TEST CONDITIONS MIN MAX UNIT

VRAMh CPUhalted(seeNote1) 1.6 V

NOTE 1: This parameter defines the minimum supply voltage when the data i n program memory RAM remain unchanged. No program execution

LCD_A

CC(LCD)

LCD

NOTES: 1. Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device.

should take place during this supply voltage condition.

PARAMETER TEST CONDITIONS V

CC(LCD)

LCD

Supply Voltage Range

Capacitor on LCDCAP (see Note 1)

Average Supply Current (see Note 2)

Charge pump enabled (LCDCPEN = 1, VLCDx > 0000)

V VLCDx = 1000, All segments on, f

LCD

(see Note 3), TA=25C

=3V,LCDCPEN=1,

LCD(typ)

ACLK

/32, No LCD connected

LCD frequency 1.1 kHz

LCD

LCD voltage VLCDx = 0000 V

LCD voltage VLCDx = 0001 2.60 V

LCD voltage VLCDx = 0010 2.66 V

LCD voltage VLCDx = 0011 2.72 V

LCD voltage VLCDx = 0100 2.78 V

LCD voltage VLCDx = 0101 2.84 V

LCD voltage VLCDx = 0110 2.90 V

LCD voltage VLCDx = 0111 2.96 V

LCD voltage VLCDx = 1000 3.02 V

LCD voltage VLCDx = 1001 3.08 V

LCD voltage VLCDx = 1010 3.14 V

LCD voltage VLCDx = 1011 3.20 V

LCD voltage VLCDx = 1100 3.26 V

LCD voltage VLCDx = 1101 3.32 V

LCD voltage VLCDx = 1110 3.38 V

LCD voltage VLCDx = 1111 3.44 3.60 V

3 V, LCDCPEN = 1,

LCD Driver Output impedance

2. Refer to the supply current specifications I

LCD =

VLCDx = 1000, I

for additional current specificat ions with the LCD_A module active.

(LPM3)

LOAD =

10 A

3. Connecting an actual display will increase the current consumption depending on the size of the LCD.

MIN TYP MAX UNIT

2.2 3.6 V

4.7 F

2.2 V 3.8 A

2.2 V 10 k

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

SeeFigure15an

/CA

TA=25

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

Comparator_A (see Note 1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(CC)

(Refladder/RefDiode)

(Ref025)

(Ref050)

(RefVT)

Vp-- V

hys

(response LH and HL)

NOTES: 1. The leakage current for the Comparator_A terminals is identical to I

Voltage @ 0.25 VCCnode

Voltage @ 0.5 VCCnode

See Figure 15 and Figure 16

Common-mode input voltage range

Offset voltage SeeNote2 VCC = 2.2 V / 3 V -- 3 0 30 mV

Input hysteresis CAON = 1 VCC=2.2V/3V 0 0.7 1.4 mV

,seeNote3

2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The two successive measurements are then summed together.

3. The response time is measured at P1.6/CA0 with an input voltage step and the Comparator_A already enabled (CAON = 1). If CAON is set at the same time, a settling time of up to 300ns is added to the response time.

CAON = 1, CARSEL = 0, CAREF = 0

CAON = 1, CARSEL = 0, CAREF = 1/2/3, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 3, No load at P1.6 T

85C

CAON = 1 VCC=2.2V/3V 0 VCC-- 1 V

=25C,

Overdrive 10 mV, without filter: CAF = 0

T Overdrive 10 m V, with filter: CAF = 1

=25C

0 and P1.7/CA1,

VCC=2.2V 25 40

VCC=3V 45 60

VCC=2.2V 30 50

VCC=3V 45 80

VCC=2.2V/3V 0.23 0.24 0.25

VCC=2.2V/3V 0.47 0.48 0.5

VCC=2.2V 390 480 540

VCC=3V 400 490 550

VCC=2.2V 80 165 300

VCC=3V 70 120 240

VCC=2.2V 1.4 1.9 2.8

VCC=3V 0.9 1.5 2.2

specification.

lkg(Px.x)



s

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

(

)

(

)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

typical characteristics

REFERENCE VOLTAGE

FREE-AIR TEMPERATURE

650

VCC=3V

600

Typical

550

500

-- Reference Voltage -- mV

REF

450

400

-- 4 5 -- 2 5 -- 5 1 5 3 5 5 5 7 5 9 5

TA-- Free-Air Temperature -- C

Figure 15. V

V+

V--

vs Temperature

RefVT

+ _

CAON

REFERENCE VOLTAGE

FREE-AIR TEMPERATURE

650

VCC=2.2V

600

Typical

550

500

-- Reference Voltage -- mV

REF

450

400

-- 4 5 -- 2 5 -- 5 1 5 3 5 5 5 7 5 9 5

TA-- Free-Air Temperature -- C

Figure 16. V

CAF

Low-Pass Filter

vs Temperature

RefVT

To I n ternal Modules

CAOUT

Figure 17. Block Diagram of Comparator_A Module

Overdrive

V--

400 mV

V+

(response)

Figure 18. Overdrive Definition

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

2 s

CAOUT

Set CAIFG Flag

MSP430FG47x

SD16L

P=0

SD1

1MHz,

SD16OSR=256

Absoluteinput

Commonmod

Differentialinput

performance

(seeNote1

)

SD1

1MHz,

SD1

1MHz,

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

SD16_A, power supply and recommended operating conditions

SD16

PARAMETER TEST CONDITIONS V

Analog supply voltage

Analog supply current including internal reference

AVCC=DV

AVSS=DVSS=0V

SD16

=1MHz,

SD16OSR = 256

SD16LP = 1,

=0.5MHz,

SD16

SD16OSR = 256

SD16BUFx = 00, GAIN: 1,2 3V 750 1050

SD16BUFx = 00, GAIN: 4,8,16 3V 830 1150

SD16BUFx = 00, GAIN: 32 3V 1150 1700

SD16BUFx = 00, GAIN: 1 3V 730 1030

SD16BUFx = 00, GAIN: 32 3V 830 1150

SD16BUFx = 01, GAIN: 1 3V 850

SD16LP = 0,

SD16BUFx = 10, GAIN: 1 3V 1000

SD16BUFx = 11, GAIN: 1 3V 1130

Analog front-end

SD16LP = 0 (Low power mode disabled) 3V 0.03 1 1.1

input clock frequency

SD16LP = 1 (Low power mode enabled) 3V 0.03 0.5

MIN TYP MAX UNIT

2.5 3.6 V



MHz

SD16_A, input range

PARAMETER TEST CONDITIONS V

bsolute input

voltage range

Common-mode input voltage range

Differential full

ID,FSR

scale input voltage range

Differential input voltage range for

specified

(see Note 1)

Input impedance

(one input pin to AV

)

Differential input

impedance (IN+ to IN--)

NOTES: 1. The analog input range depends on the reference voltage applied to V

by V

FSR+

=+(V

SD16BUFx = 00 AV

SD16BUFx > 00

SD16BUFx = 00 AV

SD16BUFx > 00

Bipolar mode, SD16UNI = 0 -- V

Unipolar mode, SD16UNI = 1

SD16GAINx = 1 500

SD16GAINx = 2 250

SD16REFON = 1

SD16GAINx = 4 125

SD16GAINx = 8 62

SD16GAINx = 16 31

SD16GAINx = 32 15

SD16

SD16BUFx = 00

SD16

SD16BUFx = 01

SD16

SD16BUFx = 00

SD16

SD16BUFx > 00

/2)/GAIN and V

REF

=1MHz,

SD16GAINx = 1 3V 200

SD16GAINx = 32 3V 75

SD16GAINx = 1 3V 10 M

SD16GAINx = 1 3V 300 400

SD16GAINx = 32 3V 100 150

SD16GAINx = 1 3V 10 M

FSR--

=--(V

/2)/GAIN. The analog input range should not exceed 80% of V

REF

MIN TYP MAX UNIT

-0.1V AV

AVSS+0.2V AVCC-- 1 . 2 V

-0.1V AV

AVSS+0.2V AVCC-- 1 . 2 V

/2GAIN +V

REF

0 +V

.IfV

is sourced externally,the full-scale range is defined

REF

/2GAIN mV

REF

/2GAIN mV

REF

FSR+

or V

k

FSR--

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

distortionratio

Signaltonoise

=50Hz

ppm

Commonmod

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

SD16_A, performance (f

PARAMETER TEST CONDITIONS V

SINAD

dG/dT

dG/dV

NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85C -- (--40_C))

Signal-to-noise + distortion ratio

Nominal gain SD16GAINx = 1, SD16OSRx = 1024 3V 0.97 1.00 1.02

Gain temperature drift

Gain supply voltage drift

2. Calculated using the box method: (MAX(2.5...3.6V) -- MIN(2.5...3.6V))/MIN(2.5...3.6V)/(3.6V -- 2.5 V)

SD16_A, performance (f

PARAMETER TEST CONDITIONS V

SINAD

CMRR

PSRR

NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C)) / MIN(--40...85_C) / (85_C--(--40_C))

Signal-to-noise + distortion ratio

Nominal gain

set error

Offset error temperature coefficient

Common-mode rejection ratio

Power supply rejection ratio

2. Calculated using the ADC output code and the box method: (MAX-code(2.5...3.6V) -- MIN-code(2.5...3.6V)) / MIN-code(2.5...3.6V) / (3.6V -- 2.5 V)

= 30kHz, SD16REFON = 1, SD16BUFx = 01)

SD16

MIN TYP MAX UNIT

SD16GAINx = 1,Signal Amplitude = 500mV SD16OSRx = 256

SD16GAINx = 1,Signal Amplitude = 500mV SD16OSRx = 512

SD16GAINx = 1,Signal Amplitude = 500mV SD16OSRx = 1024

SD16GAINx = 1, SD16OSRx = 1024 (see Note 1) 3V 15 ppm/_C

SD16GAINx = 1, SD16OSRx = 1024, VCC= 2.5 V to 3.6 V (see Note 2)

= 1MHz, SD16OSRx = 256, SD16REFON = 1, SD16BUFx = 00)

SD16

SD16GAINx = 1,Signal Amplitude = 500mV 3V 83.5 85

SD16GAINx = 2,Signal Amplitude = 250mV 3V 81.5 84

SD16GAINx = 4,Signal Amplitude = 125mV

SD16GAINx = 8,Signal Amplitude = 62mV

SD16GAINx = 16,Signal Amplitude = 31mV 3V 69 73

SD16GAINx = 32,Signal Amplitude = 15mV 3V 62 69

SD16GAINx = 1 3V 0.97 1.00 1.02

SD16GAINx = 2 3V 1.90 1.96 2.02

SD16GAINx = 4 3V 3.76 3.86 3.96

SD16GAINx = 8

SD16GAINx = 16 3V 14.56 15.04 15.52

SD16GAINx = 32 3V 27.20 28.35 29.76

SD16GAINx = 1 3V 0.2

SD16GAINx = 32

SD16GAINx = 1 3V 4 20

SD16GAINx = 32

SD16GAINx = 1, Common-mode input signal: V

= 500 mV, fIN= 50 Hz, 100 Hz

SD16GAINx = 32, Common-mode input signal: V

=16mV,fIN= 50 Hz, 100 Hz

SD16GAINx = 1 3V 80 dB

fIN=2.8Hz

= 50Hz,

100Hz

3V 84

0.35 %/V

MIN TYP MAX UNIT

3V 76 79.5

3V 73 76.5

3V 7.36 7.62 7.84

3V 1.5

3V 20 100

3V 90

3V 75

%FSR

FSR/_C

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

Senso

(

)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

SD16_A, linearity (f

PARAMETER TEST CONDITIONS V

INL Integral non-linearity

= 1MHz, SD16REFON = 1, SD16BUFx = 00)

SD16

SD16OSR = 256, SD16GAINx = 000b, Signal Amplitude = 500 mV

SD16OSR = 256, SD16GAINx = 101b, Signal Amplitude = 15 mV

SD16OSR = 1024, SD16GAINx = 000b, Signal Amplitude = 500 mV

SD16OSR = 1024, SD16GAINx = 101b, Signal Amplitude = 15 mV

typical characteristics -- SD16_A SINAD performance over OSR

100.0

95.0

90.0

85.0

80.0

75.0

70.0

SINAD -- dB

65.0

MIN TYP MAX UNIT

3V 1.5

3V 6

3V 0.8

3V 3.5

LSB

60.0

55.0

50.0

10.00 100.00 1000.00

Figure 19. SINAD performance over OSR, f

SD16_A, temperature sensor and built-in V

PARAMETER TEST CONDITIONS V

Sensor

Offset,sensor

Sensor

CC,Sense

NOTES: 1. Not production tested, limits characterized.

Sensor temperature coefficient

Sensor offset voltage SeeNote1 --100 100 mV

Sensor output voltage

seeNote

VCCdivider at input 5 f

2. The following formula can be used to calculate the temperature sensor output voltage: V

Sensor,typ

3. Results based on characterization and/or production test, not TC

=TC

Sensor

SeeNote1 1.18 1.32 1.46 mV/K

Temperature sensor voltage at TA=85C 3V 435 475 515

Temperature sensor voltage at TA=25C 3V 355 395 435

Temperature sensor voltage at TA=0C(seeNote1) 3V 320 360 400

= 32kHz, SD16OSRx = 256, SD16REFON = 1 0.08 1/11 0.1 V

SD16

( 273 + T [C] ) + V

sense

Offset,sensor

OSR

= 1MHz, SD16REFON = 1, SD16GAINx = 1

SD16

MIN TYP MAX UNIT

[mV]

Sensor

or V

Offset,sensor

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

SD16_A, built -in voltage reference

PARAMETER TEST CONDITIONS V

REF

Internal reference voltage

Reference supply current

SD16REFON = 1, SD16VMIDON = 0 3V 1.14 1.20 1.26 V

SD16REFON = 1, SD16VMIDON = 0 3V 175 260 A

TC Temperature coefficient SD16REFON = 1, SD16VMIDON = 0 (see Note 1) 3V 18 50 ppm/K

REF

LOAD

load capacitance SD16REFON = 1, SD16VMIDON = 0 (see Note 2) 100 nF

REF

maximum load

REF(I)

current

Turn on time

SD16REFON = 1, SD16VMIDON = 0 3V 200 nA

SD16REFON = 0-->1, SD16VMIDON = 0, C

= 100nF

REF

3V 5 ms

PSRR Line regulation SD16REFON = 1, SD16VMIDON = 0 3V 100 uV/V

NOTES: 1. Calculated using the box method: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85C -- (--40_C))

2. There is no capacitance required on V

. However, a capacitance of at l east 100nF is recommended to reduce any reference

REF

voltage noise.

MIN TYP MAX UNIT

SD16_A, reference output buffer

PARAMETER TEST CONDITIONS V

REF,BUF

Reference buffer output voltage

Reference Supply +

REF,BUF

Reference output buffer quiescent current

REF(O)

LOAD,Max

Required load capacitance on V

REF

Maximum load current on V

REF

Maximum voltage variation vs load current

Turn on time

SD16_A, external reference input

PARAMETER TEST CONDITIONS V

REF(I)

Input voltage range SD16REFON = 0 3V 1.0 1.25 1.5 V

Input current SD16REFON = 0 3V 50 nA

MIN TYP MAX UNIT

SD16REFON = 1, SD16VMIDON = 1 3V 1.2 V

SD16REFON = 1, SD16VMIDON = 1 3V 385 600 A

SD16REFON = 1, SD16VMIDON = 1 470 nF

SD16REFON = 1, SD16VMIDON = 1 3V 1 mA

|=0to1mA 3V -- 1 5 +15 mV

LOAD

SD16REFON = 0-->1, SD16VMIDON = 1, C

= 470nF

REF

3V 100 s

MIN TYP MAX UNIT

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

Supplycurrent

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

12-bit DAC, supply specifications

PSRR

PARAMETER TEST CONDITIONS V

Analog supply voltage

CC =DVCC

=DVSS=0V

DAC12AMPx = 2, DAC12IR = 0, DAC12_xDAT = 0800h

DAC12AMPx = 2, DAC12IR = 1,

Supply current (see Notes 1 and 2)

DAC12_xDAT = 0800h, V

REF,DAC12 =AVCC

DAC12AMPx = 5, DAC12IR = 1, DAC12_xDAT = 0800h, V

REF,DAC12 =AVCC

DAC12AMPx = 7, DAC12IR = 1,

Power supply rejection ratio (see Notes 3 and 4)

DAC12_xDAT = 0800h, V

DAC12_xDAT = 800h, V AV

= 100 mV

REF,DAC12 =AVCC

REF,DAC12

=1.2V,

2.2 V/3 V 50 110

2.2 V/3 V 200 440

2.2 V/3 V 700 1500

2.7 V 70 dB

NOTES: 1. No load at the output pin assuming that the control bits for the shared pins are set properly.

2. Current into reference terminals not included. If DAC12IR = 1 current flows through the input divider; see Reference Input specifications.

3. PSRR = 20*logAV

4. V

is applied externally. The internal reference is not used.

REF

/V

DAC12_xOUT

MIN TYP MAX UNIT

2.20 3.60 V



POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

Differentialnonlinearit

Offset_Ca

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

12-bit DAC, linearity specifications (see Figure 20)

INL

DNL

E(O)/dT

E(G)/dT

Offset Cal

PARAMETER TEST CONDITIONS V

Integral nonlinearity (see Note 1)

Differential nonlinearity

(see Note 1)

REF,DAC12

=1.2VorV

REF,ext

DAC12AMPx = 7, DAC12IR = 1

REF,ext

=1.2V

DAC12AMPx = 7, DAC12IR = 1

REF,ext

=2.5V

DAC12AMPx = 7, DAC12IR = 1

Differential nonlinearity (see Note 1)

Offset voltage without calibration (see Notes 1, 2)

Offset voltage with calibration (see Notes 1, 2)

REF,DAC12

=1.2V

DAC12AMPx = 7, DAC12IR = 1

REF,DAC12

=1.2V

DAC12AMPx = 7, DAC12IR = 1

REF,DAC12

=1.2V

DAC12AMPx = 7, DAC12IR = 1

Offset error temperature coefficient (see Note 1)

Gainerror(seeNote1) V

REF,DAC12

=1.2V 2.7 V 3.50 %FSR

Gain temperature coefficient (see Note 1)

Timefor o (see Note 3)

set calibration

DAC12AMPx = 2 2.7 V 100

DAC12AMPx = 3,5 2.7 V 32

DAC12AMPx = 4,6,7 2.7 V 6

2.7 V 2.0 8.0 LSB

2.7 V -- 1 0.4 +1.3 LSB

2.7 V 0.4 1.0 LSB

2.7 V 20

2.7 V 2.5

2.7 V 30 V/C

2.7 V 10

NOTES: 1. Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients “a” and

“b” of the first order equation: y = a + b*x. V

DAC12_xOUT=EO

+(1+EG)*(V

REF,DAC12

/4095) * DAC12_xDAT, DAC12IR = 1.

2. The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON

3. The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx = {0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may effect accuracy and is not recommended.

MIN TYP MAX UNIT

ppm of

FSR/C

DAC Output

Load

Figure 20. Linearity Test Load Conditions and Gain/Offset Definition

= 100pF

DAC V

OUT

R+

Offset Error

Positive

Negative

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

Ideal transfer function

Gain Error

DAC Code

MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

12-bit DAC, linearity specifications (continued)

TYPICAL INL ERROR

DIGITAL INPUT DATA

VCC=2.2V,V DAC12AMPx = 7

DAC12IR = 1

-- 1

REF

=1.2V

-- 2

INL -- Integral Nonlinearity Error -- LSB

-- 3

-- 4 0 512 1024 1536 2048 2560 3072 3584

DAC12_xDAT -- Digital Code

TYPICAL DNL ERROR

DIGITAL INPUT DATA

2.0

1.5

1.0

0.5

0.0

-- 0 . 5

-- 1 . 0

VCC=2.2V,V DAC12AMPx = 7 DAC12IR = 1

REF

=1.2V

4095

-- 1 . 5

DNL -- Differential Nonlinearity Error -- LSB

-- 2 . 0 0 512 1024 1536 2048 2560 3072 3584

4095

DAC12_xDAT -- Digital Code

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MaxDAC12loa

(seeFigure23)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

12-bit DAC, output specifications

PARAMETER TEST CONDITIONS V

No Load, V

REF,DAC12

=AVCC, DAC12_xDAT = 0h, DAC12IR = 1, DAC12AMPx = 7

No Load, V

Output voltage

range (see Note 1, Figure 23)

DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7

Load

DAC12_xDAT = 0h, DAC12IR = 1,

REF,DAC12

=3k,V

=AVCC,

REF,DAC12

=AVCC,

DAC12AMPx = 7

Load

=3k,V

REF,DAC12

=AVCC, DAC12_xDAT = 0FFFh, DAC12IR = 1, DAC12AMPx = 7

L(DAC12)

Max DAC12 load capacitance

Max DAC12 load current

Load

=3k,V

O/P(DAC12)

 0.3 V,

DAC12AMPx = 2, DAC12_xDAT = 0h

O/P(DAC12)

Output resistance (see Figure 23)

=3k,V

Load

O/P(DAC12)

DAC12_xDAT = 0FFFh

=3k,

Load

0.3V  V

O/P(DAC12)

 AVCC-- 0 . 3 V

 AVCC-- 0.3V

NOTES: 1. Data is valid after the offset calibration of the output amplifier.

Load

= 100pF

DAC12

Load

O/P(DAC12_x)

Figure 23. DAC12_x Output Resistance Tests

2.2 V/3 V 0 0.005

2.2 V/3 V AVCC--0.05 AV

2.2 V/3 V 0 0.1

2.2 V/3 V AVCC--0.13 AV

2.2 V/3 V 100 pF

2.2V -- 0 . 5 +0.5

3V -- 1 . 0 +1.0

2.2 V/3 V 150 250

2.2 V/3 V 1 4

O/P(DAC12_x)

Max

Min

MIN TYP MAX UNIT

0.3

AVCC--0.3V



OUT

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

Referenceinpu

(

)

(VREF

)

DAC12_xDAT=800h

Error

V(O

)

<0.5LS



)

S(FS)



)

DAC12_xDAT=

S(C-C

)

3F8h408h3F8



SRSlewRat

/s

Glitchenergy:fullscal

nVs

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

12-bit DAC, reference input specifications

REF

PARAMETER TEST CONDITIONS V

DAC12IR = 0 (see Notes 1 and 2) 2.2 V/3 V AVCC/3 AVCC+0.2

DAC12IR = 1 (see Notes 3 and 4)

DAC12IR = 0, SD16VMIDON = 1 (see Note 5)

DAC12IR = 1, SD16VMIDON = 1 2.2 V/3 V 40 48 56 k

REF

Reference input voltage range

Reference input resistance

2.2 V/3 V AVCCAVCC+0.2

2.2 V/3 V 20 M

NOTES: 1. For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).

2. The maximum voltage applied at reference input voltage terminal V

=[AVCC-- V

REF

3. For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AV

4. The maximum voltage applied at reference input voltage terminal V

=[AVCC-- V

REF

5. Characterized, not production tested

MIN TYP MAX UNIT

]/[3*(1+EG)].

E(O)

]/(1+EG).

E(O)

12-bit DAC, dynamic specifications (V

REF,DAC12

=AVCC, DAC12IR = 1) (see Figure 24 and Figure 25)

PARAMETER TEST CONDITIONS V

S(FS

S(C-C

DAC12 on-time

Settling time,full-scale 80h F7Fh 80h

Settling time, code to code

SR Slew Rate

Glitch energy: full-scale

NOTES: 1. R

Load

DAC12_xDAT = 800h, Error

(O)

(see Note 1, Figure 24)

DAC12_xDAT=

DAC12_xDAT= 3F8h 408h 3F8h BF8h C08h BF8h

C12_xDAT=

D 80h F7Fh 80h

DAC12_xDAT= 80h F7Fh 80h

and C

connected to AVSS(not AVCC/2) in Figure 24.

Load

< 0.5 LSB

DAC12AMPx = 0  {2,3,4} 2.2 V/3 V 60 120

DAC12AMPx = 0  {5, 6} 2.2 V/3 V 15 30

DAC12AMPx = 0  7 2.2 V/3 V 6 12

DAC12AMPx = 2 2.2 V/3 V 100 200

DAC12AMPx = 3,5 2.2 V/3 V 40 80

DAC12AMPx = 4,6,7 2.2 V/3 V 15 30

DAC12AMPx = 2 2.2 V/3 V 5

DAC12AMPx = 3,5 2.2 V/3 V 2

DAC12AMPx = 4,6,7 2.2 V/3 V 1

DAC12AMPx = 2 2.2 V/3 V 0.05 0.12

DAC12AMPx = 3,5 2.2 V/3 V 0.35 0.7

DAC12AMPx = 4,6,7 2.2 V/3 V 1.5 2.7

DAC12AMPx = 2 2.2 V/3 V 600

DAC12AMPx = 3,5 2.2 V/3 V 150

DAC12AMPx = 4,6,7 2.2 V/3 V 30

2. Slew rate applies to output voltage steps > = 200 mV.

Conversion 1 Conversion 2

OUT

Glitch

Energy

DAC Output

Load

=3k

= 100pF

O/P(DAC12.x)

Load

+/-- 1/2 LSB

MIN TYP MAX UNIT

s

V/s

nV-s

Conversion 3

+/-- 1/2 LSB

Figure 24. Settling Time and Glitch Energy Testing

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

settleLH

settleHL

MSP430FG47x

3dBbandwidt

ACP

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

Conversion 1 Conversion 2

OUT

90%

10%

Figure 25. Slew Rate Testing

12-bit DAC, dynamic specifications continued (T

PARAMETER TEST CONDITIONS V

DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h

DAC12AMPx = {5, 6}, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h

DAC12AMPx = 7, DAC12SREFx = 2, DAC12IR = 1, DAC12_xDAT = 800h

= 100 pF

--3dB

NOTES: 1. R

3-dB bandwidth, V

=1.5V,

=0.1V

(see Figure 26)

LOAD

=3k,C

LOAD

Conversion 3

90%

10%

SRLH

=25C unless otherwise noted)

SRHL

2.2 V/3 V 40

2.2 V/3 V 180

2.2 V/3 V 550

MIN MAX UNIT

kHz

=3k

Load

DACx

Load

= 100pF

REF+

DAC12_x

Figure 26. Test Conditions for 3-dB Bandwidth Specification

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

Supplycurrent(seeNote1)

2.2V/3V



Inputleakagecurrent

/3V

(I/P)

V(I/P

)

1kH

(I/P)

V(I/P

)

10kHz

/3V

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

operational amplifier OA, supply specifications

PARAMETER TEST CONDITIONS V

Supply voltage range 2.2 3.6 V

Fast Mode 180 290

Supply current (see Note 1)

Medium Mode

2.2 V/3 V

Slow Mode

PSRR Power supply rejection ratio Non-inverting 2.2 V/3 V 70 dB

NOTES: 1. Corresponding pins configured as OA inputs and outputs respectively.

operational amplifier OA, input/output specification

PARAMETER TEST CONDITIONS V

I/P

Ikg

Input voltage range -- 0 . 1 VCC-- 1 . 2 V

Input leakage current (see Notes 1 and 2)

TA=--40to+55_C

=+55to+85_C

Fast Mode 50

Medium Mode

Voltage noise density, I/P

Slow Mode

Fast Mode

Medium Mode

=1kHz

=10kHz

Slow Mode

Offset voltage, I/P 2.2 V/3 V 10 mV

Offset temperature drift, I/P seeNote3 2.2 V/3 V 10 V/C

Offset voltage drift with supply, I/P

High-level output voltage, O/P

Low-level output voltage, O/P

0.3 V  VIN VCC-- 1 . 0 V

V

10%, TA=25C

Fast Mode, I

Slow Mode, I

Fast Mode, I

Slow Mode, I

SOURCE

 --500 A

 +500 A

 --150 A

 +150 A

CMRR Common-mode rejection ratio Noninverting 2.2 V/3 V 70 dB

NOTES: 1. ESD damage can degrade input current leakage.

2. The input bias current is overridden by the input leakage current.

3. Calculated using the box method

4. Specification valid for voltage-follower OAx configuration

2.2

2.2 V/3 V 1.5 mV/V

2.2

MIN TYP MAX UNIT

110 190

50 80

MIN TYP MAX UNIT

-- 5 0.5 5

-- 2 0 5 20

140

VCC-- 0 . 2 V

VCC-- 0 . 1 V

0.2

0.1

A

Hz

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

SRSlewrat

/s

(seeFigure27andFigure28

)

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

operational amplifier OA, dynamic specifications

PARAMETER TEST CONDITIONS V

SR Slew rate

Open-loop voltage gain 100 dB



GBW

en(on)

en(off)

Phase margin CL=50pF 60 deg

Gain margin CL=50pF 20 dB

Gain-bandwidth product (see Figure 27 and Figure 28)

Enable time on ton, Noninverting, Gain = 1 2.2 V/3 V 10 20 s

Enable time off 2.2 V/3 V 1 s

Fast Mode 1.2

Medium Mode

Slow Mode 0.3

Noninverting, Fast Mode, R

=47k,CL=50pF

Noninverting, Medium Mode, R

= 300 k,CL= 50pF

Non-inverting, Slow Mode, R

= 300 k,CL= 50pF

2.2 V/3 V

MIN TYP MAX UNIT

0.8

2.2

1.4

0.5

V/s

MHz

TYPICAL OPEN-LOOP GAIN vs FREQUENC

140

120

100

Gain -- dB

-- 2 0

-- 4 0

-- 6 0

-- 8 0

Fast Mode

Medium Mode

Slow Mode

1 10 100 1000 10000 100000

Input Frequency -- kHz

Figure 27

TYPICALPHASE vs FREQUENC

-- 5 0

Fast Mode

--100

Medium Mode

--150

Phase -- degrees

Slow Mode

--200

--250 1 10 100 1000 10000 100000

Input Frequency -- kHz

Figure 28

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MSP430FG47x

Inputleakagecurrent

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted) (continued)

switches between OA terminals and pins

PARAMETER TEST CONDITIONS V

lkg

NOTES: 1. ESD damage can degrade input current leakage.

Supply voltage range -- 2.2 3.6 V

Input leakage current (see Note 1)

Input current Input switched to ON 0 100 A

On resistance IIN= 100 A 1 k

TA=--40Cto55C 1 10

=55Cto85C 50

typical characteristics

MIN TYP MAX UNIT

RONvs V

3000.0

2750.0

2500.0

2250.0

2000.0

1750.0

1500.0

1250.0

1000.0

750.0

500.0

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6

Typical

-- Common Mode Input Voltage (V)

COM

TA=25C

VCC=2.2V

VCC=2.7V

VCC=3V

Figure 29

VCC=3.6V

RONvs V

1700.0

1600.0

1500.0

1400.0

1300.0

1200.0

1100.0

1000.0

900.0

800.0

0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6

Typical

TA=85C

TA=25C

TA=--40C

-- Common Mode Input Voltage (V)

COM

VCC=3V

Figure 30

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended operating free-air temperature (unless otherwise noted)

Timer_A

TA, cap

Timer_B

TB,cap

PARAMETER TEST CONDITIONS V

Timer

Timer_A, capture timing TA0, TA1, TA 2 2.2 V/3 V 20 ns

Timer_Bclockfrequency

Timer_B, capture timing TB0, TB1, TB2 2.2 V/3 V 20 ns

clockfrequency

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK, E

ternal: TACLK, INCLK,

Duty cycle = 50% 10%

Internal: SMCLK, ACLK, E

ternal: TBCLK,

Duty cycle = 50% 10%

2.2 V 8

3V 10

2.2 V 8

3V 10

MIN MAX UNIT

MHz

MIN MAX UNIT

MHz

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

UARTreceivedeglitchtime

UCLKedgetoSOMIvalid

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

USCI (UART mode)

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI

USCI input clock frequency

External: UCLK Duty cycle = 50%  10%

Maximum BITCLK clock frequency

fmax,

BITCLK

(equals baudrate in MBaud) (see Note 1)



UART receive deglitch time (see Note NO TAG)

NOTES: 1. The DCO wake-up time must be considered in LPM3/4 for baudrates above 1 MHz.

2. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed.

USCI (SPI master mode) (see Figure 31 and Figure 32)

PARAMETER TEST CONDITIONS V

USCI

SU,MI

HD,MI

VAL ID, MO

NOTE: f

USCI input clock frequency

SOMI input data s etup time

SOMI input data hold time

SIMO output data valid time UCLK edge to SIMO valid, CL=20pF

UCxCLK

with t

LO∕HI

For the slave’s parameters t

≥ max(t

LO∕HI

SU,SI(Slave)

and t

SMCLK, ACLKm Duty cycle = 50%  10%

VALID,MO(USCI)

VALID,SO(Slave)

+ t

SU,SI(Slave),tSU,MI(USCI)

+ t

refer to the SPI parameters of the attached slave.

2.2V /3 V 2 MHz

2.2 V 50 150 ns

3V 50 100 ns

VALID,SO(Slave)

MIN TYP MAX UNIT

SYSTEM

MIN MAX UNIT

SYSTEM

MHz

2.2 V 110 ns

3V 75 ns

2.2 V 0 ns

3V 0 ns

2.2 V 30 ns

3V 20 ns

USCI (SPI slave mode) (see Figure 33 and Figure 34)

PARAMETER TEST CONDITIONS V

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

SU,SI

HD,SI

VAL ID, SO

NOTE: f

For the master’s parameters t

STE lead time STE low to clock

STE lag time Last clock to STE high

STE access time STE low to SOMI data out

STE disable time STE high to SOMI high impedance

SIMO input data setup time

SIMO input data hold time

SOMI output data valid time

UCxCLK

LO∕HI

with t

LO∕HI

≥ max(t

SU,MI(Master)

UCLK edgetoSOMIvalid, C

=20pF

VALID,MO(Master)

and t

VALID,MO(Master)

+ t

MIN TYP MAX UNIT

2.2 V/3 V 50 ns

2.2 V/3 V 10 ns

2.2 V/3 V 50 ns

2.2 V 20 ns

3V 15 ns

2.2 V 10 ns

3V 10 ns

2.2 V 75 110 ns

3V 50 75 ns

SU,SI(USCI),tSU,MI(Master)

+ t

VALID,SO(USCI)

refer to the SPI parameters of the attached master.

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

1/f

UCxCLK

CKPL=0

UCLK

CKPL=1

SOMI

SIMO

UCLK

SOMI

CKPL=0

CKPL=1

LO/HItLO/HI

VAL I D,MO

SU,MI

HD,MI

Figure 31. SPI Master Mode, CKPH = 0

1/f

UCxCLK

LO/HItLO/HI

SU,MI

VAL I D,MO

HD,MI

SIMO

Figure 32. SPI Master Mode, CKPH = 1

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

STE

UCLK

SIMO

SOMI

STE

CKPL=0

CKPL=1

STE,ACC

STE,LEAD

1/f

UCxCLK

LO/HItLO/HI

VAL I D,SO

Figure 33. SPI Slave Mode, CKPH = 0

STE,LEAD

SU,SI

HD,SI

STE,LAG

STE,DIS

UCLK

SIMO

SOMI

CKPL=0

CKPL=1

STE,ACC

1/f

UCxCLK

LO/HItLO/HI

SU,SI

VAL I D,SO

Figure 34. SPI Slave Mode, CKPH = 1

HD,SI

STE,DIS

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MSP430FG47x

Pulsewidthofspikessuppressedb

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

USCI (I2C mode) (see Figure 35)

USCI

SCL

HD,STA

SU,STA

HD,DAT

SU,DAT

SU,STO

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI input clock frequency

External: UCLK Duty cycle = 50%  10%

SCL clock frequency 2.2 V/3 V 0 400 kHz

 100kHz 2.2 V/3 V 4.0 s

Hold time (repeated) START

Setup timefor a repeated START

SCL

> 100kHz 2.2 V/3 V 0.6 s

SCL

 100kHz 2.2 V/3 V 4.7 s

SCL

> 100kHz 2.2 V/3 V 0.6 s

SCL

Data hold time 2.2 V/3 V 0 ns

Data setup time 2.2 V/3 V 250 ns

SetuptimeforSTOP 2.2 V/3 V 4.0 s

Pulse width ofspikes su input filter

ressed b

2.2 V 50 150 600 ns

3V 50 100 600 ns

MIN TYP MAX UNIT

SYSTEM

MHz

SDA

SCL

HD,STA

1/f

SCL

HD,DAT

SU,STAtHD,STA

SU,DAT

Figure 35. I2C Mode Timing

SU,STO

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MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued)

flash memory

PARAMETER

CC(PGM/

ERASE)

FTG

PGM

ERASE

CPT

CMErase

Program and Erase s upply v oltage 2.2 3.6 V

Flash Timing Generator frequency 257 476 kHz

Supply current from DVCCduring program 2.5 V/3.6V 3 5 mA

Supply current from DVCCduring erase 2.5 V/3.6V 3 7 mA

Cumulative program time seeNote1 2.5 V/3.6V 10 ms

Cumulative mass erase time seeNote2 2.5 V/3.6V 200 ms

Program/Erase endurance 10

Retention

Word

Block, 0

Block, 1-63

Block, End

Mass Erase

Seg Erase

Data retention duration TJ=25C 100 years

Word or byte program time 35

Block program time for 1stbyte or word 30

Block program time for each additional byte or word

Block program end-sequence wait time

Mass erase time 5297

Segment erase time 4819

NOTES: 1. The cumulative program time must not be exceeded when writing to a 64--byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

2. The mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f achieve the required cumulative mass erase time the Flash Controller’s mass erase operation can be repeated until this time is met. (A worst case minimum of 19 cycles are required).

3. These values are hardwired into the Flash Controller’s state machine (t

TEST

CONDITIONS

seeNote3

FTG

=1/f

FTG

MIN TYP MAX UNIT

FTG

cycles

FTG

,max = 5297x1/476kHz). To

JTAG interface

TEST

CONDITIONS

MIN TYP MAX UNIT

2.2 V 0 5 MHz

3V 0 10 MHz

TCK

Internal

NOTES: 1. f

2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.

PARAMETER

TCK inputfrequency See Note 1

Internal pull-up resistance on TMS, TCK, TDI/TCLK SeeNote2 2.2 V/ 3 V 25 60 90 k

may be restricted to meet the timing requirements of the module selected.

TCK

JTAG fuse (see Note 1)

PARAMETER

CC(FB)

Supply voltage during fuse-blow condition TA=25C 2.5 V

Voltage level on TDI/TCLK for fuse-blow: F versions 6 7 V

Supply current into TDI/TCLK during fuse blow 100 mA

Time to blow fuse 1 ms

NOTES: 1. Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched

to bypass mode.

TEST

CONDITIONS

MIN MAX UNIT

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APPLICATION INFORMATION

Port P1 pin schematic: P1.0, input/output with Schmitt trigger

CAPD.0

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

P1DIR.0

P1SEL2.0

Module X OUT

P1OUT.0

P1SEL.0

P1IN.0

Module X IN

P1IRQ.0

P1IFG.0

P1SEL.0

P1IES.0

P1IE.0

Set

Interrupt

Edge Select

Direction 0: Input 1: Output

Bus

Keeper

Pad Logic

P1.0/TA0/OA0RFB

SWCTL1.SWCTL8

OA0

Port P1 (P1.0) pin functions

PIN NAME (P1.X)

P1.0/TA0/OA0RFB 0

P1.x (I/O) 0 I: 0, O: 1 0 0

Timer_A3.CCI0A 0 0 1 0

Timer_A3.TA0 0 1 1 0

OA0RFB x x 1 1

FUNCTION

CONTROL BITS / SIGNALS

CAPD.x P1DIR.x P1SEL.x P1SEL2.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P1 pin schematic: P1.1, input/output with Schmitt trigger

CAPD.1

P1DIR.1

P1SEL2.1

Module X OUT

MCLK

P1OUT.1

P1SEL.1

P1IN.1

Module X IN

P1IRQ.1

P1SEL.1

P1IES.1

P1IE.1

P1IFG.1

Set

Interrupt

Edge Select

Direction 0: Input 1: Output

Bus

Keeper

Pad Logic

P1.1/TA0/MCLK/ OA1RFB

SWCTL1.SWCTL12

OA1

Port P1 (P1.1) pin functions

PIN NAME (P1.X)

P1.1/TA0/MCLK 1 OA1RFB

P1.x (I/O) 0 I: 0, O: 1 0 0

Timer_A3.CCI0A 0 0 1 0

Timer_A3.TA0 0 1 1 0

OA1RFB x 0 1 1

MCLK 0 1 1 1

FUNCTION

CONTROL BITS / SIGNALS

CAPD.x P1DIR.x P1SEL.x P1SEL2.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

///

Port P1 pin schematic: P1.2 input/output with Schmitt trigger

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

INCH

A4-

SD16AE.2

CAPD.2

P1DIR.2

P1OUT.2

Module X OUT

P1SEL.2

P1IN.2

Module X IN

P1IRQ.2

Pad Logic

P1IE.2

P1IFG.2

Direction 0: Input 1: Output

Set

P1.2/TA1/A4-/OA0I3

Bus

Keeper

OA0

P1SEL.2

P1IES.2

Port P1 (P1.2) pin functions

PIN NAME (P1.X)

P1.2/TA1/A4--/OA0I3 2

NOTES: 1. x: Don’t care.

X FUNCTION

P1.x (I/O) 0 I: 0, O: 1 0 xx 0

Timer_A3.CCI1A 0 0 1 xx 0

Timer_A3.TA1 0 1 1 xx 0

A4-- x x x xx 1

OA0I3 x x x 10 1

Interrupt

Edge Select

CONTROL BITS / SIGNALS

CAPD.x P1DIR.x P1SEL.x

P1SEL2.x = 0

OAN (OA0)

P1SEL2.x = 0

SD16AE.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P1 pin schematic: P1.3, input/output with Schmitt trigger

INCH =4

A4+

SD16AE.3

CAPD.3

P1DIR.3

P1OUT.3

Module X OUT

P1SEL.3

P1IN.3

Module X IN

P1IRQ.3

Pad Logic

P1IE.3

P1IFG.3

Set

Direction 0: Input 1: Output

Bus

Keeper

P1.3/TBOUTH/ SVSOUT/A4+/OA1I3

OA1

P1SEL.3

P1IES.3

Port P1 (P1.3) pin functions

PIN NAME (P1.X)

P1.3/TBOUTH/ 3 SVSOUT/A4+/OA1I3

NOTES: 1. x: Don’t care.

X FUNCTION

P1.x (I/O) 0 I: 0, O: 1 0 xx 0

TBOUTH 0 0 1 xx 0

SVSOUT 0 1 1 xx 0

A4+ x x x xx 1

OA1I3 x x x 10 1

Interrupt

Edge Select

CONTROL BITS / SIGNALS

CAPD.x P1DIR.x P1SEL.x

P1SEL2.x = 0

OAN (OA1)

P1SEL2.x = 0

SD16AE.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P1 pin schematic: P1.4, input/output with Schmitt trigger

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

DAC12_1OUT

DAC12OPS

INCH=3

A3-

SD16AE.4

CAPD.4

P1DIR.4

P1OUT.4

Module X OUT

P1SEL.4

P1IN.4

Module X IN

P1IRQ.4

Pad Logic

01DV

Direction 0: Input 1: Output

P1IE.4

P1IFG.4

P1.4/TBCLK/

Bus

Keeper

Set

OA1

SMCLK/A3-/ OA1I0/DAC1

P1SEL.4

P1IES.4

Port P1 (P1.4) pin functions

PIN NAME (P1.X)

P1.4TBCLK/SMCLK/ 4 A3--/OA1I0/DAC1

NOTES: 1. x: Don’t care.

X FUNCTION

P1.x (I/O) I: 0, O: 1 0 0 xx 0

TBCLK 0 1 0 xx 0

SMCLK 1 1 0 xx 0

A3-- x x 1 xx 0

OA1I0 x x 1 00 0

DAC1 x x x xx 1

Interrupt

Edge Select

CONTROL BITS / SIGNALS

CAPD.x P1DIR.x P1SEL.x

P1SEL2.x = 0

SD16AE.x

P1SEL2.x = 0

OAP (OA1)

P1SEL2.x = 0

DAC12OPS

(DAC12_1)

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

///

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P1 pin schematic: P1.5, input/output with Schmitt trigger

INCH =3

Ax+

SD16AE.5

CAPD.5

P1DIR.5

P1OUT.5

Module X OUT

P1SEL.5

P1IN.5

Module X IN

P1IRQ.5

P1SEL.5

P1IES.5

P1IE.5

P1IFG.5

Pad Logic

Direction 0: Input 1: Output

P1.5/TACLK/ACLK/A3+

Bus

Keeper

Set

Interrupt

Edge Select

Port P1 (P1.5) pin functions

PIN NAME (P1.X)

P1.5/TACLK/ACLK/ 5 A3+

NOTES: 1. x: Don’t care.

X FUNCTION

P1.x (I/O) 0 I: 0, O: 1 0 0

TAC L K 0 0 1 0

ACLK 0 1 1 0

A3+ x x x 1

CAPD.x P1DIR.x P1SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

CONTROL BITS / SIGNALS

P1SEL2.x = 0

SD16AE.x

APPLICATION INFORMATION

Port P1 pin schematic: P1.6, input/output with Schmitt trigger

To Comparator_A

From Comparator_A

CAPD.6

DAC12_0OUT

DAC12OPS

A2-

INCH=2

SD16AE.6

P1DIR.6

Direction 0: Input 1: Output

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Pad Logic

P1OUT.6

0/1

P1SEL.6

P1IN.6

Module X IN

P1IRQ.6

P1SEL.6

P1IES.6

P1IE.6

P1IFG.6

Set

Interrupt

Edge Select

Bus

Keeper

P1.6/CA0/A2-/ OA0I0/DAC0

OA0

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

///

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Port P1 (P1.6) pin functions

PIN NAME (P1.X)

P1.6/CA0/A2--/OA0I0/ 6 DAC0

NOTES: 1. x: Don’t care.

X FUNCTION

P1.x (I/O) I: 0, O: 1 0 0 0 xx 0

CA0 x x 1 or selected x xx x

A2-- x x x 1 xx x

OA0I0 x x x x 00 x

DAC0 x x x x xx 1

P1DIR.x P1SEL.x

CONTROL BITS / SIGNALS

P1SEL2.x = 0

CAPD.x

P1SEL2.x = 0

SD16AE.x

P1SEL2.x = 0

OAP (OA0)

P1SEL2.x = 0

DAC12OPS

(DAC12_0)

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P1 pin schematic: P1.7, input/output with Schmitt trigger

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

To Comparator_A

From Comparator_A

CAPD.7

SD16AE.7

INCH=2

A2+

P1DIR.7

P1OUT.7

0/1

P1SEL.7

P1IN.7

Module X IN

Pad Logic

Direction 0: Input 1: Output

P1.7/CA1/A2+

Bus

Keeper

P1IRQ.7

P1IFG.7

P1SEL.7

P1IES.7

Port P1 (P1.7) pin functions

PIN NAME (P1.X)

P1.7/CA1/A2+ 7

NOTES: 1. x: Don’t care.

X FUNCTION

P1.x (I/O) I: 0, O: 1 0 0 0

CA1 x x 1 or selected x

A2+ x x x 1

P1IE.7

Set

Interrupt

Edge Select

CONTROL BITS / SIGNALS

P1DIR.x P1SEL.x

P1SEL2.x = 0

CAPD.x

P1SEL2.x = 0

SD16AE.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P2 pin schematic: P2.0 to P2.1, input/output with Schmitt trigger

LCDS0

Segment Sx

P2DIR.x

P2OUT.x

Module X OUT

P2SEL.x

P2IN.x

Module X IN

P2IRQ.x

P2IFG.x

P2SEL.x

P2IES.x

P2IE.x

Set

Interrupt

Edge Select

Direction 0: Input 1: Output

Bus

Keeper

Pad Logic

P2.0/TA2/S1 P2.1/TB0/S0

Port P2 (P2.0 to P2.1) pin functions

PIN NAME (P2.X)

P2.0/TA2/S1 0

P2.1/TB0/S0 1

NOTES: 1. x: Don’t care.

P2.x (I/O) I: 0, O: 1 0 0

Timer_A3.CCI2A 0 1 0

Timer_A3.TA2 1 1 0

S1 x x 1

P2.x (I/O) I: 0, O: 1 0 0

Timer_B3.CCI0A 0 1 0

Timer_B3.TB0 1 1 0

S0 x x 1

FUNCTION

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x LCDS0

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

APPLICATION INFORMATION

Port P2 pin schematic: P2.2 to P2.3, input/output with Schmitt trigger

MSP430FG47x

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

P2DIR.x

Module X OUT

P2OUT.x

P2SEL.x

P2IN.x

Module X IN

P2IRQ.x

P2IFG.x

P2SEL.x

P2IES.x

P2IE.x

Set

Interrupt

Edge Select

Direction 0: Input 1: Output

Pad Logic

P2.2/TB1 P2.3/TB2

Port P2 (P2.2 to P2.3) pin functions

PIN NAME (P2.X)

P2.2/TB1 2

P2.3/TB2 3

P2.x (I/O) I: 0, O: 1 0

Timer_B3.CCI1A 0 1

Timer_B3.TB1 1 1

P2.x (I/O) I: 0, O: 1 0

Timer_B3.CCI2A 0 1

TimerB3.TB2 1 1

FUNCTION

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P2 pin schematic: P2.4 and P2.5, input/output with Schmitt trigger

P2DIR.x

Module

direction

P2OUT.x

Module X OUT

P2SEL.x

P2IN.x

Module X IN

P2IRQ.x

P2SEL.x

P2IES.x

P2IE.x

P2IFG.x

Direction 0: Input 1: Output

Set

Interrupt

Edge Select

Port P2 (P2.4 and P2.5) pin functions

PIN NAME (P2.X)

P2.4/UCA0TXD/ 4 UCA0SIMO

P2.5/UCA0RXD/ 5 UCA0SOMI

NOTES: 1. x: Don’t care.

2. The pin direction is controlled by the USCI module.

P2.x (I/O) I: 0, O: 1 0

UCA0TXD/UCA0SIMO (see Notes 2) x 1

P2.x (I/O) I: 0, O: 1 0

UCA0RXD/UCA0SOMI (see Notes 2) x 1

FUNCTION

Pad Logic

P2.4/UCA0TXD/UCA0SIMO P2.5/UCA0RXD/UCA0SOMI

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

APPLICATION INFORMATION

Port P2 pin schematic: P2.6 and P2.7, inpututput with Schmitt trigger

MSP430FG47x

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

LCDS0

Segment Sy

P2DIR.x

P2OUT.x

0/1

P2SEL.x

P2IN.x

P2IRQ.x

P2SEL.x

P2IES.x

P2IE.x

P2IFG.x

Direction 0: Input 1: Output

Interrupt

Edge Select

Set

Bus

Keeper

Pad Logic

P2.6/CAOUT/S2 P2.7/S3

Port P2 (P2.6 and P2.7) pin functions

PIN NAME (P2.X)

P2.6/CAOUT/S2 6

P2.7/S3 7

NOTES: 1. x: Don’t care.

P2.x (I/O) I: 0, O: 1 0 0

CAOUT 1 1 0

S2 x x 1

P2.x (I/O) I: 0, O: 1 0 0

S3 x x 1

FUNCTION

CONTROL BITS / SIGNALS

P2DIR.x P2SEL.x LCDS0

1 1 0

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P3 pin schematic: P3.0 and P3.3, input/output with Schmitt trigger

P3DIR.x

Module

direction

P3OUT.x

Module X OUT

P3SEL.x

P3IN.x

Module X IN

Direction 0: Input 1: Output

Port P3 (P3.0 and P3.3) pin functions

PIN NAME (P3.X)

P3.0/UCB0STE/ 0 UCA0CLK

P3.3/UCB0CLK/ 3 UCA0STE

NOTES: 1. x: Don’t care.

2. The pin direction is controlled by the USCI module.

P3.x (I/O) I: 0, O: 1 0

UCB0STE/UCA0CLK (see Note 2) x 1

P3.x (I/O) I: 0, O: 1 0

UCB0CLK/UCA0STE (see Note 2) x 1

FUNCTION

Pad Logic

P3.0/UCB0STE/UCA0CLK P3.3/UCB0CLK/UCA0STE

CONTROL BITS / SIGNALS

P3DIR.x P3SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P3 pin schematic: P3.1 and P3.2, input/output with Schmitt trigger

MSP430FG47x

LCDS24

Segment Sy

P3DIR.x

Module

direction

P3OUT.x

Module X OUT

P3SEL.x

P3IN.x

Module X IN

Direction 0: Input 1: Output

Port P3 (P3.1 and P3.2) pin functions

PIN NAME (P3.X)

P3.1/UCB0SIMO/ 1 UCB0SDA/S26

P3.2/UCB00SOMI/ 2 UCB0SCL/S27

NOTES: 1. x: Don’t care.

2. The pin direction is controlled by the USCI module.

3. In case the I2C functionality is selected the output drives only the logical 0 to V

P3.x (I/O) I: 0, O: 1 0 0

UCB0SIMO/UCB0SDA (see Notes 2 and 3) x 1 0

S26 x x 1

P3.x (I/O) I: 0, O: 1 0 0

UCB0SOMI/UCB0SCL (see Notes 2 and 3) x 1 0

S27 x x 1

FUNCTION

Bus

Keeper

Pad Logic

P3.1/UCB0SIMO/UCB0SDA/S26 P3.2/UCB0SOMI/UCB0SCL/S27

CONTROL BITS / SIGNALS

P3DIR.x P3SEL.x LCDS24

level.

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P3 pin schematic: P3.4 to P3.7, input/output with Schmitt trigger

LCDS28

Segment Sy

P3DIR.x

P3OUT.x

Module X Out

P3SEL.x

P3IN.x

Direction 0: Input 1: Output

Port P3 (P3.4 to P3.7) pin functions

PIN NAME (P3.X)

P3.4/S28 4

P3.5/S29 5

P3.6/S30 6

P3.7/S31 7

NOTES: 1. x: Don’t care.

P3.x (I/O) I: 0, O: 1 0 0

S28 x x 1

P3.x (I/O) I: 0, O: 1 0 0

S29 x x 1

P3.x (I/O) I: 0, O: 1 0 0

S30 x x 1

P3.x (I/O) I: 0, O: 1 0 0

S31 x x 1

FUNCTION

Bus

Keeper

Pad Logic

P3.4/S28 P3.5/S29 P3.6/S30 P3.7/S31

CONTROL BITS / SIGNALS

P3DIR.x P3SEL.x LCDS28

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

APPLICATION INFORMATION

Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt trigger

MSP430FG47x

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

LCDS4/8

Segment Sy

P4DIR.x

P4OUT.x

0/1

P4SEL.x

P4IN .x

Direction 0: Input 1: Output

Port P4 (P4.0 and P4.7) pin functions

PIN NAME (P4.X)

P4.0/S11 0

P4.1/S10 1

P4.2/S9 2

P4.3/S8 3

P4.4/S7 4

P4.5/S6 5

P4.6/S5 6

P4.7/S4 7

NOTES: 1. x: Don’t care.

P4.x (I/O) I: 0, O: 1 0 0 (LCDS8)

S11 x x 1 (LCDS8)

P4.x (I/O) I: 0, O: 1 0 0 (LCDS8)

S10 x x 1 (LCDS8)

P4.x (I/O) I: 0, O: 1 0 0 (LCDS8)

S9 x x 1 (LCDS8)

P4.x (I/O) I: 0, O: 1 0 0 (LCDS8)

S8 x x 1 (LCDS8)

P4.x (I/O) I: 0, O: 1 0 0 (LCDS4)

S7 x x 1 (LCDS4)

P4.x (I/O) I: 0, O: 1 0 0 (LCDS4)

S6 x x 1 (LCDS4)

P4.x (I/O) I: 0, O: 1 0 0 (LCDS4)

S5 x x 1 (LCDS4)

P4.x (I/O) I: 0, O: 1 0 0 (LCDS4)

S4 x x 1 (LCDS4)

FUNCTION

Bus

Keeper

Pad Logic

P4.0/S11 P4.1/S10 P4.2/S9 P4.3/S8 P4.4/S7 P4.5/S6 P4.6/S5 P4.7/S4

CONTROL BITS / SIGNALS

P4DIR.x P4SEL.x LCDS4/8

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P5 pin schematic: P5.0 and P5.1, input/output with Schmitt trigger

LCDS20

Segment Sy

P5DIR.x

P5OUT.x

0/1

P5SEL.x

P5IN.x

Direction 0: Input 1: Output

Port P5 (P5.0 and P5.1) pin functions

PIN NAME (P5.X)

P5.0/S20 0

P5.1/S21 1

NOTES: 1. x: Don’t care.

P5.x (I/O) I: 0, O: 1 0 0

S20 x x 1

P5.x (I/O) I: 0, O: 1 0 0

S21 x x 1

FUNCTION

Bus

Keeper

Pad Logic

P5.0/S20 P5.1/S21

CONTROL BITS / SIGNALS

P5DIR.x P5SEL.x LCDS20

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

APPLICATION INFORMATION

Port P5 pin schematic: P5.2 to P5.7, input/output with Schmitt trigger

MSP430FG47x

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

LCD Signal

P5DIR.x

P5OUT.x

0/1

P5SEL.x

P5IN.x

Direction 0: Input 1: Output

Port P5 (P5.2 to P5.7) pin functions

PIN NAME (P5.X)

P5.2/COM1 2

P5.3/COM2 3

P5.4/COM3 4

P5.5/R23 5

P5.6/LCDREF/R13 6

P5.7/R03 7

NOTES: 1. x: Don’t care.

P5.x (I/O) I: 0, O: 1 0

COM1 x 1

P5.x (I/O) I: 0, O: 1 0

COM2 x 1

P5.x (I/O) I: 0, O: 1 0

COM3 x 1

P5.x (I/O) I: 0, O: 1 0

R23 x 1

P5.x (I/O) I: 0, O: 1 0

R13 or LCDREF x 1

P5.x (I/O) I: 0, O: 1 0

R03 x 1

FUNCTION

Bus

Keeper

Pad Logic

P5.2/COM1 P5.3/COM2 P5.4/COM3 P5.5/R23 P5.6/LCDREF/R13 P5.7/R03

CONTROL BITS / SIGNALS

P5DIR.x P5SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P6 pin schematic: P6.0 and P6.3, input/output with Schmitt trigger

INCH=y

Ay+

P6DIR.x

P6OUT.x

Module X OUT

P6SEL.x

P6IN.x

Direction 0: Input 1: Output

Port P6 (P6.0 and P6.3) pin functions

PIN NAME (P6.X)

P6.0/A0+/OA0O 0

P6.3/A1+/OA1O 3

NOTES: 1. x: Don’t care.

P6.x (I/O) I: 0, O: 1 0

A0+ x 1

OA0O x 1

P6.x (I/O) I: 0, O: 1 0

A1+ x 1

OA1O x 1

FUNCTION

Bus

Keeper

Pad Logic

P6.0/A0+/OA0O P6.3/A1+/OA1O

OAx

CONTROL BITS / SIGNALS

P6DIR.x P6SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P6 pin schematic: P6.1 and P6.4, input/output with Schmitt trigger

MSP430FG47x

Ay-

INCH=y

P6DIR.x

P6OUT.x

0/1

P6SEL.x

P6IN .x

Pad Logic

Direction 0: Input 1: Output

Bus

Keeper

P6.1/A0-/O A0FB P6.4/A1-/O A1FB

OAx

Port P6 (P6.1 and P6.4) pin functions

PIN NAME (P6.X)

P6.1/A0--/OA0FB 1

P6.4/A1--/OA1FB 4

NOTES: 1. x: Don’t care.

P6.x (I/O) I: 0, O: 1 0

A0-- x 1

OA0FB x 1

P6.x (I/O) I: 0, O: 1 0

A1-- x 1

OA1FB x 1

FUNCTION

CONTROL BITS / SIGNALS

P6DIR.x P6SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Port P6 pin schematic: P6.2, P6.5 and P6.6, input/output with Schmitt trigger

P6DIR.x

P6OUT.x

0/1

P6SEL.x

P6IN.x

Direction 0: Input 1: Output

Port P6 (P6.2, P6.5 and P6.6) pin functions

PIN NAME (P6.X)

P6.2/OA0I1 2

P6.5/OA0I2 5

P6.6/OA1I1 6

NOTES: 1. x: Don’t care.

P6.x (I/O) I: 0, O: 1 0

OA0I1 x 1

P6.x (I/O) I: 0, O: 1 0

OA0I2 x 1

P6.x (I/O) I: 0, O: 1 0

OA1I1 x 1

FUNCTION

Pad Logic

P6.2/OA0I1 (SW0A) P6.5/OA0I2 (SW0B) P6.6/OA1I1 (SW1A)

Bus

Keeper

OAx

CONTROL BITS / SIGNALS

P6DIR.x P6SEL.x

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

APPLICATION INFORMATION

Port P6 pin schematic: P6.7, input/output with Schmitt trigger

VLDx = 1111

To SVS Mux

MSP430FG47x

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

P6DIR.7

P6OUT.7

Module X OUT

P6SEL.7

P6IN.7

Port P6 (P6.7) pin functions

PIN NAME (P6.X)

P6.7/OA1I2/SVSIN 7

NOTES: 1. x: Don’t care.

P6.x (I/O) I: 0, O: 1 0 x

OA1I2 x 1 x

SVSIN x 1 1111

Direction 0: Input 1: Output

FUNCTION

Pad Logic

P6.7/OA1I2/SVSIN (SW1B)

Bus

Keeper

OAx

CONTROL BITS / SIGNALS

P6DIR.x P6SEL.x VLDx

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x

PINNAMEXFUNCTIO

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

Segment pin schematic: Sx, dedicated Segment Pins

LCDS12/16/20/24

Segment Sx

Sx pin functions

PIN NAME

Sx 12

Sx 13

Sx 14

Sx 15

Sx 16

Sx 17

Sx 18

Sx 19

Sx 22

Sx 23

Sx 24

Sx 25

Pad Logic

CONTROL BITS /

FUNCTION

Sx 1 (LCDS12)

3-state 0 (LCDS12)

Sx 1 (LCDS12)

3-state 0 (LCDS12)

Sx 1 (LCDS12)

3-state 0 (LCDS12)

Sx 1 (LCDS12)

3-state 0 (LCDS12)

Sx 1 (LCD16)

3-state 0 (LCD16)

Sx 1 (LCD16)

3-state 0 (LCD16)

Sx 1 (LCD16)

3-state 0 (LCD16)

Sx 1 (LCDS16)

3-state 0 (LCDS16)

Sx 1 (LCDS20)

3-state 0 (LCDS20)

Sx 1 (LCDS20)

3-state 0 (LCDS20)

Sx 1 (LCDS24)

3-state 0 (LCDS24)

Sx 1 (LCDS24)

3-state 0 (LCDS24)

SIGNALS

LCDSy

Segment pin schematic: COM0, dedicated COM0 pin

COM0

Sx pin functions

PIN NAME

COM0 -- COM0

Pad Logic

COM0

FUNCTION

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

APPLICATION INFORMATION

JTAG pins: TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt trigger

TDO

Controlled by JTAG

MSP430FG47x

JTAG

Test

and

Emulation

Module

Controlled by JTAG

TDI

TMS

TCK

Fuse

Burn & Test

Fuse

TDO/TDI

TDI/TCLK

TMS

During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry

TCK

JTAG fuse check mode

For details on the JTAG fuse check mode, see the MSP430 Memory Programming User’s Guide (SLAU265) chapter ”Fuse Check and Reset of the JTAG State Machine (TAP Controller)”.

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

MSP430FG47x MIXED SIGNAL MICROCONTROLLER

SLAS580D -- OCTOBER 2008 -- REVISED MARCH 2011

Data Sheet Revision History

LITERATURE

NUMBER

SLAS580 Product Preview release SLAS580A Changes throughout to update Product Preview SLAS580B Production Data release

SLAS580C

SLAS580D

In recommended operating c onditions table, changed maximum LFXT1 crystal frequency, f from 8 MHz to 6 MHz (page 24)

Changed limits on t Corrected measurement pin name for “Duty cycle, LF mode” parameter (page 37)

d(SVSon)

parameter (page 32)

SUMMARY

with XT1 selected

(LFXT1)

POST OFFICE BOX 655303  DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

28-Apr-2015

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

MSP430FG477IPN ACTIVE LQFP PN 80 119 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG477

MSP430FG477IPNR ACTIVE LQFP PN 80 1000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG477

MSP430FG477IZQWR ACTIVE BGA

MICROSTAR

JUNIOR

ZQW 113 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-3-260C-168 HR -40 to 85 M430FG477

MSP430FG478IPNR ACTIVE LQFP PN 80 1000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG478

MSP430FG478IZQW ACTIVE BGA

MICROSTAR

JUNIOR

ZQW 113 250 Green (RoHS

& no Sb/Br)

SNAGCU Level-3-260C-168 HR -40 to 85 M430FG478

MSP430FG478IZQWR ACTIVE BGA

MICROSTAR

JUNIOR

ZQW 113 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-3-260C-168 HR -40 to 85 M430FG478

MSP430FG479IPN ACTIVE LQFP PN 80 119 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG479

MSP430FG479IPNR ACTIVE LQFP PN 80 1000 Green (RoHS

& no Sb/Br)

CU NIPDAU Level-3-260C-168 HR -40 to 85 M430FG479

MSP430FG479IZQW ACTIVE BGA

MICROSTAR

JUNIOR

ZQW 113 250 Green (RoHS

& no Sb/Br)

SNAGCU Level-3-260C-168 HR -40 to 85 M430FG479

MSP430FG479IZQWR ACTIVE BGA

MICROSTAR

JUNIOR

ZQW 113 2500 Green (RoHS

& no Sb/Br)

SNAGCU Level-3-260C-168 HR -40 to 85 M430FG479

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.

PACKAGE OPTION ADDENDUM

www.ti.com

28-Apr-2015

Addendum-Page 2

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)

Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Sep-2014

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type

MSP430FG477IZQWR BGA MI

CROSTA

R JUNI

MSP430FG478IZQWR BGA MI

CROSTA

R JUNI

MSP430FG479IZQWR BGA MI

CROSTA

R JUNI

Package

Drawing

ZQW 113 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q1

Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm)B0(mm)K0(mm)P1(mm)W(mm)

Quadrant

Pin1

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Sep-2014

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

MSP430FG477IZQWR BGA MICROSTAR

JUNIOR

MSP430FG478IZQWR BGA MICROSTAR

JUNIOR

MSP430FG479IZQWR BGA MICROSTAR

JUNIOR

ZQW 113 2500 336.6 336.6 28.6

Pack Materials-Page 2

MECHANICAL DATA

MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996

PN (S-PQFP-G80) PLASTIC QUAD FLATPACK

1,45 1,35

0,50

9,50 TYP 12,20

11,80 14,20

13,80

0,27 0,17

0,08

0,05 MIN

0,13 NOM

Gage Plane

0,25

0°–7°

0,75 0,45

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Seating Plane

0,08

4040135 /B 11/96

IMPORTANT NOTICE

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

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Texas Instruments MSP430FG47x User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual