Texas Instruments MSP430FG4618, MSP430FG4617, MSP430FG4619, MSP430CG4618, MSP430FG4616 User Manual

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MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

MSP430FG461x, MSP430CG461x Mixed-Signal Microcontrollers

1 Device Overview

1.1 Features

• Low Supply-Voltage Range: 1.8 V to 3.6 V • Universal Serial Communication Interface

• Ultra-Low Power Consumption – Enhanced UART Supports Automatic Baud– Active Mode: 400 µA at 1 MHz, 2.2 V – Standby Mode: 1.3 µA – Off Mode (RAM Retention): 0.22 µA

• Five Power-Saving Modes

• Wakeup From Standby Mode in Less Than 6 µs

• 16-Bit RISC Architecture, Extended Memory, 125‑ns Instruction Cycle Time

• Three-Channel Internal DMA

• 12-Bit Analog-to-Digital Converter (ADC) With Internal Reference, Sample-and-Hold and Autoscan Feature • Section 3 Summarizes the Available Family

• Three Configurable Operational Amplifiers

• Dual 12-Bit Digital-to-Analog Converters (DACs) With Synchronization

• 16-Bit Timer_A With Three Capture/Compare Registers

• 16-Bit Timer_B With Seven Capture/CompareWith-Shadow Registers

• On-Chip Comparator

• Supply Voltage Supervisor and Monitor With Programmable Level Detection

• Serial Communication Interface (USART1), Select Asynchronous UART or Synchronous SPI by Software

Rate Detection – IrDA Encoder and Decoder – Synchronous SPI – I2C

• Serial Onboard Programming, Programmable Code Protection by Security Fuse

• Brownout Detector

• Basic Timer With Real-Time Clock (RTC) Feature

• Integrated LCD Driver up to 160 Segments With Regulated Charge Pump

Members – MSP430FG4616, MSP430FG4616

92KB+256B of Flash or ROM 4KB of RAM

– MSP430FG4617, MSP430CG4617

92KB+256B of Flash or ROM 8KB of RAM

– MSP430FG4618, MSP430CG4618

116KB+256B of Flash or ROM 8KB of RAM

– MSP430FG4619, MSP430CG4619

120KB+256B of Flash or ROM 4KB of RAM

• For Complete Module Descriptions, see the MSP430x4xx Family User’s Guide (SLAU056)

1.2 Applications

• Portable Medical Applications • E-Meter Applications

1.3 Description

The TI MSP430™ family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from lowpower modes to active mode in less than 6 µs.

The MSP430xG461x series are microcontroller configurations with two 16-bit timers, a high-performance 12-bit ADC, dual 12-bit DACs, three configurable operational amplifiers, one universal serial communication interface (USCI), one universal synchronous/asynchronous communication interface (USART), DMA, 80 I/O pins, and a segment liquid crystal display (LCD) driver with regulated charge pump.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

Oscillators

FLL+

RAM

4KB 8KB 8KB 4KB

Brownout

Protection

SVS/SVM

RST/NMI

DVCC 1/2 DVSS1 /2

MCLK

Watchdog

WDT+

15/16- Bit

Timer_ A3

3 CC

Registers

8MHz

CPUX

incl. 16

Registers

XOUT/ XT2 OUT

OA0, OA 1,

OA2

3 Op Amps

Basic Timer

and

Real-Time

Clock

JTAG

Interface

LCD_A

160

Segments

1,2,3 ,4 Mux

Ports

P1/P2

2x8 I/O

Interrupt

capability

USCI_A 0:

UART,

IrDA, SPI

USCI_B 0:

SPI, I2 C

Comparator

Flash (FG) ROM (CG)

120KB 116KB

92KB 92KB

Hardware

Multiplier

MPY,

MPYS,

MAC,

MACS

Timer_B 7

7 CC

Registers,

Shadow

Reg

ADC12

12-Bit

Channels

DAC12

12-Bit

2 Channels Voltage out

USART 1

UART , SPI

DMA

Controller

3 Channels

Ports P3/P4 P5/P6

4x8 I/O

Ports

P7/P8

P9/P10

4x8, 2x16 I/O

AVCC AVSS P1.x/P2 .x

2x 8

P3.x/P4 .x P5.x/P6 .x

4x 8

P7.x/P8. x

P9.x/P10.x

4x 8/2x16

XIN /

XT2 IN

SMCLK

ACLK

MDB

MAB

Enhanced

Emulation

(FG only)

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

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PART NUMBER PACKAGE BODY SIZE

MSP430FG4619IPZ LQFP (100) 14 mm × 14 mm MSP430FG4619IZQW MicroStar Junior™ BGA (113) 7 mm × 7 mm

(1) For the most current part, package, and ordering information for all available devices, see the Package

Option Addendum in Section 8, or see the TI website at www.ti.com.

(2) The sizes shown here are approximations. For the package dimensions with tolerances, see the

Mechanical Data in Section 8.

1.4 Functional Block Diagram

Figure 1-1 shows the functional block diagram.

Device Information

(1)

(2)

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Figure 1-1. Functional Block Diagram

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MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table of Contents

1 Device Overview ......................................... 1 5.30 12-Bit ADC, Timing Parameters .................... 37

1.1 Features .............................................. 1 5.31 12-Bit ADC, Linearity Parameters................... 37

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagram............................ 2

2 Revision History ......................................... 4

3 Device Comparison ..................................... 5

4 Terminal Configuration and Functions.............. 6

4.1 Pin Diagrams ......................................... 6

4.2 Signal Descriptions................................... 8

5 Specifications........................................... 14

5.1 Absolute Maximum Ratings ........................ 14

5.2 ESD Ratings ........................................ 14

5.3 Recommended Operating Conditions............... 14

5.4 Supply Current Into AVCC+ DVCCExcluding

External Current .................................... 16

5.5 Thermal Characteristics............................. 17

5.6 Schmitt-Trigger Inputs – Ports P1 to P10, RST/NMI,

JTAG (TCK, TMS, TDI/TCLK,TDO/TDI) ............ 18

5.7 Inputs Px.x, TAx, TBX............................... 18

5.8 Leakage Current – Ports P1 to P10 ................ 18

5.9 Outputs – Ports P1 to P10 .......................... 18

5.10 Output Frequency................................... 19

5.11 Typical Characteristics – Outputs................... 20

5.12 Wake-up Timing From LPM3 ....................... 21

5.13 RAM................................................. 21

5.14 LCD_A............................................... 21

5.15 Comparator_A ...................................... 22

5.16 Typical Characteristics – Comparator_A............ 23

5.17 POR, BOR .......................................... 24

5.18 SVS (Supply Voltage Supervisor and Monitor) ..... 25

5.19 DCO................................................. 27

5.20 Crystal Oscillator, LFXT1 Oscillator ................ 29

5.21 Crystal Oscillator, XT2 Oscillator ................... 29

5.22 USCI (UART Mode)................................. 29

5.23 USCI (SPI Master Mode)............................ 30

5.24 USCI (SPI Slave Mode)............................. 30

5.25 USCI (I

5.26 USART1............................................. 33

5.27 12-Bit ADC, Power Supply and Input Range

5.28 12-Bit ADC, External Reference ................... 34

5.29 12-Bit ADC, Built-In Reference...................... 35

C Mode).................................... 33

Conditions .......................................... 34

5.32 12-Bit ADC, Temperature Sensor and Built-In V

MID

...................................................... 38

5.33 12-Bit DAC, Supply Specifications.................. 38

5.34 12-Bit DAC, Linearity Specifications ................ 39

5.35 12-Bit DAC, Output Specifications .................. 41

5.36 12-Bit DAC, Reference Input Specifications........ 41

5.37 12-Bit DAC, Dynamic Specifications................ 42

5.38 12-Bit DAC, Dynamic Specifications Continued .... 43

5.39 Operational Amplifier OA, Supply Specifications ... 44

5.40 Operational Amplifier OA, Input/Output

Specifications........................................ 44

5.41 Operational Amplifier OA, Dynamic Specifications . 45

5.42 Operational Amplifier OA, Typical Characteristics.. 45

5.43 Operational Amplifier OA Feedback Network,

Noninverting Amplifier Mode (OAFCx = 4).......... 46

5.44 Operational Amplifier OA Feedback Network,

Inverting Amplifier Mode (OAFCx = 6).............. 46

5.45 Flash Memory (FG461x Devices Only) ............. 47

5.46 JTAG Interface...................................... 47

5.47 JTAG Fuse ......................................... 47

6 Detailed Description................................... 48

6.1 CPU ................................................. 48

6.2 Instruction Set....................................... 49

6.3 Operating Modes.................................... 50

6.4 Interrupt Vector Addresses.......................... 51

6.5 Special Function Registers (SFRs) ................. 52

6.6 Memory Organization ............................... 54

6.7 Bootstrap Loader (BSL)............................. 55

6.8 Flash Memory....................................... 55

6.9 Peripherals .......................................... 55

6.10 Input/Output Schematics ............................ 65

7 Device and Documentation Support.............. 100

7.1 Device Support..................................... 100

7.2 Documentation Support............................ 103

7.3 Related Links ...................................... 103

7.4 Community Resources............................. 104

7.5 Trademarks ........................................ 104

7.6 Electrostatic Discharge Caution ................... 104

7.7 Export Control Notice.............................. 104

7.8 Glossary............................................ 104

8 Mechanical, Packaging, and Orderable

Information............................................. 105

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SLAS508J –APRIL 2006–REVISED JUNE 2015

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from March 2, 2011 to June 19, 2015 Page

• Document format and organization changes throughout, including the addition of section numbering ................... 1

• Added Device Information table .................................................................................................... 2

• Moved functional block diagram to Section 1.4................................................................................... 2

• Added Section 3, Device Comparison............................................................................................. 5

• Added signal names to ZQW pinout figure........................................................................................ 7

• Changed table note that starts "Segments S0 through S3 are disabled when..."............................................ 8

• Added row for unassigned ball locations on ZQW package................................................................... 13

• Added Section 5 and moved all electrical specifications to it ................................................................. 14

• Added Section 5.2, ESD Ratings.................................................................................................. 14

• In Recommended Operating Conditions, added test conditions for TYP values ........................................... 14

• Added Section 5.5, Thermal Characteristics .................................................................................... 17

• Changed table note that starts "Segments S0 through S3 are disabled when..." .......................................... 21

• Changed the value of DAC12_xDAT from 7F7h to F7Fh in Figure 5-33 .................................................... 43

• Added Table 6-19 and moved P4.6 and P4.7 from Table 6-18 to insert correct LCDS32 control bit name ............ 75

• Added Table 6-29 and moved P7.2 and P7.3 from Table 6-28 to insert correct LCDS28 control bit name ............ 88

• Added Table 6-31 and moved P7.6 and P7.7 from Table 6-30 to insert correct LCDS24 control bit name ............ 89

• Added Table 6-33 and moved P8.2 to P8.5 from Table 6-32 to insert correct LCDS20 control bit name............... 90

• Added Table 6-36 and moved P9.2 to P9.5 from Table 6-35 to insert correct LCDS12 control bit name............... 92

• Corrected LCD segment numbers in PIN NAME column of Table 6-36..................................................... 92

• Added Table 6-37 and moved P9.6 and P9.7 from Table 6-35 to insert correct LCDS8 control bit name.............. 93

• Corrected LCD segment numbers in PIN NAME column of Table 6-37..................................................... 93

• Corrected LCD segment numbers in PIN NAME and FUNCTION columns of Table 6-38................................ 94

• Added Table 6-39 and moved P10.2 to P10.5 from Table 6-38 to insert correct LCDS4 control bit name ............. 94

• Added Section 7 and moved Trademarks and ESD Caution sections to it ................................................ 100

• Added Section 8 ................................................................................................................... 105

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SLAS508J –APRIL 2006–REVISED JUNE 2015

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1. Device Comparison

(1)(2)

FLASH ROM RAM ADC12 DAC12 COMP_A

DEVICE EEM Timer_A Timer_B OP AMP USART USCI I/O PACKAGE

(KB) (KB) (KB) (Channels) (Channels) (Channels)

PZ 100

MSP430FG4619 120 – 4 1 TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430FG4618 116 – 8 1 TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430FG4617 92 – 8 1 TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430FG4616 92 – 4 1 TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430CG4619 – 120 4 – TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430CG4618 – 116 8 – TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430CG4617 – 92 8 – TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

PZ 100

MSP430CG4616 – 92 4 – TA3 TB7 12 3 2 2 1 A0, B0 80

ZQW 113

(1) For the most currentdevice, package,and ordering information for all available devices, see thePackage Option Addendum in Section 8, orsee theTI website at www.ti.com. (2) Package drawings, thermal data,and symbolizationare available at www.ti.com/packaging.

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MSP430CG4618 MSP430CG4617 MSP430CG4616

10 0

P1 .7 /C A1

P6 .1 /A 1/ OA 0 O

P6 .0 /A 0/ OA 0 I0

RS T /N M I

XT 2 IN

XT 2 OU T

P1 .3 /T BO U T H/ SV S O UT

P1 .4 /T BC L K/SMC L K

P1 .5 /TA CLK /A CLK

P1 .6 /C A0

P2 .3 /T B2

P9 ,2 /S 15

P9 .1 /S 16

P9 .0 /S 17

P8 .5 /S 20

P8 .0 /S 25

P7 .7 /S 26

P7 .6 /S 27

P7 .5 /S 28

P7 .4 /S 29

P4 .7 /U C A0 R XD /S3 4

P7 .3 /U C A0 C LK /S 3 0

P1 .0 /TA 0

TD I/ TC L K

TD O /T DI

P8 .4 /S 21

SS 1

P6 .2 /A 2/ OA 0 I1

P1 .2 /TA 1

P8 .1 /S 24

P4 .6 /U C A0 TXD /S 3 5

DVCC1

P6.3/A3/OA1O

P6.4/A4/OA1I0

P6.5/A5/OA2O

P6.6/A6/DAC0/OA2I0

P6.7/A7/DAC1/SVSIN

VREF+

XIN

XOUT

VeREF+/DAC0

VREF-/VeREF-

P5.1/S0/A12/DAC1

P5.0/S1/A13/OA1I1

P10.7/S2/A14/OA2I1

P10.6/S3/A15

P10.5/S4

P10.4/S5

P10.3/S6

P10.2/S7

P10.1/S8

P10.0/S9

P9.7/S10

P9.6/S11

P9.5/S12

P9.4/S13

P2.4/UCA0TXD

P2.5/UCA0RXD

P2.6/CAOUT

P2.7/ADC12CLK/DMAE0

P3.0/UCB0STE

P3.1/UCB0SIMO/UCB0SDA

P3.2/UCB0SOMI/UCB0SCL

P3.3/UCB0CLK

P3.4/TB3

P3.5/TB4

P3.6/TB5

P3.7/TB6

P4.0/UTXD1

P4.1/URXD1

DVSS2

DVCC2

LCDCAP/R33

P5.7/R23

P5.6/LCDREF/R13

P5.5/R03

P5.4/COM3

P5.3/COM2

P5.2/COM1

COM0

P4.2/STE1/S39

P8 .6 /S 19

P8 .3 /S 22

P8 .2 /S 23

P7 .0 /U C A0 S TE /S 3 3

P4 .5 /U C LK 1/S36

P4 .4 /S OMI 1/S3 7

P4 .3 /S IM O 1/S3 8

CCAVSS

TC K

TM S

P1 .1 /TA 0/MC L K

P2 .0 /TA 2

P2 .1 /T B0

P2 .2 /T B1

P9.3/S14

P8.7/S18

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the 100-pin PZ package.

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Figure 4-1. 100-Pin PZ Package (Top View)

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1 2 3 4 5 6 7 8 9 10 11 12

CC1

P6.3

P6.6

XIN

XOUT

P5.1

P10.6

P10.3

P10.0

P9.5

P9.4

N/A

P6.4

P6.5

REF+

P5.0

P10.5

P10.2

P9.7

P9.2

N/A

P9.3

SS1

P6.7

P9.1

P9.0

P6.0

P6.2

N/A

REF–

P10.4

P9.6

P8.7

N/A

P8.6

P8.5

TCK

RST

P6.1

P10.7

P10.1

P8.4

P8.1

P8.0

P8.3

P8.2

TDO

XT2IN

TDI

TMS

P7.3

P7.5

P7.6

P7.7

P1.0

XT2OUT

P1.2

P1.1

P4.4

P4.7

P7.2

P7.4

P1.3

P1.4

P2.1

P2.2

N/A

P5.3

P7.0

P7.1

P1.6

P1.5

N/A

P2.7

P3.2

P3.5

P4.0

N/A

P4.5

P4.6

P2.0

P1.7

COM0

P4.3

P2.3

N/A

P2.5

P3.0

P3.3

P3.6

P4.1

LCDCAP

P5.7

P5.5

N/A

P4.2

N/A

P2.4

P2.6

P3.1

P3.4

P3.7

SS2

CC2

P5.6

P5.4

P5.2

N/A

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Figure 4-2 shows the pinout for the 113-pin ZQW package. This figure shows only the default pin

assignments; for all pin assignments, see Table 4-1.

MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616

MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

supply. The shortest ground return path to the device should be established to ball location B3, DV

N/A = Not Assigned. All unassigned ball locations on the ZQW package should be electrically tied to the ground

Figure 4-2. 113-Pin ZQW Package (Top View)

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SS1

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SLAS508J –APRIL 2006–REVISED JUNE 2015

4.2 Signal Descriptions

Table 4-1 describes the signals for all device variants and package options.

Table 4-1. Signal Descriptions

SIGNAL NAME I/O DESCRIPTION

CC1

P6.3 General-purpose digital I/O A3 2 B1 I/O Analog input A3 for 12-bit ADC OA1O OA1 output P6.4 General-purpose digital I/O A4 3 B2 I/O Analog input A4 for 12-bit ADC OA1I0 OA1 input multiplexer on + terminal and – terminal P6.5 General-purpose digital I/O A5 4 C2 I/O Analog input A5 for 12-bit ADC OA2O OA2 output P6.6 General-purpose digital I/O A6 Analog input A6 for 12-bit ADC DAC0 DAC12.0 output OA2I0 OA2 input multiplexer on + terminal and – terminal P6.7 General-purpose digital I/O A7 Analog input A7 for 12-bit ADC DAC1 DAC12.1 output SVSIN Analog input to brownout, supply voltage supervisor V

REF+

XIN 8 D1 I Input port for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT 9 E1 O Output terminal of crystal oscillator XT1 Ve

REF+

DAC0 DAC12.0 output V

REF

REF–

P5.1 General-purpose digital I/O

(1)

S0 A12 Analog input A12 for 12-bit ADC DAC1 DAC12.1 output P5.0 General-purpose digital I/O

(1)

S1 A13 Analog input A13 for 12-bit ADC OA1I1 OA1 input multiplexer on + terminal and – terminal P10.7 General-purpose digital I/O

(1)

S2 A14 Analog input A14 for 12-bit ADC OA2I1 OA2 input multiplexer on + terminal and – terminal P10.6 General-purpose digital I/O

(1)

S3 A15 Analog input A15 to 12-bit ADC

PIN NO.

PZ ZQW

1 A1 Digital supply voltage, positive terminal

5 C1 I/O

6 C3 I/O

7 D2 O Output of positive terminal of the reference voltage in the ADC

10 E2 I/O

11 E4 I

12 F1 I/O

13 F2 I/O

14 E5 I/O

Input for an external reference voltage to the ADC

Internal reference voltage, negative terminal for the ADC reference voltage External applied reference voltage, negative terminal for the ADC reference voltage

LCD segment output 0

LCD segment output 1

LCD segment output 2

15 G1 I/O LCD segment output 3

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(1) Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and, therefore, cannot be used

together with the LCD charge pump. On the MSP430xG461x devices only, S0 through S3 are also disabled if VLCDEXT = 1. This setting is typically used to apply an external LCD voltage supply to the LCDCAP terminal. For these devices, set LCDCPEN = 0, VLCDEXT = 0, and VLCDx > 0 to enable an external LCD voltage supply to be applied to the LCDCAP terminal.

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Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

P10.5 General-purpose digital I/O S4 LCD segment output 4 P10.4 General-purpose digital I/O S5 LCD segment output 5 P10.3 General-purpose digital I/O S6 LCD segment output 6 P10.2 General-purpose digital I/O S7 LCD segment output 7 P10.1 General-purpose digital I/O S8 LCD segment output 8 P10.0 General-purpose digital I/O S9 LCD segment output 9 P9.7 General-purpose digital I/O S10 LCD segment output 10 P9.6 General-purpose digital I/O S11 LCD segment output 11 P9.5 General-purpose digital I/O S12 LCD segment output 12 P9.4 General-purpose digital I/O S13 LCD segment output 13 P9.3 General-purpose digital I/O S14 LCD segment output 14 P9.2 General-purpose digital I/O S15 LCD segment output 15 P9.1 General-purpose digital I/O S16 LCD segment output 16 P9.0 General-purpose digital I/O S17 LCD segment output 17 P8.7 General-purpose digital I/O S18 LCD segment output 18 P8.6 General-purpose digital I/O S19 LCD segment output 19 P8.5 General-purpose digital I/O S20 LCD segment output 20 P8.4 General-purpose digital I/O S21 LCD segment output 21 P8.3 General-purpose digital I/O S22 LCD segment output 22 P8.2 General-purpose digital I/O S23 LCD segment output 23 P8.1 General-purpose digital I/O S24 LCD segment output 24 P8.0 General-purpose digital I/O S25 LCD segment output 25 P7.7 General-purpose digital I/O S26 LCD segment output 26

PIN NO.

PZ ZQW

16 G2 I/O

17 F4 I/O

18 H1 I/O

19 H2 I/O

20 F5 I/O

21 J1 I/O

22 J2 I/O

23 G4 I/O

24 K1 I/O

25 L1 I/O

26 M2 I/O

27 K2 I/O

28 L3 I/O

29 M3 I/O

30 H4 I/O

31 L4 I/O

32 M4 I/O

33 G5 I/O

34 L5 I/O

35 M5 I/O

36 H5 I/O

37 J5 I/O

38 M6 I/O

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Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

P7.6 General-purpose digital I/O S27 LCD segment output 27 P7.5 General-purpose digital I/O S28 LCD segment output 28 P7.4 General-purpose digital I/O S29 LCD segment output 29 P7.3 General-purpose digital I/O UCA0CLK External clock input – USCI_A0 in UART or SPI mode,

S30 LCD segment 30 P7.2 General-purpose digital I/O UCA0SOMI 43 L7 I/O Slave out/master in of USCI_A0 in SPI mode S31 LCD segment output 31 P7.1 General-purpose digital I/O UCA0SIMO 44 M8 I/O Slave in/master out of USCI_A0 in SPI mode S32 LCD segment output 32 P7.0 General-purpose digital I/O UCA0STE 45 L8 I/O Slave transmit enable – USCI_A0 in SPI mode S33 LCD segment output 33 P4.7 General-purpose digital I/O UCA0RXD 46 J7 I/O Receive data in – USCI_A0 in UART or IrDA mode S34 LCD segment output 34 P4.6 General-purpose digital I/O UCA0TXD 47 M9 I/O Transmit data out – USCI_A0 in UART or IrDA mode S35 LCD segment output 35 P4.5 General-purpose digital I/O UCLK1 External clock input – USART1 in UART or SPI mode,

S36 LCD segment output 36 P4.4 General-purpose digital I/O SOMI1 49 H7 I/O Slave out/master in of USART1 in SPI mode S37 LCD segment output 37 P4.3 General-purpose digital I/O SIMO1 50 M10 I/O Slave in/master out of USART1 in SPI mode S38 LCD segment output 38 P4.2 General-purpose digital I/O STE1 51 M11 I/O Slave transmit enable – USART1 in SPI mode S39 LCD segment output 39 COM0 52 L10 O Common output, COM0 for LCD backplanes P5.2 General-purpose digital I/O COM1 Common output, COM1 for LCD backplanes P5.3 General-purpose digital I/O COM2 Common output, COM2 for LCD backplanes P5.4 General-purpose digital I/O COM3 Common output, COM3 for LCD backplanes P5.5 General-purpose digital I/O R03 Input port of lowest analog LCD level (V5)

PIN NO.

PZ ZQW

39 L6 I/O

40 J6 I/O

41 M7 I/O

42 H6 I/O

48 L9 I/O

53 L12 I/O

54 J8 I/O

55 K12 I/O

56 K11 I/O

Clock output – USCI_A0 in SPI mode

Clock output – USART1 in SPI MODE

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

P5.6 General-purpose digital I/O LCDREF 57 J12 I/O External reference voltage input for regulated LCD voltage R13 Input port of third most positive analog LCD level (V4 or V3) P5.7 General-purpose digital I/O R23 Input port of second most positive analog LCD level (V2) LCDCAP LCD capacitor connection R33 Input/output port of most positive analog LCD level (V1) DV

CC2

SS2

P4.1 General-purpose digital I/O URXD1 Receive data in – USART1 in UART mode P4.0 General-purpose digital I/O UTXD1 Transmit data out – USART1 in UART mode P3.7 General-purpose digital I/O TB6 Timer_B7 CCR6. Capture: CCI6A/CCI6B input, compare: Out6 output P3.6 General-purpose digital I/O TB5 Timer_B7 CCR5. Capture: CCI5A/CCI5B input, compare: Out5 output P3.5 General-purpose digital I/O TB4 Timer_B7 CCR4. Capture: CCI4A/CCI4B input, compare: Out4 output P3.4 General-purpose digital I/O TB3 Timer_B7 CCR3. Capture: CCI3A/CCI3B input, compare: Out3 output P3.3 General-purpose digital I/O UCB0CLK External clock input – USCI_B0 in UART or SPI mode,

P3.2 General-purpose digital I/O UCB0SOMI 69 F9 I/O Slave out/master in of USCI_B0 in SPI mode UCB0SCL I2C clock – USCI_B0 in I2C mode P3.1 General-purpose digital I/O UCB0SIMO 70 D12 I/O Slave in/master out of USCI_B0 in SPI mode UCB0SDA I2C data – USCI_B0 in I2C mode P3.0 General-purpose digital I/O UCB0STE Slave transmit enable – USCI_B0 in SPI mode P2.7 General-purpose digital I/O ADC12CLK 72 E9 I/O Conversion clock for 12-bit ADC DMAE0 DMA channel 0 external trigger P2.6 General-purpose digital I/O CAOUT Comparator_A output P2.5 General-purpose digital I/O UCA0RXD Receive data in – USCI_A0 in UART or IrDA mode P2.4 General-purpose digital I/O UCA0TXD Transmit data out – USCI_A0 in UART or IrDA mode P2.3 General-purpose digital I/O TB2 Timer_B7 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output P2.2 General-purpose digital I/O TB1 Timer_B7 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output P2.1 General-purpose digital I/O TB0 Timer_B7 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output

PIN NO.

PZ ZQW

58 J11 I/O

59 H11 I

60 H12 Digital supply voltage, positive terminal 61 G12 Digital supply voltage, negative terminal

62 G11 I/O

63 H9 I/O

64 F12 I/O

65 F11 I/O

66 G9 I/O

67 E12 I/O

68 E11 I/O

Clock output – USCI_B0 in SPI mode

71 D11 I/O

73 C12 I/O

74 C11 I/O

75 B12 I/O

76 A11 I/O

77 E8 I/O

78 D8 I/O

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Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

P2.0 General-purpose digital I/O TA2 Timer_A Capture: CCI2A input, compare: Out2 output P1.7 General-purpose digital I/O CA1 Comparator_A input P1.6 General-purpose digital I/O CA0 Comparator_A input P1.5 General-purpose digital I/O TACLK 82 B9 I/O Timer_A, clock signal TACLK input ACLK ACLK output (divided by 1, 2, 4, or 8) P1.4 General-purpose digital I/O TBCLK 83 B8 I/O Input clock TBCLK – Timer_B7 SMCLK Submain system clock SMCLK output P1.3 General-purpose digital I/O TBOUTH 84 A8 I/O Switch all PWM digital output ports to high impedance – Timer_B7 TB0 to TB6 SVSOUT SVS: output of SVS comparator P1.2 General-purpose digital I/O TA1 Timer_A, Capture: CCI1A input, compare: Out1 output P1.1 General-purpose digital I/O TA0 86 E7 I/O Timer_A. Capture: CCI0B input. Note: TA0 is only an input on this pin. BSL receive. MCLK MCLK output P1.0 General-purpose digital I/O TA0 Timer_A. Capture: CCI0A input, compare: Out0 output. BSL transmit. XT2OUT 88 B7 O Output terminal of crystal oscillator XT2 XT2IN 89 B6 I Input port for crystal oscillator XT2. Only standard crystals can be connected. TDO Test data output port. TDO/TDI data output. TDI Programming data input terminal TDI Test data input TCLK Test clock input. The device protection fuse is connected to TDI/TCLK. TMS 92 E6 I Test mode select. TMS is used as an input port for device programming and test. TCK 93 A5 I Test clock. TCK is the clock input port for device programming and test. RST Reset input NMI Nonmaskable interrupt input port P6.0 General-purpose digital I/O A0 95 A4 I/O Analog input A0 for 12-bit ADC OA0I0 OA0 input multiplexer on + terminal and – terminal P6.1 General-purpose digital I/O A1 96 D5 I/O Analog input A1 for 12-bit ADC OA0O OA0 output P6.2 General-purpose digital I/O A2 97 B4 I/O Analog input A2 for 12-bit ADC OA0I1 OA0 input multiplexer on + terminal and – terminal

AVSS 98 A3 DV

SS1

PIN NO.

PZ ZQW

79 A10 I/O

80 B10 I/O

81 A9 I/O

85 D7 I/O

87 A7 I/O

90 A6 I/O

91 D6 I

94 B5 I

Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator, Comparator_A, port 1

99 B3 Digital supply voltage, negative terminal

100 A2

Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator, Comparator_A, port 1. Do not power up before powering DV

CC1

and DV

CC2

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SLAS508J –APRIL 2006–REVISED JUNE 2015

Table 4-1. Signal Descriptions (continued)

SIGNAL NAME I/O DESCRIPTION

Not Assigned – G8, H8, – supply. The shortest ground return path to the device should be established to ball location

PIN NO.

PZ ZQW

A12,

B11, D4,

D9, F8, All unassigned ball locations on the ZQW package should be electrically tied to the ground

J4, J9, B3, DV

L2, L11,

M1, M12

SS1

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5 Specifications

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5.1 Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

Voltage applied at VCCto V Voltage applied to any pin

(2)

–0.3 4.1 V –0.3 VCC+ 0.3 V

Diode current at any device terminal ±2 mA

Storage temperature, T

stg

Unprogrammed device –55 105 Programmed device –40 85

°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are referenced to VSS.The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TDI/TCLK pin when blowing the JTAG fuse.

5.2 ESD Ratings

VALUE UNIT

Electrostatic discharge V

(ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 Charged-device model (CDM), per JEDEC specification JESD22-C101

(1)

(2)

±1000

±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±1000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V

may actually have higher performance.

5.3 Recommended Operating Conditions

Typical values are specified at VCC= 3.3 V and TA= 25°C (unless otherwise noted)

MIN NOM MAX UNIT

During program execution (AVCC= DV

Supply voltage 2.7 3.6 V

During flash memory programming (FG461x) (AVCC= DV

CC1/2

= VCC)

During program execution, SVS enabled and PORON = 1 (AVCC= DV

Supply voltage (AVSS= DV

= VSS) 0 0 V

SS1/2

Operating free-air temperature range –40 85 °C

CC1/2

= VCC)

LF selected, XTS_FLL = 0

(LFXT1)

Crystal frequency

(3)

XT1 selected, XTS_FLL = 1 Ceramic resonator 450 8000 kHz XT1 selected, XTS_FLL = 1 Crystal 1000 8000

(XT2)

(System)

Crystal frequency kHz

Processor frequency (signal MCLK) VCC= 2.0 V DC 4.6 MHz

(1) TI recommends powering AVCCand DVCCfrom the same source. A maximum difference of 0.3 V between AVCCand DVCCcan be

tolerated during power up and operation.

(2) The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply

voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS circuitry.

(3) In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.

(1)

(2)

(3)

Watch crystal 32.768

(1)

1.8 3.6

2 3.6

Ceramic resonator 450 8000 Crystal 1000 8000 VCC= 1.8 V DC 3

VCC= 3.6 V DC 8

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1.8 3.62.7 3

3.0 MHz

8.0 MHz

Supply Voltage (V)

Supply voltage range, MSP430FG461x, during flash memory programming

Supply voltage range, MSP430xG461x, during program execution

2.0

4.6 MHz

f (MHz)

System

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Figure 5-1. Frequency vs Supply Voltage

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5.4 Supply Current Into AVCC+ DVCCExcluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

(1) (2)

= f

= 32768 Hz, µA

(SMCLK)

= 1 MHz,

CG461x TA= –40°C to 85°C

FG461x TA= –40°C to 85°C

(1) (2)

TA= –40°C to 85°C µA

(AM)

(LPM0)

Active mode f

(MCLK)

(ACLK)

XTS = 0, SELM = (0, 1), (FG461x: program executes from flash)

Low power mode (LPM0)

Low-power mode (LPM2), VCC= 2.2 V 11 20

(LPM2)f(MCLK)

= f

(ACLK)

(SMCLK)

= 32768 Hz, SCG0 = 0

= 0 MHz, TA= –40°C to 85°C µA

(3) (2)

TA= –40°C 1.3 4.0 TA= 25°C 1.3 4.0

(LPM3)

Low-power mode (LPM3), f

= f

(MCLK)

= 32768 Hz, SCG0 = 1,

(ACLK)

Basic Timer1 enabled, ACLK selected, LCD_A enabled, LCDCPEN = 0, (static mode, f

(SMCLK)

= 0 MHz,

LCD

= f

(ACLK)

/32)

(3) (4) (2)

TA= 60°C 2.22 6.5 TA= 85°C 6.5 15.0 TA= –40°C 1.9 5.0 TA= 25°C 1.9 5.0 TA= 60°C 2.5 7.5 TA= 85°C 7.5 18.0 TA= –40°C 1.5 5.5 TA= 25°C 1.5 5.5

(LPM3)

Low-power mode (LPM3), f

= f

(MCLK)

= 32768 Hz, SCG0 = 1,

(ACLK)

Basic Timer1 enabled, ACLK selected, LCD_A enabled, LCDCPEN = 0, (4-mux mode; f

(SMCLK)

= 0 MHz,

= f

LCD

(ACLK)

/32)

(3) (4) (2)

TA= 60°C 2.8 7.0 TA= 85°C 7.2 17.0 TA= –40°C 2.5 6.5 TA= 25°C 2.5 6.5 TA= 60°C 3.2 8.0 TA= 85°C 8.5 20.0 TA= –40°C 0.13 1.0 TA= 25°C 0.22 1.0 TA= 60°C 0.9 2.5

Low-power mode (LPM4),

(LPM4)f(MCLK)

(ACLK)

= 0 MHz, f

= 0 Hz, SCG0 = 1

(SMCLK)

= 0 MHz, µA

(3) (2)

TA= 85°C 4.3 12.5 TA= –40°C 0.13 1.6 TA= 25°C 0.3 1.6 TA= 60°C 1.1 3.0 TA= 85°C 5.0 15.0

(1) Timer_B is clocked by f (2) Current for brownout included.

(DCOCLK)

= f

= 1 MHz. Allinputs aretied to 0 V or to VCC. Outputs do notsource orsink any current.

(DCO)

(3) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. (4) The LPM3 currents are characterized with a Micro Crystal CC4V-T1A (9 pF) crystal and OSCCAPx = 1h.

VCC= 2.2 V 280 370 VCC= 3 V 470 580 VCC= 2.2 V 400 480 VCC= 3 V 600 740 VCC= 2.2 V 45 70 VCC= 3 V 75 110

VCC= 3 V 17 24

VCC= 2.2 V

VCC= 3 V

VCC= 2.2 V

VCC= 3 V

VCC= 2.2 V

VCC= 3 V

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µA

Current consumption of active mode versus system frequency, FG version: I

(AM)

= I

(AM) [1 MHz]

× f

(System)

[MHz] Current consumption of active mode versus supply voltage, FG version: I

= I

(AM)

(AM) [3 V]

+ 200 µA/V × (VCC– 3 V)

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.5 Thermal Characteristics

PARAMETER PACKAGE VALUE UNIT

JC,TOP

Junction-to-ambient thermal resistance, still air Junction-to-case (top) thermal resistance Junction-to-board thermal resistance

(3)

Junction-to-board thermal characterization parameter 12 °C/W Junction-to-top thermal characterization parameter 0.3 °C/W Junction-to-ambient thermal resistance, still air Junction-to-case (top) thermal resistance Junction-to-board thermal resistance

(3)

Junction-to-board thermal characterization parameter 21.2 °C/W Junction-to-top thermal characterization parameter 0.2 °C/W

(1) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as

specified in JESD51-7, in an environment described in JESD51-2a.

(2) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC

standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB

temperature, as described in JESD51-8.

(1)

(2)

42 °C/W 10 °C/W

ZQW (S-PBGA-N113) 12 °C/W

(1)

(2)

43.5 °C/W

6.2 °C/W

PZ (S-PQFP-G100) 21.8 °C/W

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5.6 Schmitt-Trigger Inputs – Ports P1 to P10, RST/NMI, JTAG (TCK, TMS, TDI/TCLK,TDO/TDI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

IT+

IT–

hys

Positive-going input threshold voltage V

Negative-going input threshold voltage V

Input voltage hysteresis (V

IT+

– V

) V

IT–

VCC= 2.2 V 1.1 1.55 VCC= 3 V 1.5 1.98 VCC= 2.2 V 0.4 0.9 VCC= 3 V 0.9 1.3 VCC= 2.2 V 0.3 1.1 VCC= 3 V 0.5 1

5.7 Inputs Px.x, TAx, TBX

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

(int)

(cap)

(TAext)

(TBext)

(TAint)

(TBint)

External interrupt timing ns

Timer_A, Timer_B capture timing ns

Timer_A or Timer_B clock frequency TACLK, TBCLK externally applied to pin INCLK t

Timer A or Timer B clock frequency SMCLK or ACLK signal selected MHz

Port P1, P2: P1.x to P2.x, external trigger signal for the interrupt flag

TA0, TA1, TA2 TB0, TB1, TB2, TB3, TB4, TB5, TB6

= t

(H)

(L)

(1) The external signal sets the interrupt flag every time the minimum t

shorter than t

5.8 Leakage Current – Ports P1 to P10

(int)

(1)

parameters are met. It may be set even with trigger signals

(int)

2.2 V 62 3 V 50

2.2 V 8 3 V 10

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

(2)

lkg(Px.y)

Leakage current, Port Px VCC= 2.2 V, 3 V ±50 nA

(1) The leakage current is measured with VSSor VCCapplied to the corresponding pins, unless otherwise noted. (2) The port pin must be selected as input.

V(Px.y) (1 ≤ × ≤ 10, 0 ≤ y ≤ 7)

MIN MAX UNIT

MHz

5.9 Outputs – Ports P1 to P10

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

(1) The maximum total current, I (2) The maximum total current, I

High-level output voltage V

Low-level output voltage V

and I

voltage drop. voltage drop.

OH(max)

and I

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= –1.5 mA, VCC= 2.2 V

OH(max)

= –6 mA, VCC= 2.2 V

OH(max)

= –1.5 mA, VCC= 3 V

OH(max)

= –6 mA, VCC= 3 V

OH(max)

= 1.5 mA, VCC= 2.2 V

OL(max)

= 6 mA, VCC= 2.2 V

OL(max)

= 1.5 mA, VCC= 3 V

OL(max)

= 6 mA, VCC= 3 V

OL(max)

, for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified

OL(max)

, for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified

OL(max)

(1) (2) (1)

(2)

(1) (2) (1)

(2)

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VCC– 0.25 V

VCC– 0.6 V

VCC– 0.25 V

VCC– 0.6 V

VSS+ 0.25

V V V

SS SS SS

VSS+ 0.6

VSS+ 0.25

VSS+ 0.6

CC CC CC CC

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5.10 Output Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(Px.y)

(MCLK)

(SMCLK)

(ACLK)

(Xdc)

(1 ≤ × ≤ 10, 0 ≤ y ≤ 7) CL= 20 F, IL= ±1.5 mA MHz

P1.1/TA0/MCLK P1.4/TBCLK/SMCLK

CL= 20 pF MHz

P1.5/TACLK/ACLK VCC= 3 V DC 12

P1.5/TACLK/ACLK, CL= 20 pF, VCC= 2.2 V, 3 V

Duty cycle of output frequency

P1.1/TA0/MCLK, CL= 20 pF, VCC= 2.2 V, 3 V

P1.4/TBCLK/SMCLK, CL= 20 pF, VCC= 2.2 V, 3 V

VCC= 2.2 V DC 10 VCC= 3 V DC 12

VCC= 2.2 V 10

(ACLK)

(MCLK)

(SMCLK)

= f = f = f

= f = f

(LFXT1) (LFXT1) (LFXT1)

(XT1)

(DCOCLK)

= f

(XT2)

= f

(DCOCLK)

= f = f

(XT1)

(LF)

40% 60% 30% 70%

50%

40% 60%

50% – 50%+

15 ns 15 ns

50%

40% 60%

50% – 50% +

15 ns 15 ns

50%

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0.0

-5.0

-10.0

-15.0

-20.0

-25.0

0.0 0.5 1.0 1.5 2.0 2.5

T =25 CA°

T =85 CA°

V =2.2V P2.0

V High-LevelOutputVoltage V

- -

I -typicalHigh-LevelOutputCurrent-mA

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

I TypicalHigh-LevelOutputCurren mA

- -

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

V High-LevelOutputVoltage V

- -

T =25 CA°

T =85 CA°

V =3V P2.0

25.0

20.0

15.0

10.0

5.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5

V Low-LevelOutputVoltage V

– –

V =2.2V P2.0

T =25 CA°

T =85 CA°

I -TypicalLow-LevelOutputCurrent-mA

50.0

40.0

30.0

20.0

10.0

0.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

V Low-LevelOutputVoltage V

- -

I TypicalLow-LevelOutputCurrent mA

- -

V =3V P2.0

T =25 CA°

T =85 CA°

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.11 Typical Characteristics – Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

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Figure 5-2. Typical Low-Level Output Current vs Typical Low- Figure 5-3. Typical Low-Level Output Current vs Typical Low-

Figure 5-4. Typical High-Level Output Current vs Typical High- Figure 5-5. Typical High-Level Output Current vs Typical High-

Level Output Current Level Output Current

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.12 Wake-up Timing From LPM3

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f = 1 MHz 6

d(LPM3)

Delay time f = 2 MHz VCC= 2.2 V, 3 V 6 µs

f = 3 MHz 6

5.13 RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

VRAMh CPU halted

(1) This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution

should take place during this supply voltage condition.

(1)

1.6 V

5.14 LCD_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

CC(LCD)

LCD

PARAMETER TEST CONDITIONS V

Supply voltage

Supply current

(1)

Capacitor on LCDCAP

(3) (4)

Charge pump enabled (LCDCPEN = 1, VLCDx > 0000)

V VLCDx= 1000, all segments on, f no LCD connected

= 3 V, LCDCPEN = 1,

LCD(typ)

(2)

, TA= 25°C

Charge pump enabled (LCDCPEN = 1, VLCDx > 0000)

LCD

= f

/32, 2.2 V 3 µA

ACLK

LCD frequency 1.1 kHz

VLCDx = 0000 V VLCDx = 0001 2.60 VLCDx = 0010 2.66 VLCDx = 0011 2.72 VLCDx = 0100 2.78 VLCDx = 0101 2.84 VLCDx = 0110 2.90

LCD

LCD voltage

(4)

VLCDx = 0111 2.96 VLCDx = 1000 3.02 VLCDx = 1001 3.08 VLCDx = 1010 3.14 VLCDx = 1011 3.20 VLCDx = 1100 3.26 VLCDx = 1101 3.32 VLCDx = 1110 3.38 VLCDx = 1111 3.44 3.60

LCD

LCD driver output impedance 2.2 V 10 kΩ

(1) Refer to the supply current specifications I (2) Connecting an actual display increases the current consumption depending on the size of the LCD.

= 3 V, CPEN = 1,

LCD

VLCDx = 1000, I

for additional current specifications with the LCD_A module active.

(LPM3)

LOAD

= ±10 µΑ

(3) Enabling the internal charge pump with an external capacitor smaller than the minimum specified might damage the device. (4) Segments S0 through S3 are disabled when the LCD charge pump feature is enabled (LCDCPEN = 1) and, therefore, cannot be used

MIN TYP MAX UNIT

2.2 3.6 V

4.7 µF

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Voltage@0.5V node

Voltage@0.25V node

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5.15 Comparator_A

(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

(CC)

(Refladder/RefDiode)

(Ref025)

(Ref050)

CAON = 1, CARSEL = 0, CAREF = 0 µA

CAON = 1, CARSEL = 0, CAREF = (1, 2, 3), No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 1, No load at P1.6/CA0 and P1.7/CA1

PCA0 = 1, CARSEL = 1, CAREF = 2, No load at P1.6/CA0 and P1.7/CA1

2.2 V 25 40 3 V 45 60

2.2 V 30 50 3 V 45 71

2.2 V, 3 V 0.23 0.24 0.25

2.2 V, 3 V 0.47 0.48 0.5

PCA0 = 1, CARSEL = 1, CAREF = 3, 2.2 V 390 480 540

(RefVT)

Vp– V V

hys

(response LH)

(response HL)

Common-mode input voltage range

Offset voltage

(2)

Input hysteresis CAON = 1 2.2 V, 3 V 0 0.7 1.4 mV

(1) The leakage current for the Comparator_A terminals is identical to I (2) The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The

No load at P1.6/CA0 and P1.7/CA1, mV TA= 85°C

3 V 400 490 550

CAON = 1 2.2 V, 3 V 0 VCC– 1 V

2.2 V, 3 V –30 30 mV

TA= 25°C, Overdrive 10 mV, without filter: CAF = 0

TA= 25°C, Overdrive 10 mV, without filter: CAF = 1

TA= 25°C, Overdrive 10 mV, without filter: CAF = 0

TA= 25°C, Overdrive 10 mV, without filter: CAF = 1

lkg(Px.x)

specification.

2.2 V 160 210 300 3 V 80 150 240

2.2 V 1.4 1.9 3.4 3 V 0.9 1.5 2.6

2.2 V 130 210 300 3 V 80 150 240

2.2 V 1.4 1.9 3.4 3 V 0.9 1.5 2.6

two successive measurements are then summed together.

MIN TYP MAX UNIT

µA

µs

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Overdrive

VCAOUT

t(response)

V+

V-

400mV

CAON

V+

CAF

Low-PassFilter

t »2µ

ToInternal Modules

SetCAIFG Flag

CAOUT

V-

VCC

0V

650

600

550

500

450

400

-45 -25

-5

15 35

55 75

T Free-AirTemperature C

- - °

V ReferenceVoltage mV

REF

- -

V =3V

Typical

650

600

550

500

450

400

-45 -25

-5

15 35

55 75

T Free-AirTemperature C

- - °

V ReferenceVoltage mV

REF

- -

V =2.2V

Typical

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5.16 Typical Characteristics – Comparator_A

SLAS508J –APRIL 2006–REVISED JUNE 2015

Figure 5-6. Reference Voltage vs Free-Air Temperature Figure 5-7. Reference Voltage vs Free-Air Temperature

Figure 5-8. Block Diagram of Comparator_A Module

Figure 5-9. Overdrive Definition

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CC(drop)

3V

0.5

1.5

0.001 1 1000

TypicalConditions

1ns 1ns

t -PulseWidth-

s t -PulseWidth-

V =3V

V -V

CC(drop)

d(BOR)

(B_IT-)

hys(B_IT-)

CC(start)

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.17 POR, BOR

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

d(BOR)

CC(start)

(B_IT–)

hys(B_IT–)

(reset)

Brownout

(2) (3)

(1) The current consumption of the brownout module is already included in the ICCcurrent consumption data. (2) The voltage level V (3) During power up, the CPU begins code execution following a period of t

(B_IT–)

+ V

hys(B_IT–)

must not be changed until VCC≥ V MSP430x4xx Family User’s Guide (SLAU056) for more information on the brownout and SVS circuit.

dVCC/dt ≤ 3 V/s (see Figure 5-10) V

(B_IT– )

dVCC/dt ≤ 3 V/s (see Figure 5-10 through Figure 5-

12)

dVCC/dt ≤ 3 V/s (see Figure 5-10) 70 130 210 mV Pulse duration needed at RST/NMI pin to accepted

reset internally, VCC= 2.2 V, 3 V

2 µs

≤ 1.89 V.

CC(min)

, where V

after VCC= V

is the minimum supply voltage for the desired operating frequency. See the

CC(min)

d(BOR)

(B_IT–)

+ V

. The default FLL+settings

hys(B_IT–)

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(1)

2000 µs

0.7 ×

1.79 V

Figure 5-11. V

CC(drop)

Level with a Square Voltage Drop to Generate a POR or BOR Signal

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Figure 5-10. POR, BOR vs Supply Voltage

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0.5

1.5

CC(drop)

tpw-PulseWidth-ms

CC(d ro p )

- V

3V

0.001 1 1000

tpw-PulseWidth-ms

t =t

f r

TypicalConditions

V =3V

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Figure 5-12. V

CC(drop)

Level With a Triangle Voltage Drop to Generate a POR or BOR Signal

5.18 SVS (Supply Voltage Supervisor and Monitor)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(SVSR)

d(SVSon)

settle

(SVSstart)

hys(SVS_IT–)

(SVS_IT–)

(3)

CC(SVS)

(1) t (2) The recommended operating voltage range is limited to 3.6 V.

(3) The current consumption of the SVS module is not included in the ICCcurrent consumption data.

is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD

settle

value from 2 to 15. The overdrive is assumed to be > 50 mV.

dVCC/dt > 30 V/ms (see Figure 5-13) 5 150 dVCC/dt ≤ 30 V/ms 2000 SVS on, switch from VLD = 0 to VLD ≠ 0, VCC= 3 V 150 300 µs

(1)

VLD ≠ 0 VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-13) 1.55 1.7 V

VCC/dt ≤ 3 V/s (see Figure 5-13)

VCC/dt ≤ 3 V/s (see Figure 5-13), external voltage applied on A7

VCC/dt ≤ 3 V/s (see Figure 5-13)

VCC/dt ≤ 3 V/s (see Figure 5-13), external voltage applied on A7

VLD ≠ 0, VCC= 2.2 V, 3 V 10 15 µA

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VLD = 1 70 120 155 mV VLD = 2 to 14

VLD = 15 4.4 20 mV VLD = 1 1.8 1.9 2.05

VLD = 2 1.94 2.1 2.23 VLD = 3 2.05 2.2 2.35 VLD = 4 2.14 2.3 2.46 VLD = 5 2.24 2.4 2.58 VLD = 6 2.33 2.5 2.69 VLD = 7 2.46 2.65 2.84 VLD = 8 2.58 2.8 2.97 VLD = 9 2.69 2.9 3.10 VLD = 10 2.83 3.05 3.26 VLD = 11 2.94 3.2 3.39 VLD = 12 3.11 3.35 3.58 VLD = 13 3.24 3.5 3.73 VLD = 14 3.43 3.7

VLD = 15 1.1 1.2 1.3

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(SVS_IT–)

× 0.001 × 0.016

(SVS_IT–)

(2)

3.96

µs

12 µs

(2) (2) (2)

0.5

1.5

1ns 1ns

tpw-PulseWidth-ms

3V

1 10 1000

t-PulseWidth-ms

100

3V

t =t

f r

RectangularDrop

TriangularDrop

CC(drop)

CC(d ro p )

- V

CC(drop)

CC(start)

(B_IT-)

Brownout

Region

(SVSstart)

(SVS_IT-)

SoftwareSetsVLD>0:

SVSis Active

d(SVSR)

undefined

hys(SVS_IT-)

d(BOR)

Brownout

d(SVSon)

d(BOR)

SetPOR

Brown

Out

Region

SVSCircuitis ActiveFromVLD>toVCC<V(B_IT-)

SVSOut

Vhys(B_IT-)

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Figure 5-13. SVS Reset (SVSR) vs Supply Voltage

Figure 5-14. V

CC(drop)

with a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal

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T -

CV -V

1.8 3.0

2.4 3.6

1.0

20 6040 85

1.0

0-20-400

(DCO)

(DCO3V)

(DCO)

(DCO20 C)°

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.19 DCO

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

= 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,

(DCOCLK)

(DCO = 2)

(DCO = 27)

(DCO = 2)

(DCO = 27)

(DCO = 2)

(DCO = 27)

(DCO = 2)

(DCO = 27)

(DCO = 2)

(DCO = 27)

(DCO)

DCOPLUS = 0

2.2 V, 3 V 1 MHz

FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1 MHz

FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1 MHz

FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1 MHz

FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1 MHz

FN_8 = 1, FN_4 = 1 = FN_3 = FN_2 = x, DCOPLUS = 1 MHz

Step size between adjacent DCO taps: Sn= f

DCO(Tap n+1)/fDCO(Tap n)

Temperature drift, N FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0

Drift with VCCvariation, N FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0

(see Figure 5-16 for taps 21 to 27)

= 01Eh,

(DCO)

= 01Eh,

(DCO)

1 < TAP ≤ 20 1.06 1.11

2.2 V 0.3 0.65 1.25

3 V 0.3 0.7 1.3

2.2 V 2.5 5.6 10.5

3 V 2.7 6.1 11.3

2.2 V 0.7 1.3 2.3

3 V 0.8 1.5 2.5

2.2 V 5.7 10.8 18

3 V 6.5 12.1 20

2.2 V 1.2 2 3

3 V 1.3 2.2 3.5

2.2 V 9 15.5 25

3 V 10.3 17.9 28.5

2.2 V 1.8 2.8 4.2

3 V 2.1 3.4 5.2

2.2 V 13.5 21.5 33

3 V 16 26.6 41

2.2 V 2.8 4.2 6.2

3 V 4.2 6.3 9.2

2.2 V 21 32 46

3 V 30 46 70

TAP = 27 1.07 1.17

2.2 V –0.2 –0.3 –0.4

3 V –0.2 –0.3 –0.4

MIN TYP MAX UNIT

0 5 15 %/V

%/°C

Figure 5-15. DCO Frequency vs Supply Voltage VCCand vs Ambient Temperature

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DCOFrequency AdjustedbyBits 2 to2 inSCFI1{N }

9 5

{DCO}

FN_2=0 FN_3=0 FN_4=0 FN_8=0

FN_2=1 FN_3=0 FN_4=0 FN_8=0

FN_2=x FN_3=1 FN_4=0 FN_8=0

FN_2=x FN_3=x FN_4=1 FN_8=0

FN_2=x FN_3=x FN_4=x

FN_8=1

Legend

ToleranceatTap27

ToleranceatTap2

OverlappingDCORanges: UninterruptedFrequencyRange

(DCO)

1 2720

1.11

1.17

DCOTap

Sn - S te p s iz e Ratio b et w een D C O Ta p s

Min

Max

1.07

1.06

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Figure 5-16. DCO Tap Step Size

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Figure 5-17. Five Overlapping DCO Ranges Controlled by FN_x Bits

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SLAS508J –APRIL 2006–REVISED JUNE 2015

5.20 Crystal Oscillator, LFXT1 Oscillator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

OSCCAPx = 0h, VCC= 2.2 V, 3 V 0

V V

XIN

XOUT

IL IH

Integrated input capacitance

Integrated output capacitance

Low-level input voltage at XIN VCC= 2.2 V, 3 V High-level input voltage at XIN VCC= 2.2 V, 3 V

(3)

(1) The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is

× C

) / (C

+ C

XIN

(2) To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.

XOUT

XIN

). This is independent of XTS_FLL.

XOUT

• Keep the trace between the MCU and the crystal as short as possible.

• Design a good ground plane around the oscillator pins.

• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.

• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.

• If conformal coating is used, ensure that it does not induce capacitive or resistive leakage between the oscillator pins.

• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter.

(3) TI recommends external capacitance for precision real-time clock applications; OSCCAPx = 0h. (4) Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.

OSCCAPx = 1h, VCC= 2.2 V, 3 V 10 OSCCAPx = 2h, VCC= 2.2 V, 3 V 14 OSCCAPx = 3h, VCC= 2.2 V, 3 V 18 OSCCAPx = 0h, VCC= 2.2 V, 3 V 0 OSCCAPx = 1h, VCC= 2.2 V, 3 V 10 OSCCAPx = 2h, VCC= 2.2 V, 3 V 14 OSCCAPx = 3h, VCC= 2.2 V, 3 V 18

(4) (4)

0.8 × V

SS CC

(1) (2)

0.2 × V

V V

5.21 Crystal Oscillator, XT2 Oscillator

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

XT2IN

XT2OUT

(1) The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer. (2) Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.

Integrated input capacitance VCC= 2.2 V, 3 V 2 pF Integrated output capacitance VCC= 2.2 V, 3 V 2 pF

Input levels at XT2IN

VCC= 2.2 V, 3 V

(2)

0.8 × V

(1)

0.2 × V

5.22 USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS V

Internal: SMCLK, ACLK

USCI

BITCLK

USCI input clock frequency External: UCLK f

Duty cycle = 50% ±10%

BITCLK clock frequency (equals baud rate in MBaud)

UART receive deglitch time UART

(1)

2.2 V, 3 V 1 MHz

2.2 V 50 150 600 3 V 50 100 600

(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

MIN TYP MAX UNIT

SYSTEM

V V

MHz

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MSP430FG4619,MSP430FG4618,MSP430FG4617,MSP430FG4616 MSP430CG4619, MSP430CG4618, MSP430CG4617, MSP430CG4616

SLAS508J –APRIL 2006–REVISED JUNE 2015

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5.23 USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-18 and Figure 5-19)

USCI

SU,MI

HD,MI

VALID,MO

PARAMETER TEST CONDITIONS V

USCI input clock frequency f

SMCLK, ACLK Duty cycle = 50% ±10%

SOMI input data setup time ns

iSOMI input data hold time ns

SIMO output data valid time UCLK edge to SIMO valid, CL= 20 pF ns

2.2 V 110 3 V 75

2.2 V 0 3 V 0

2.2 V 30 3 V 20

MIN MAX UNIT

SYSTEM

5.24 USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-20 and Figure 5-21)

STE,LEAD

STE,LAG

STE,ACC

STE,DIS

SU,SI

HD,SI

VALID,SO

PARAMETER TEST CONDITIONS V

STE lead time STE low to clock

STE lag time Last clock to STE high

STE access time STE low to SOMI data out

STE disable time STE high to SOMI high impedance

SIMO input data setup time ns

SIMO input data hold time ns

SOMI output data valid time UCLK edge to SOMI valid, CL= 20 pF ns

2.2 V, 3 V 50 ns

2.2 V, 3 V 10 ns

2.2 V, 3 V 50 ns

2.2 V 20 3 V 15

2.2 V 10 3 V 10

2.2 V 75 110 3 V 50 75

MIN TYP MAX UNIT

MHz

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MSP430CG4618 MSP430CG4617 MSP430CG4616

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Texas Instruments MSP430FG4618, MSP430FG4617, MSP430FG4619, MSP430CG4618, MSP430FG4616 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual