Texas Instruments ISO5852SDWEVM-017 User Manual

User's Guide

SLLU298–May 2018

ISO5852SDW Driving and Protecting SiC and IGBT Power

Modules

This user's guide describes the characteristics, operation, and use of the ISO5852SDWEVM-017 Evaluation Module (EVM). This TI EVM provides driving and protection for popular Silicon Carbide (SiC) MOSFET and Si IGBT Power Modulues. A complete schematic diagram, printed-circuit board layouts, and bill of materials are included in this document.

Contents

1 Overview...................................................................................................................... 3

1.1 Features.............................................................................................................. 3

1.2 Applications.......................................................................................................... 3

1.3 Description........................................................................................................... 4

2 Test Setup and Results ..................................................................................................... 9

2.1 Before You Begin .................................................................................................. 9

2.2 Equipment ......................................................................................................... 10

3 Board Layout................................................................................................................ 18

4 Schematic and Bill of Materials........................................................................................... 25

4.1 Schematic .......................................................................................................... 25

4.2 Bill of Materials .................................................................................................... 31

List of Figures

1 ISO5852SDWEVM-017 EVM Block Diagram............................................................................ 6

2 ISO5852SDWEVM-017 Top View......................................................................................... 8

3 ISO5852SDWEVM-017 Mounted on Top of Power Module ........................................................... 9

4 Power Up and Bias Supply Voltages VU and VL Test Setup ........................................................ 11

5 Test Setup for Input and Output Switching Waveforms............................................................... 12

6 Major Input and Output Waveforms Using Output Overlapping Prevention Feature.............................. 14

7 Thermistor Amplifier Test Setup.......................................................................................... 15

8 Input Bus Voltage Sense Amplifier Test Setup......................................................................... 16

9 Safety Isolated Regions between High and Low Voltage Board Areas............................................. 17

10 Top View of the Board..................................................................................................... 18

11 Bottom View Of The Board ............................................................................................... 19

12 Component Placement .................................................................................................... 20

13 Top Layer ................................................................................................................... 21

14 Signal Layer 1 .............................................................................................................. 22

15 Signal Layer 2 .............................................................................................................. 23

16 Bottom Layer................................................................................................................ 24

17 Electrical Schematic of ISO5852SDWEVM-017 ....................................................................... 26

18 Electrical Schematic with Functional Blocks Outlined................................................................. 27

19 Waveforms with Overlapping Enabled .................................................................................. 28

20 Rise Time and Propagation Delay Waveforms with 10 nF Load .................................................... 29

21 Fall Time and Propagation Delay Waveforms with 10 nF Load...................................................... 30

SLLU298–May 2018

Submit Documentation Feedback

List of Tables

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

1 Electrical Specifications..................................................................................................... 4

2 Voltages and Current During Power Up Test........................................................................... 12

3 Function Generator Settings.............................................................................................. 13

4 Oscilloscope Settings...................................................................................................... 13

5 Themistor Amplifier Output Signals...................................................................................... 15

6 Input Bus Voltage Sense Amplifier Outputs ............................................................................ 16

7 Bill of Materials ............................................................................................................. 31

Trademarks

All trademarks are the property of their respective owners.

www.ti.com

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Submit Documentation Feedback

SLLU298–May 2018

www.ti.com

1 Overview

The ISO5852SDWEVM-017 is a compact, dual channel isolated gate driver board providing drive, bias voltages, protection and diagnostic needed for half-bridge SiC MOSFET and Si IGBT Power Modules housed in 150-mm × 62-mm × 17-mm packages.

This TI EVM is based on 5.7-kVrms reinforced isolation driver IC ISO5852SDW in SOIC-16DW package with 8.0 mm creepage and clearance. The EVM includes SN6505B based isolated DC-DC transformer bias supplies.

Isolated temperature and input rail monitoring is provided by 5-kVrms isolated amplifiers AMC1301. Compact form factor 100-mm × 62-mm × 6.6-mm, excluding connector height, allows direct connection to

standard 62-mm half-bridge modules.

1.1 Features

This EVM supports the following features:

• 20-A peak split sink and source drive current to optimize turn on and turn off switching time

• Two, 2-W output bias supplies with undervoltage lockout (UVLO) and overvoltage lockout (OVLO)

protection

• Turn ON and turn OFF drive voltages can be programmed independently from 12 V to 21 V and from

–3.3 V to –7 V respectively by using two input supplies from 3.3 V to 5.3 V

• Robust noise-immune solution with CMTI >100 V/ns

• Supports 5-kVrms Reinforced Isolation for input rail up to 1700-V

• Programmable Short-circuit sensing and Soft Turn-OFF protection by de-saturation circuit

• 2-A Active Miller Clamp

• Output Short Circuit Clamp

• Fault feedback with reset

• Temperature and input rail monitoring

Overview

1.2 Applications

This EVM is used in the following applications:

• Solar inverters

• Motor drives

• HEV and EV chargers

• Wind turbines

• Transportation

• UPS

SLLU298–May 2018

Submit Documentation Feedback

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Overview

1.3 Description

Compact driver board ISO5852SDWEVM-017 supports SiC power modules by reducing parasitics, minimizing switching loss and EMI and providing full required protection and diagnostics features.

1.3.1 Specification

Electrical parameters of the board are shown in Table 1.

SUPPLY VOLTAGES AND CURRENTS

VCC Primary supply voltage 4.5 5.0 5.5 V IVCCQ Primary quiescent current IN+, IN- low 30 mA

IVCCS Primary supply current VCCUR Vcc rising UVLO threshold 4.5 4.6 V

VCCUF Vcc falling UVLO threshold 4.2 4.3 V VCCUH Vcc UVLO hysteresis 0.2 V VCCOR Vcc rising OVLO threshold 5.7 5.8 V VCCOF Vcc falling OVLO threshold 5.4 5.5 V VCCOH Vcc UVLO hysteresis 0.2 V VCC2U,

VCC2L VCC2U,

VCC2L

DRIVE CURRENT AND POWER

IOH Peak source current CLOAD = 10nF 15 20 A IOL Peak sink current CLOAD = 10nF 15 20 A PDRV Drive power per channel At 25⁰C 2.0 W

INPUT/OUTPUT SIGNALS

VINR, VRSTR INL+, INU+, RST rising threshold

VINF, VRSTF INL+, INU+, RST falling threshold

VINH, VRSTH INL+, INU+, RST hysteresis VFLU, VFLL FL, FU Fault voltage IFLT = 5 mA 0.2 V VFLU, VFLL FL, FU Fault current VFLTH F high level At VCC = 4.5 V 4.4 4.5 V

VFLTL F low level At VCC = 4.5 V 0.1 V ATEMP Thermistor monitor gain 8.2 ARAIL Input rail monitor gain 8.2

TIMING PARAMETERS

TRISE Drive output rise time CLOAD = 10nF 30 ns TFALL Drive output fall time CLOAD = 10nF 34 ns TPROP Propagation delay CLOAD = 100nF 130 150 ns TSKEW Pulse skew 20 ns TGLITCH Input glitch filter 20 30 40 ns TUVLO UVLO recovery delay 50 µs TOVOL OVLO recovery delay 50 µs

Turn ON drive voltages

Turn OFF drive voltages

www.ti.com

Table 1. Electrical Specifications

PARAMETER TEST CONDITION MIN NOM MAX UNIT

FSW = 10kHz, CLOAD = 10nF

Transformer 750342879

Transformer 750313734

Internal pullup current

15 17 19 V

–5.9 –5 –4.7 V

0.3 × VCC

210 mA

0.7 × VCC

0.15 × VCC

100

µA

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Submit Documentation Feedback

SLLU298–May 2018

www.ti.com

Overview

Table 1. Electrical Specifications (continued)

PARAMETER TEST CONDITION MIN NOM MAX UNIT

SHORT CIRCUIT PROTECTION

Can be

VDESAT Nominal desaturation threshold

TDESATBLN K

TDS90 Response time to 90% VOUTHL CLOAD = 10nF 553 760 ns TDS10 Response time to 10% VOUTHL CLOAD = 10nF 2 3.5 µs ICHARGE Capacitor charge current 0.42 0.5 0.58 mA IDISCHARGE Capacitor discharge current 9 14 mA VCLAMP Miller clamp threshold 1.6 2.1 2.5 V ICLAMP Miller clamp current 4 A

ISOLATION

CMTI CMTI 100 V/ns VISO Withstand isolation voltage Reinforced, 60s 5.0 kVrms CI Barrier capacitance 20 pF TA Operating Ambient Temperature -40 25 125 oC

SIZE

Board size Without connector 100 x 62 x 6.6 mm

Blanking time 310 400 480 ns

programmed by resistors down to 4 V

8.3 9.0 9.5 V

SLLU298–May 2018

Submit Documentation Feedback

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Inv Rec

+15 V

Vdrp1 S2 Vdrn1

DC-DC

Rx Tx

GND1 V

EE2

RST

RDY

FLT

IN+

IN±

CC1

CC2

DESAT

GND2

OUTH

OUTL

CLAMP

CC1

UVLO1

Mute

Decoder

Q S

CC1

Gate Drive

and

Encoder

Logic

UVLO2

2 V

9 V

500 µA

STO

CC2

Ready

Fault

GND1 V

EE2

RST

RDY

FLT

IN+

IN±

CC1

CC2

DESAT

GND2

OUTH

OUTL

CLAMP

CC1

UVLO1

Mute

Decoder

Q S

CC1

Gate Drive

and

Encoder

Logic

UVLO2

2 V

9 V

500 µA

STO

CC2

Ready

Fault

10 

Vdrp2

Vdrn1

Logic Block

Inv Rec

+15 V

Vdrp1 S1 Vdrn1

DC-DC

Rx Tx

Reinforced Isolation

10 

5 V

AMC1301

Vdrn2

±5 V

Vdrp1

BUS_P

BUS_N

VCC_5V

GND

INU+

RST

INL+

TRO_P

TRO_N

TR_N

TR_P

± 5 V

Overview

1.3.2 Block Diagram

The ISO5852SDWEVM-017 board block diagram is shown in Figure 1.

www.ti.com

Figure 1. ISO5852SDWEVM-017 EVM Block Diagram

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

SLLU298–May 2018

Submit Documentation Feedback

www.ti.com

It includes two isolated channels with the following key functional blocks:

• 20A source/sink 5.7 kVrms Isolated driver using ISO5852SDW driver IC

• Split rail bias supply using two 424 kHz transformer drivers SN6505B to generate separately +17 V rail for turn ON and -5 V rail for turn OFF

• Input logic block with shoot-through prevention

• Output protection and diagnostic block

• Analog amplifiers AMC1301 to monitor temperature inside the module and input voltage rail with 5.0 kVrms isolation

1.3.3 Isolated Gate Driver ISO5852S

ISO5852SDW, isolated driver in SOIC-16DW package with 8.0mm creepage and clearance providing

5.7kVrms reinforced isolation, includes all main short circuit protection features. ISO5852SDW driver IC

employs TI proprietary high voltage, low propagation delay, CMTI immune capacitive isolation technology. The list of isolation safety certifications from agencies like VDE, CSA, UL and CQC is provided in related datasheet. Short, 76 ns propagation delay with only 20 ns skew allows accurate control of power devices.

Figure 1 includes block diagram of ISO5852SDW driver.

Primary side voltage Vcc1 is controlled by internal UVLO1 circuit with 2.25Vmax rising threshold and

1.7Vmin falling threshold. Inverting and non-inverting input signals IN- and IN+ have CMOS thresholds

derived from Vcc1 voltage: 0.7 x Vcc1 max rising and 0.3 x Vcc1 min falling accordingly. Secondary side voltage Vcc2 can go up to 35V abs. max. Turn ON drive voltage between Vcc2 and GND2 pins is controlled by internal UVLO2 circuit with 13Vmax rising threshold and 9.5V min falling threshold. The split sink/source output allows setting optimal turn ON and turn OFF time by selecting separate gate resistors between driver output and gate of power device. This driver has all necessary short circuit protection features including desaturation current sensing, soft short circuit turn OFF, Miller gate clamp, fault, power ready and reset signals.

Overview

1.3.4 Split-Rail Bias Supply using SN6505B

Split rail bias supply generates 17V turn ON, and -5V turn OFF voltages using two push-pull transformer drivers SN6505B operating at 424kHz and housed in 6-pin small SOT-23 package.

The SN6505B is supplied through Vcc terminal from external source in the range from 2.25 to 5.5V. Input voltage is controlled by UVLO circuit having rising threshold 2.25Vmax and falling threshold 1.7V min. Internal oscillator operates at 424kHz typical frequency within range from 363 kHz min. to 517 kHz max.. The SN6505 employs spread spectrum clocking technique to minimize EMI. The output stage includes 1A push-pull switches rated up to 16 V abs. max. The switches are protected by current limit circuit tripped at

1.7 A typ. level. The device also protected by thermal shutdown circuit triggered at 168 ºC typical

threshold and returning back to normal operation at 150 ºC typical. Additional features include soft start and Enable signal. Because there is no closed feedback loop in this inexpensive bias supply solution, it operates like DC-DC transformer and requires low tolerance primary voltage to maintain output voltages within ±10% range.

1.3.5 Input Logic

Input logic block fulfills the following functions:

• Provides additional UVLO and OVLO protection of secondary side drive voltages using sensing on primary side Vcc based on window comparator TPS3700

• Generates separate fault signals for each channel when the short circuit occurs along with general system fault signal using AND logic CMOS IC SN74AHC1G08QDBVRQ1

• Generates combined Reset signal output for both isolated channels

• Provides isolated differential output signals from temperature and input rail monitoring circuits using isolated amplifiers AMC1301

• Can be set for driver outputs overlapping prevention mode by having shunt resistors R48 and R52 in place. To allow outputs overlapping simply remove shunt resistors R48 and R52.

SLLU298–May 2018

Submit Documentation Feedback

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Overview

1.3.6 Output Protection and Diagnostic

The output boost and protection blocks fulfill the following functions:

• Boost sink and source currents up to 20 A typical

• Determine short circuit conditions using Vds sensing

• Provide analog isolated input rail sensing signal using AMC1301 amplifier

• Provide analog isolated temperature monitoring using thermistor inside the module and AMC1301 amplifier

1.3.7 Isolated Differential Amplifier AMC1301

The AMC1301 is a precision, isolated amplifier with an output separated from the input circuitry by an isolation barrier providing protection from electromagnetic and electrical noise in the system.

The input of the AMC1301 device is optimized for sensing signals in ±250 mV range with high immunity to common mode noise. The amplifier is housed in wide body SOIC-8DWV package with 9 mm creepage and clearance.

1.3.8 Board Views

Top view of the driver board ISO5852SDWEVM-017 is shown in Figure 2. Figure 3 shows the driver EVM soldered on top of power module.

www.ti.com

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Figure 2. ISO5852SDWEVM-017 Top View

Submit Documentation Feedback

SLLU298–May 2018

www.ti.com

Test Setup and Results

Figure 3. ISO5852SDWEVM-017 Mounted on Top of Power Module

2 Test Setup and Results

Test setup and related waveforms presented in User's Guide are for ISO5852SDWEVM-017 EVM EXCLUDING any user provided power modules attached to backside of the EVM. Capacitive load presented by power module is emulated by 10 nF capacitors C16 and C36. When EVM is attached to and evaluated with power module, capacitors C16 and C36 should be removed.

2.1 Before You Begin

When starting to evaluate and test the ISO5852SDWEVM-017 EVM, it will typically be in a stand-alone configuration, separate from power module. This EVM does not internally generate high voltages or high temperatures.

In the start-up configuration, there will be no high voltage or high temperature capable of presenting the user with an electrical shock hazard or burn resulting from elevated temperature risks provided the EVM is used within its electrical load rating limits established in Table 1.

To minimize risk of electric shock hazard always follow safety practices normally followed in a development laboratory. Refer to TI’s EVM High Voltage guideline accompanying this EVM.

WARNING

However, to evaluate isolated input rail amplifier voltages in accordance with the described below test procedure 2.2.4, which requires the addition of an external power source with maximum rating of 300 VDC, high voltage may be accessible between board test points DU and SL.

SLLU298–May 2018

Submit Documentation Feedback

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Test Setup and Results

To minimize risk of electrical shock hazard, always follow all high voltage safety rules and regulations while operating electrical equipment!

When evaluating ISO5852SDWEVM-017 with EVM attached to its intended vendor provided power module as part of the system level measurements and assessments, the power module will have accessibility of high voltage and high temperatures that impact the EVM’s operating conditions as well. High voltages with transients up to 1500Vpk can appear between isolated areas of the EVM, bounded as illustrated in Figure 9. The externally provided power module also radiates heat that indirectly provides air flow and convection that can elevate the temperature of EVM board.

The EVM provides isolated thermal dissipation diagnostic signals available at connector J1 shown in

Figure 9, which measure high voltage input rail and thermistor temperatures inside the external power

module. Both BUS_P (pin 17) to BUS_N (pin 18) and TRO_P (pin 20) to TRO_N (pin 19) diagnostic signals must be strictly monitored to assure both high voltage and thermal protective features are being utilized.

The user is required to provide necessary interface controller hardware to shut down and deenergize the system immediately if BUS_P to BUS_N signal exceeds 1.85 VDC, or signal TRO_P to TRO_N drops below 0.135 VDC.

www.ti.com

WARNING

To minimize risk of fire hazard, it is critical to assure that the external power module’s electrical and thermal ratings are never exceeded as published by the external power module’s manufacturer’s datasheet, and the maximum temperature of any external power module should never exceed 130oC.

2.2 Equipment

• Power Supplies – At least up to 6-V and 1-A power supply for powering EVM, for example: BK Precision, series 1715 – At least up to 300-V and 10-mA power source for testing bus isolated sense amplifier within EVM

• Function Generator and accessories – One 2-channel function generator, for example: Tektronix AFG3102 – Two standard 50-Ω BNC coaxial cables – Two 50-Ω BNC male to female feed-thru terminators, for example: Tektronix 011-0049-02

• Oscilloscope and accessories – Oscilloscope 500-MHz or higher with at least 4 channels, for example: Tektronix DPO7104 – Four at least 500-MHz bandwidth passive voltage probes, for example: P6139A

• Six Digital Multi-Meters (DMM), for example Fluke 187

• Other – 20-wire flat cable with receptacle 71600-120LF from FCI with opposite end wired to PCB with

related test points – Wires 7 to 10 inch long with clips on both ends to make jumpers on some test points – Resistance decade box, for example 72-7270 from Tenma

Test procedure includes four main tests with different test setups

1. Power up and bias supply voltages test

2. Input and output pulse switching waveforms test

3. Thermistor isolated amplifier input and output signal test

4. Bus voltage sense isolated amplifier input and output signal test

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Submit Documentation Feedback

SLLU298–May 2018

www.ti.com

All test setups shown in the following figures assume the flat test cable with receptacle and test points is attached to the connector J1 of the EVM.

2.2.1 Power UP Test

Test setup for power up test is shown in Figure 4. For these tests digital multi-metersfor DC voltage measurements are set auto-range. MM1 is set for DC current measurements with expected range up to 500 mA. Here and in all test setups below, red arrows indicate positive terminals and black arrows indicate return terminal.

Test Setup and Results

Figure 4. Power Up and Bias Supply Voltages VU and VL Test Setup

Before start testing make sure to follow all electrical safety and ESD protection requirements implemented at your company!

1. Enable power supply PS1

2. Gradually increase the voltage at PS1 and monitor voltage using MM4 and current using MM1

3. Verify measured voltage and current in accordance to Table 2. If current or voltage is outside the specified range, stop increasing the voltage at PS1 and return to initial stage

4. Gradually reduce the voltage at PS1 to 0 V and disable it

SLLU298–May 2018

Submit Documentation Feedback

WARNING

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Test Setup and Results

Measured voltages and current should be within range shown in Table 2.

Table 2. Voltages and Current During Power Up Test

MM4 (Vcc) MM1 (Icc) MM2 (+VU) MM3 (-VU) MM5 (+VL) MM6 (-VL)

2.95 V – 3.05 V < 30 mA < ±0.1 V < ±0.1 V < ±0.1 V < ±0.1 V

4.65 V – 4.75 V 130 mA – 145 mA 15.5 V – 16.5 V 4.5 V – 5.2 V 15.4 V – 16.4 V 4.5 V – 5.2 V

4.95 V – 5.05 V 135 mA – 150 mA 16.8 V – 17.5 V 5.0 V – 5.5 V 16.6 V – 17.4 V 5.0 V – 5.5 V

5.4 V – 5.45 V 140 mA – 155 mA 17.5 V – 19.0 V 5.5 V – 6.2 V 17.3 V – 18.8 V 5.5 V – 6.2 V

5.7 V < MM4 < 6 V < 30 mA < ±0.1 V < ±0.1 V < ±0.1 V < ±0.1 V

2.2.2 Input and Output Switching Waveforms Test

Test setup for switching waveforms is shown in Figure 5.

www.ti.com

Figure 5. Test Setup for Input and Output Switching Waveforms

ISO5852SDW Driving and Protecting SiC and IGBT Power Modules

Submit Documentation Feedback

SLLU298–May 2018

+ 25 hidden pages

Texas Instruments ISO5852SDWEVM-017 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual