GC5328 Low-Power Wideband Digital Predistortion Transmit Processor
Check for Samples: GC5328
1
FEATURES
•Integrated DUC, CFR, and DPD Solution•Supports Direct Interface to TI High-Speed
•20-MHz Max. Signal Bandwidth, Based on Max.
DPD Clock of 200 Mhz, Fifth-Order Correction
•DUC: Up to 12 CDMA2000/TDSCDMA, 4
W-CDMA, 2–10 MHz or 1–20 MHz OFDMA
Carriers
•CFR: Typically Meets 3GPP TS 25.141 < 6.5 dB
PAR, < 8.5 dB PAR for OFDMA Signals
•DPD: Short-Term Memory Compensation,
Typical ACLR Improvement > 20 dB
•GC5328IZER PBGA Package, 23 mm × 23 mm
•1.2-V Core, 1.8-V HSTL, 3.3-V I/O
•2.5-W Typical Power Consumption
•TMS320C6727 DPD Optimization Software
Data Converters
APPLICATIONS
•3 GPP (W-CDMA) Base Stations
•3 GPP2 (CDMA2000) Base Stations
•WiMAX, WiBRO, and LTE (OFDMA) Base
Stations
•Multicarrier Power Amplifiers (MCPAs)
DESCRIPTION
The GC5328 is a lower-power version of the GC5322 wideband digital predistortion transmit processor. The
GC5328 includes a digital upconverter (DUC) block, a crest factor reduction (CFR) block, a digital predistortion
(DPD) block, feedback (FB) block, and capture buffer (CB) blocks.
The GC5328 GPP block receives the interleaved IQ data from the baseband input. The individual IQ channels
are gain-adjusted in the GPP and routed to the DUC. The GPP and DUC can be bypassed to input a combined
IQ signal. The DUC provides three stages of interpolation and a complex mixer. There are two DUC blocks. The
output from the DUC blocks is combined in the sum chain. Each of the 1 to 12 DUC channels can be summed,
and the composite signal can be scaled.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
The CFR block has four serial stages of peak detection and cancellation. The CFR block cancellation filter can
be programmed as real or complex. The CFR peak-reduced output is routed to the Farrow resampler. The
Farrow resampler resamples the CFR output to the DPD clock rate. The Farrow resampler block also has a
complex mixer for composite carrier frequency offset.
The DPD subsystem has a circular limiter, nonlinear DPD correction, and a transmit equalizer. The DPD
correction can reduce the follow-on circuitry distortion products. The DPD output is sent to the BUC. The BUC
provides a post-DPD interpolation, and also provides a complex mixer for frequency offset. The DAC interface
converts the BUC signal output to the interleaved IQ or parallel IQ output signals for the DAC5682Z or DAC5688.
The CB block captures the selected internal reference signal, and the feedback block in two up to 4K capture
buffers. The signal capture can be based on an externally timed event (standard capture buffer), delay after a
timed event, or signal statistics (smart capture buffer). Normally the DPD input and feedback output are selected.
The capture buffers are stored and read by the microprocessor.
The FB block receives the LVDS ADC information and performs signal processing to downconvert the received
signal to 0IF. The FB block also has a feedback-path receive equalizer.
The GC5328 is a flexible transmit sector processor that includes a digital upconverter (DUC) block, a crest factor
reduction (CFR) block, and a digital predistortion (DPD) block and its associated feedback chain. The GC5328
processes composite input bandwidths of up to 20 MHz and processes DPD expansion bandwidths of up to 100
MHz. By reducing both the peak-to-average ratio (PAR) of the input signals using the CFR block and linearizing
the power amplifier (PA) using the DPD block, the GC5328 reduces the costs of multicarrier PAs (MCPA) for
wireless infrastructure applications. The GC5328 applies CFR and DPD while a separate microprocessor (a
Texas Instruments TMS320C6727 DSP) is used to optimize performance levels and maintain target PA
performance levels.
By including the GC5328 in their system architecture, manufacturers of BTS equipment can realize significant
savings on power amplifier bill of materials (BOM) and overall operational costs due to the PA efficiency
improvement. The GC5328 meets multicarrier 3G performance standards (PCDE, composite EVM, and ACLR) at
PAR levels down to 6.5 dB and improves the ACLR, at the PA output, by 20 dB or more. The GC5328 integrates
easily into the transmit signal chain between baseband processors (such as the Texas Instruments
TMS320C64x™ DSP family) and TI high-performance data converters.
A typical GC5328 system application would include the following transmit-chain components:
•ADS6149 14-bit, 250-Msps ADC or ADS5517 11-bit 200-Msps (feedback path)
•AMC7823 analog monitoring and control circuit with GPIO and SPI
BASEBAND INTERFACE
The GC5328 baseband interface block accepts baseband signals over an interleaved parallel interface at a data
rate of up to 70 MHz. The input interface supports up to 12 separate baseband carriers. The baseband interface
sends the interleaved IQ data to the DUC, or in DUC bypass to the sum chain, with up to 35-Mhz composite BW.
The baseband interface has 18-bit data (top16) BBData[15.0], BBFrame, and two additional (bottom two data)
MFIO(18,19).
The baseband clock input is a CMOS, low-jitter clock.
GAIN/PILOT INSERTION/AntCal INSERTION/POWER METER
Baseband gain can be applied on a per-carrier basis to control the individual channel power accurately through
the system. A UMTS pilot sequence at a programmable gain can be added for antenna calibration. Each
individual baseband channel has an integrated I2+ Q2power accumulator. The baseband power meters have a
common integration counter and interval counter for all channels. The GPP block has an IPDL detection and
control section to select one of four CFR memories when IPDL autoselection is used. Normally, IPDL 0 is
manually selected.
DIGITAL UPCONVERTERS (DUCs)
The GC5328 DUC block has interpolation filters, programmable delays, and complex mixers for each channel.
There are two DUC blocks within the GC5328. The sum chain after the DUC channel combines the DUC channel
streams or the bypass stream and sends the data to the CFR block. Each DUC can operate in one wide, two
medium, or six CDMA channels. Each DUC has a PFIR for spectral shaping, a CFIR for interpolation and image
rejection, and a bulk interpolation CIC.
The 2 DUCs can support:
•(6 channel/DUC mode) up to 12 – 1.23(8) Mhz CDMA, 1xEVDO, or TDSCDMA carriers
•(2 channel/DUC mode) up to 4 – WCDMA or LTE-5 carriers
•(1 channel/DUC mode) up to 2 – Wibro, Wimax, LTE 10 carriers
•(1 channel/DUC mode) 1 – Wimax or LTE20 carrier
Users can specify the filter characteristics of the DUC. The filters are the programmable finite impulse response
(PFIR), compensating finite impulse response (CFIR), and cascade integrator comb (CIC) filters. Users can also
specify the center frequencies of each carrier with a resolution of 0.25 mHz. Additional controls available in the
DUCs include bulk and fractional-time delay adjustments, phase adjustments, and equalization. The maximum
DUC output bandwidth is 40 MHz.
The GC5328 CFR block selectively reduces the peak-to-average ratio (PAR) of wideband digital signals. There
are four peak detection cancellation sections in series in the CFR block. Each stage compares the estimated
peak at the stage input with the target, and subtracts a scaled cancellation peak from the signal. There are 24
cancellers pooled among the four stages. The CFR interpolation filter must have at least 1.6× bandwidth, typical
is 2× BBClock to signal bandwidth.
There are four canceller memories and an update shadow memory that can be used for the auto-IPDL UMTS
select cancellation filter. The shadow memory allows the user to update one of the four filter banks during
operation. The CFR block has a composite RMS meter that can select the CFR input or output for monitoring.
The CFR block for WCDMA reduces TM1, TM3 signals for four adjacent carriers to 6.5 db PAR within the 3GPP
limit. The Wimax 10 reduction for two adjacent carriers is to 8.5 db PAR. TDSCDMA and CDMA performance is
limited by the carrier allocations and carrier coding.The CFR processing complex BW is limited to 62.5% of the
baseband clock rate.
FRACTIONAL FARROW RESAMPLER (FR)
The fractional resampler block takes the peak-reduced composite signals from CFR and resamples this through
fractional interpolation to the DPD processing rate. The user-programmable Farrow resampler supports
upsampling rates from 1× to 64×, with 16-bit precision on the interpolation ratio. After the fractional interpolation,
a complex mixer is available to provide a composite carrier IF offset frequency. A peak I or Q monitor is
provided.
DIGITAL PREDISTORTION (DPD)
The DPD block provides predistortion for up to Nth-order nonlinearities, and can correct multiple orders and
lengths of PA memory effects. The circular hard limiter provides a circular clipper that limits the
magnitude-squared value to –6 dbFS. This is optimized for hardware, and for the allowed gain expansion in the
nonlinear DPD correction.
The DPD has an RMS power meter, and a peak I or Q monitor.
The predistortion is performed for the nonlinear correction in the DPD section. The linear correction is performed
in the Tx equalizer. The predistortion correction terms are computed by an external processor (TMS320C6727
DSP) based on capture buffer information and the DPD software.
The DSP sets up the condition for collecting capture buffer data, retrieves the captured data over the EMIF bus,
and then performs calculations to compute the error and corrections to be used for the transmit path.
The host interface controls the mode of operation of the software in the TI DSP. TI provides a base delivery of
'C6727 software to GC5328 customers that achieves a typical ACLR improvement of 20 dB or more when
compared to a PA without DPD.
DPD CLOCK INPUT
The DPD clock input is an LVDS, low-jitter clock.
BULK UPCONVERTER (BUC)
The bulk upconverter block can interpolate the DPD block output by 1×, 1.5×, 2×, or 3× with a complex output.
The BUC interpolation blocks of 2 and 1.5 can provide 1×, 2×, or 3× interpolation for complex signals. The 1.5×
interpolation after DPD is performed by interpolating by 3 in the BUC and decimating by 2 in the OFMT block.
The BUC mixer can translate the composite IQ predistorted Tx output if the BUC Interpolation is > 1. Note: the
BUC interpolation of 1, 1.5, or 2 is recommended.
OUTPUT FORMATTER AND DAC INTERFACE (OFMT)
The output format and DAC interface presents the GC5328 output in the proper format for the different output
interfaces. The output formatter supports a test pattern for testing the DAC5682Z interface. The two output
interfaces supported for the GC5328 are:
The feedback path has two LVDS input ports. The A port is preferred (it has better timing). The external ADC
Input is converted or processed to generate a complex signal. The feedback equalizer has eight complex taps as
a receive equalizer. The feedback path has a mixer to translate the complex IF to the 0IF reference. The ADC
feedback rate is at the same rate as the DPD clock (fS). The typical feedback is fS/4, fS3/4 (m), or fS5/4 IF. The
feedback equalizer can provide (m) inverted spectral output, if needed.
The FB complex mixer translates the frequency of the complex input signal to 0IF. The feedback path has the
capability for nonlinear correction with a lookup table. TI ADCs that connect to the feedback path are the SDR
type ADS5444, DDR type ADS5445 (6149, 5517), DDR with reversed data phase ADSC217. The ADC feedback
path has modified connections for shared feedback path operation (see GC5325 schematic, User's Guide, in
References ). The GC5328 simplifies timing by providing a FIFO for each ADC port.
NOTE
There are eight LVDS data lanes and 1 LVDS clock lane. If the ADC has < 8 LVDS
data lanes the MSB of the ADC is connected to LVDS lane 7 (MSB) of the A feedback
port.
MICROPROCESSOR (MPU) INTERFACE
The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in
asynchronous mode. It consists of a 16-bit bidirectional data bus, a 10-bit address bus, and RDB, WRB, OEB,
and CEB control signals. The CEB and OEB signals to the GC5328 require additional logic outside the
TMS320C6727B; see Table 1.
6727 DSP EMIFGC5328NOTES
EM_D[15.0]UPDATA[15.0]
EM_A[8.0]UPADDR[9.1]
EM_BA[1]UPADDR[0]
EM_CS2CEBNote: DSP HD[22.20] are used for logic for multiple chip-select, inverted outputs.
EM_RWBOEBInvert RWB send to OEB
EM_WEBWRB
EM_OEBRDB
AXRO[7]InterruptNote: DSP [HD22.20] can also be used with a multiplexer to select GC5328 interrupt.
The GC5328 has two capture buffers of 4096 complex words. The capture buffers are normally used to capture
the Tx reference signal and the feedback output signal. Capture buffer A can capture:
•The TX reference from the DPD after the circular hard limiter
•The feedback output; this represents the waveform as seen by the PA.
•The error output
•Testbus(31:16)
•QRD error output
Capture buffer B can capture:
•The TX reference from the DPD after the circular hard limiter
•The feedback output; this represents the waveform as seen by the PA.
•The error output
•Testbus(15:0)
Standard capture mode – The capture buffers can be armed to collect the 4K complex samples after a
programmable delay following a sync event.
Smart capture mode – There are two trigger conditions that combine the number of samples greater than a
threshold; these are used to find a number of peak events while the transmit signal is above a threshold. In this
case, the magnitude and magnitude-squared of the signal are compared against a threshold and counted. If the
capture buffer finds the trigger condition, the capture logic captures the programmed capture-buffer depth after
the trigger. This is a combination of DSP software and the GC5328 hardware.
Capture buffer A has a special mode to source data for diagnostic testing.
The DSP host-interface software has a function to select and get capture-buffer data.
The complex data is then passed from the GC5328 to the EMIF bus, to the DSP, and
back to the host processor.
The DSP host software has a signal-power monitoring function. This uses the
capture-buffer data to perform special monitoring, power measurement, and error
measurements.
There are special DSP software PA protection modes that use the capture buffer to
determine the DPD correction applied to the signal, the error between the DPD
reference input and the feedback signal. The capture buffers are also used in the
initial bulk delay and fractional delay alignment.
INPUT SYNCS AND OUTPUT SYNC
The GC5328 features multiple user-programmable input syncs. There are three syncs sampled with the BBClock,
(A, B, and C), and the Sync D,DC as an LVDS sync sampled by the DPD clock. Internally, the GC5328 can also
generate timed and software-controlled syncs. The sync A input is required for the GC5328 hardware to initialize.
It should ideally be the start of the frame or frame downlink. The output sync is a test signal used for debugging.
The input syncs can be used to trigger:
•Power measurements
•DUC channel delay, dither, and mixer-phase alignment
•Initializing/loading the DUC, feedback, equalizer, LUTs, etc.
•Feedback path tuner alignment
•Capturing and sourcing of data through SCBs
NOTE
The sync A external synchronization should match the customer Tx frame (total Tx
period – i.e., 5 ms).
See the baseband interface figure, these synchronization signals must meet the
timing of the BBClk.
POWER METERS AND PEAK I–or–Q MONITORS
There are three integrated I2+ Q2power meters in the GC5328:
•GPP – each baseband input channel
•CFR – the CFR input or output, and which antenna stream (0, 1)
•DPD – the input to the DPD nonlinear correction after the DPDL gain, and which antenna stream (0, 1)
There are several peak I or Q monitors within the GC5328.
•FRW– The resampled combined IQ interleaved input to the DPD
•DPD – The input to the DPD nonlinear correction after the DPDL gain
•DPD – After the nonlinear correction in DPD, and separately after the linear correction in DPD
•FDBK – There is a peak monitor at the output of the feedback path.
NOTE
The DSP host software has a HW POWER meter setup and Get(Monitor) function to
configure and get data from the integrated I2+Q2values.
SPECIAL POWER-SUPPLY REQUIREMENTS FOR VDDA1, VSSA1, VDDA2, VSSA2
The two PLLs require an analog supply. Each pair (VDDA1, VSSA1) requires a separate filter. These can be
generated by filtering the core digital supply (VDD). A representative filter is shown in Figure 8. The filters should
be located as close as reasonable to their respective pins (especially the bypass capacitors). The ferrite beads
should be series 50R (similar to Murata P/N: BLM31P500SPT; description: IND FB BLM31P500SPT 50R 1206).
In particular, supply VDDA1 must be less than or equal to VDD1 when VDD1 is at the low end of the required
range. The series resistor assures this condition is met.
DACCLKTX21OClock to DAC
DACCLKCTX20OComplementary clock to DAC
DACSYNCPTX14OPositive output data sync
DACSYNCNTX15ONegative output data sync
TX36, TX29, TX25
TX37, TX28, TX24
FB INPUT FROM LVDS ADC
Figure 6 shows the ADC data and clock signals to the GC5328. These tables list the specific ADC-to-GC5328 FB
connections. There are two feedback (FB) ports, A and B. Port A has faster timing and is preferred. There are
several ADC styles:
•LVDS DDR – ADS5545 (ADS61x9, ADS5517)
•LVDS DDR – ADS62C17 – reversed data alignment (same connections as ADS5545)
•LVDS SDR – ADS5544
ADCs are typically connected to the GC5328 so the MSB of the ADC is connected to FB port A MSB. The lower
bit numbers follow until the ADC bits are all connected. Any remaining lower-order bits on the FB port should be
terminated with resistors, P connection to GND, N connection to 1.8 V as a logic 0. See the GC5325 schematic
listed under References for an example.
There are special connections for shared-feedback ADCs between GC5328s. See the
GC5325 schematic diagram for the shared feedback connection to (2) GC5328.
Table 4. Single LVDS SDR ADC to FB Ports A and B
PIN NAMEPIN NUMBERI/ODESCRIPTION
ADC[15:10]P FB2, FB4, FB6, FB8, FB10, FB12IADC positive feedback from PA output
DAC[9:0]PFB14, FB16, FB20, FB22, FB24, FB26, FB28, FB30,IADC negative feedback from PA output
FB32, FB34
ADC[15:10]N FB3, FB5, FB7, FB9, FB11, FB13IADC negative feedback from PA output
ADC[9:0]NFB15, FB17, FB21, FB23, FB25, FB27, FB29, FB31,IADC negative feedback from PA output
FB33, FB35
ADCCLKFB0IClock from ADC
ADCCLKCFB1IComplementary clock from ADC
Table 5. Single LVDS DDR ADC to FB Port A (Preferred)
PIN NAMEPIN NUMBERI/ODESCRIPTION
ADCA[7:0]PFB2, FB4, FB6, FB8, FB10, FB12, FB14, FB16IADC-A positive feedback from PA output
ADC[9:0]PFB3, FB5, FB7, FB9, FB11, FB13, FB15, FB17IADC-A negative feedback from PA output
ADCACLKFB0IClock from ADC-A
ADCACLKCFB1IComplementary clock from ADC-A
www.ti.com
Table 6. Single LVDS DDR ADC to FB Port B
PIN NAMEPIN NUMBERI/ODESCRIPTION
ADCB[7:0]PFB20, FB22, FB24, FB26, FB28, FB30, FB32, FB34IADC-B positive feedback from PA output
ADCB[7:0]NFB21, FB23, FB25, FB27, FB29, FB31, FB33, FB35IADC-B negative feedback from PA output
ADCBCLKFB18IClock from ADC-B
ADCBCLKCFB19IComplementary clock from ADC-B
MPU INTERFACE GUIDELINES
The following section describes the hardware interface between the recommended microprocessor, external
memory, and the GC5328. Users may select a microprocessor that meets their specific system requirements.
Although the hardware can support multiple options, the recommended TMS320C6727 DSP is also fully
supported with host control and adaptation software. Figure 7 and Figure 9 illustrate the hardware interface
between the DSP, GC5328, and SDRAM. The external memory is required to accommodate the computational
efforts of the adaptation algorithm. Although the system evaluation kit suggests dual-parallel 64-Mb/PC133
(128-Mb) memory modules provided by Samsung (K4S641632H-TC(L)75), other memory alternatives are
available.
The use of an external inverter with minimal propagation delay is required for OEB of the GC5328; this device is
necessary when using a TMS320C6727 DSP. Additional documentation for the hardware interface is available in
the TMS320C672x Hardware Designer’s Resource Guide application report (SPRAA87) and TMS320C672x DSPExternal Memory Interface (EMIF) user's guide (SPRU711).
LatchupJEDEC Level 2 per JEDEC 78 standard (at 90°C and 1.5 × Vmax)±100mA
Core supply voltage–0.3 to 1.32V
Digital supply voltage for TX–0.3 to 2V
Digital supply voltage–0.3 to 3.6V
Input voltage (under/overshoot)–0.5 to VDDSHV + 0.5V
Clamp current for an input/output–20 to 20mA
Storage temperature–65 to 150°C
Lead soldering temperature, 10 seconds300°C
ESD classification Class 2
(Required 2-kV HBM, 500-V CDM)
(Passed 2.5-kV HBM, 500-V CDM, 200-V MM)
Moisture sensitivity Class 3 (floor life at 30°C/60% H)1week
Reflow conditions JEDEC standard260°C
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
VDD, V
V
DDA1
V
DDS
V
DDSHV
IDD, I
I
PP
I
DDS
I
DDSHV
T
C
(1) VDDA1 must be less than VDD1 when VDD1 is low. See recommended filtering circuit in Figure 1 Figure 1. Maximum observed current
(2) Chip specifications in are production tested to 90°C case temperature. QA tests are performed at 85°C.
(1) Customer must check that heat removal is appropriate for the application to limit the junction temperature (TJ) aspecified in the
Recommended Operating Conditions. Conducting heat through the ground and power balls, or adding a heat sink and airflow, may be
needed to limit junction temperature.
(3)
105°C
ELECTRICAL CHARACTERISTICS
Describes the electrical characteristics for the baseband interface, multifunction I/O (MFIO), DPD clock and fast sync, MPU
and JTAG interfaces over recommended operating conditions. Device is production tested at 90°C for the given specification
and characterized at –40°C (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
CMOS INTERFACE
V
V
V
V
|IPU|Pullup currentVIN= 0 V40100200μA
|IIN|Leakage currentVIN= 0 or VIN= V
DAC INTERFACE (DACP/N[15:0])
V
V
LVDS INTERFACE (FB[35:0], DPDCLK/C, SYNCD/C)
V
V
R
POWER SUPPLY
I
dyn
(1) HSTL output levels measured at 675 Mb/s delay and with 100-Ω load from P to N. Drive strength set to 0x360.
(2) 400-Mbps DAC signal, 200-Mhz DPD clock, maximum filtering, 70-Mhz BBPLL clock input
Describes the electrical characteristics for the baseband interface, MFIO[19,18]. Sync A, B, C, and BB Clock over
recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINMAX UNIT
BASEBAND INTERFACE
f
CLK(BB)
t
su(BB)
t
h(BB)
t
h(SYNCA, -B, -C)
Duty
CLK(BB)
Baseband input clock frequencyGPP is ACTIVE2570MHz
GPP is BYPASSED2570
Input data setup time before BBCLK↑BB[15:0], BBFR, SYNCA, SYNCB, and SYNCC;1.3ns
MFIO18/19
Input data hold time after BBCLK↑BB[15:0], BBFR, MFIO18/191.5ns
Input data hold time after BBCLK↑Valid for SYNCA, SYNCB, and SYNCC2ns
Duty cycle30%70%
(1) Controlled by design and process
(2) Jitter is based on a period of (1/(DPDClk × 2)) (for BUC Interp 1 or 2); (1/( DPDClk × 3)) (for BUC Interp 1.5 or 3).
DPD input clock frequency100200MHz
DPD input clock duty cycle30%70%
Input hold time after DPDCLK↑See
Input setup time after DPDCLK↑See
(1)
(1)
Input hold time after DPDCLK↑2ns
Input setup time after DPDCLK↑0.4ns
Cycle-to cycle jitter–2.5%2.5%
www.ti.com
0.2ns
0.4ns
Figure 11. DPD Clock and Fast Sync Timing Specifications
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINMAXUNIT
t
su(AD)
t
su(CEB)
t
su(OEB)
t
d(RD)
t
h(RD)
t
HIGH(RD)
t
Z(RD)
(1) Controlled by design and process and not directly tested.
ADDR setup time to RDB↓WRB is HIGH5ns
CEB setup time to RDB↓WRB is HIGH7ns
OEB setup time to RDB↓WRB is HIGH2ns
DATA valid time after RDB↓WRB is HIGH14ns
ADDR hold time to RDB↑WRB is HIGH2ns
OEB, CEB hold time to RDB↑0
Time RDB must remain HIGH between READs.WRB is HIGH
DATA goes high-impedance after OEB↑ or RDB↑WRB is HIGH
CEB setup time to WRB↓OEB and RDB are HIGH7ns
OEB setup time to WRB↓2
DATA and ADDR hold time after WRB↑OEB and RDB are HIGH2
OEB and CEB hold time after WRB↑0
Time WRB and CEB must remain simultaneously LOWOEB and RDB are HIGH15ns
Time CEB or WRB must remain HIGH between WRITEsOEB and RDB are HIGH10ns
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS PARAMETERMINMAXUNIT
f
TCK
t
p(TCKL)
t
p(TCKH)
t
su(TDI)
t
h(TDI)
t
d(TDO)
JTAG clock frequency50MHz
JTAG clock low period10ns
JTAG clock high period10ns
Input data setup time before TCK↑Valid for TDI and TMS1ns
Input data hold time after TCK↑Valid for TDI and TMS6ns
Output data delay from TCK↓8ns
SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009
TX SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAX UNIT
HSTL MODE – DDR ex. DAC5682
f
CLK(DAC)
t
SKW(DAC)
(1) Because the output clock is DDR, the data rate is 2× the f
(2) t
(1) Because the output clock is SDR, the positive edge of the clock is used to register the data at the DAC receiver. The clock rate is limited
to 200 MHz.
(2) tdand thodata clock-to-data is measured during characterization.
(1)
(2)
(2)
1.5ns
200MHz
1.5ns
Figure 16. TX Timing Specifications (HSTL – SDR)
ENVELOPE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
MFIO CMOS – SDR to Envelope Modulator
f
CLK(ENV)
t
d
t
ho
ENVELOPE data output clock frequency2-mA load
ENVCLK-to-ENVData delay time2-mA load
ENVCLK-to-ENVData hold time2-mA load
(1) Envelope output is magnitude; this is a real output at a DPDClk/2 (100-MHz) rate.
(2) tdand thodata clock-to-data is measured during characterization.
over recommended operating conditions (unless otherwise noted). The following table uses a shorthand nomenclature, NxM.
N means the number of differential pairs used to transmit data from one ADC, and M means the number of bits sent serially
down each LVDS pair. Thus, 8x2 means eight LVDS pairs, each containing 2 bits of information sent serially. NOTE: The
ADC clock rate must match the DPDClock rate for real feedback.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
16x1 SDR LVDS MODE ex. ADS5444
f
CLK(ADC)
t
su(ADC[#]P)
t
h(ADC[#]P)
ADC interface clock frequencySee
Input data setup time before CLK↑See
Input data hold time after CLK↑See
8x2 DDR LVDS MODE ex. ADS5545, ADS6149
f
CLK(ADCA)
t
su(ADCA[#/2]P)
t
h(ADCA[#/2]P)
f
CLK(ADCB)
t
su(ADCB[#/2]P)
t
h(ADCB[#/2]P)
ADCA interface clock frequencySee
Input data setup time before CLK↑↓See
Input data hold time after CLK↑↓See
ADCB interface clock frequencySee
Input data setup time before CLK↑↓See
Input data hold time after CLK↑↓See
(1) Specifications are limited by GC5328 performance and may exceed the example ADC capabilities for the given interface.
(2) Setup and hold measured for ADC[15:0]P, ADC[15:0]N valid for (VOD > 250 mV) to/from ADCCLK and ADCCLKC clock crossing
(VOD = 0).
(3) Setup and hold measured for ADCA[7:0]P, ADCA[7:0]N valid for (VOD > 250 mV) to/from ADCACLK and ADCACLKC clock crossing
(VOD = 0).
(4) Setup and hold measured for ADCB[7:0]P, ADCB[7:0]N valid for (VOD > 250 mV) to/from ADCBCLK and ADCBCLKC clock crossing
3GThird-generation (refers to next-generation wideband cellular systems that use CDMA)
3GPPThird-generation partnership project (W-CDMA specification, www.3gpp.org)
3GPP2Third-generation partnership project 2 (cdma2000 specification, www.3gpp2.org)
ACLRAdjacent channel leakage ratio (measure of out-of-band energy from one CDMA carrier)
ACPRAdjacent channel power ratio
ADCAnalog-to-digital converter
BWBandwidth
CCDFComplementary cumulative distribution function
CDMACode division multiple access (spread spectrum)
CEVMComposite error vector magnitude
CFRCrest factor reduction
CMOSComplementary metal oxide semiconductor
DACDigital-to-analog converter
dBDecibels
dBmDecibels relative to 1 mW (30 dBm = 1 W)
DDRDual data rate (ADC output format)
DSPDigital signal processing or digital signal processor
DUCDigital upconverter (usually provides the GC5328 input)
EVMError vector magnitude
FIRFinite impulse response (type of digital filter)
I/QIn-phase and quadrature (signal representation)
IFIntermediate frequency
IIRInfinite impulse response (type of digital filter)
JTAGJoint Test Action Group (chip debug and test standard 1149.1)
LOLocal oscillator
LSBLeast-significant bit
MbMegabits (divide by 8 for megabytes MB)
MSBMost-significant bit
MSPSMegasamples per second (1×106samples/s)
PAPower amplifier
PARPeak-to-average ratio
PCDEPeak code domain error
PDCPeak detection and cancellation (stage)
PDFProbability density function
RFRadio frequency
RMSRoot mean square (method to quantify error)
SDRSingle data rate (ADC output format)
SEMSpectrum emission mask
SNRSignal-to-noise ratio (usually measured in dB or dBm)
UMTSUniversal mobile telephone service
W-CDMAWideband code division multiple access (synonymous with 3GPP)
WiBROWireless broadband (Korean initiative IEEE 802.16e)
WiMAXWorldwide Interoperability of Microwave Access (IEEE 802.16e)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
ProductsApplications
Amplifiersamplifier.ti.comAudiowww.ti.com/audio
Data Convertersdataconverter.ti.comAutomotivewww.ti.com/automotive
DLP® Productswww.dlp.comCommunications andwww.ti.com/communications
DSPdsp.ti.comComputers andwww.ti.com/computers
Clocks and Timerswww.ti.com/clocksConsumer Electronicswww.ti.com/consumer-apps
Interfaceinterface.ti.comEnergywww.ti.com/energy
Logiclogic.ti.comIndustrialwww.ti.com/industrial
Power Mgmtpower.ti.comMedicalwww.ti.com/medical
Microcontrollersmicrocontroller.ti.comSecuritywww.ti.com/security
RFIDwww.ti-rfid.comSpace, Avionics &www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprfVideo and Imagingwww.ti.com/video