Texas Instruments GC5328 User Manual

GC5328

DU C- CF R- DP D

BBData

DAC

'C6727

DSP

DAC

I/Q

ADC

I/Q

Modulator

Mixer

LPA

HPA

Attenuator

0 31.5dB–

Attenuator

0 31.5dB–

Host

Control

Interface

B0278-03

GC5328

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SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

GC5328 Low-Power Wideband Digital Predistortion Transmit Processor

Check for Samples: GC5328

FEATURES

• Integrated DUC, CFR, and DPD Solution • Supports Direct Interface to TI High-Speed

• 20-MHz Max. Signal Bandwidth, Based on Max. DPD Clock of 200 Mhz, Fifth-Order Correction

• DUC: Up to 12 CDMA2000/TDSCDMA, 4 W-CDMA, 2–10 MHz or 1–20 MHz OFDMA Carriers

• CFR: Typically Meets 3GPP TS 25.141 < 6.5 dB PAR, < 8.5 dB PAR for OFDMA Signals

• DPD: Short-Term Memory Compensation, Typical ACLR Improvement > 20 dB

• GC5328IZER PBGA Package, 23 mm × 23 mm

• 1.2-V Core, 1.8-V HSTL, 3.3-V I/O

• 2.5-W Typical Power Consumption

• TMS320C6727 DPD Optimization Software

Data Converters

APPLICATIONS

• 3 GPP (W-CDMA) Base Stations

• 3 GPP2 (CDMA2000) Base Stations

• WiMAX, WiBRO, and LTE (OFDMA) Base Stations

• Multicarrier Power Amplifiers (MCPAs)

DESCRIPTION

The GC5328 is a lower-power version of the GC5322 wideband digital predistortion transmit processor. The GC5328 includes a digital upconverter (DUC) block, a crest factor reduction (CFR) block, a digital predistortion (DPD) block, feedback (FB) block, and capture buffer (CB) blocks.

The GC5328 GPP block receives the interleaved IQ data from the baseband input. The individual IQ channels are gain-adjusted in the GPP and routed to the DUC. The GPP and DUC can be bypassed to input a combined

IQ signal. The DUC provides three stages of interpolation and a complex mixer. There are two DUC blocks. The output from the DUC blocks is combined in the sum chain. Each of the 1 to 12 DUC channels can be summed, and the composite signal can be scaled.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Figure 1. GC5328 System Block Diagram

BBin

DACout

Gain

Pilot

Insertion

AntCal

Insertion

Power

Meter

BBFR

Wide Band DUC

Medium

Band DUC

Medium

Band DUC

Medium

Band DUC

Medium

Band DUC

NarrowBand DUC

CFR

Fractional

Resampler

Circular

Limiter

GC5328

JTAGMPU Interface

RESETB

SYNC3SYNC

OUT

INT UPDATA UPADDR

OEB

RDB WRB

CEB

TCK

TRST

TMS

BBclk

DPDclk

SYNC

PLL

DPD

PLL

Real to Complex

Feedback

Equalizer

Feedback Mixer

and NL Correction

Bulk Interpolation

+ Mixer

Transmit

Equalizer

DPD

ADC

Interface

DAC

Interface

Capture Buffers

DUCs in 1-Chn Mode

DUCs in 2-Chn Mode

DUCs in 6-Chn Mode

BB Clock Domain DPD Clock Domain

B0279-03

Envelope

Interface

To Capture

Buffer

To Capture

Buffer

To Capture

Buffer

Pilot

Insertion

ADCin

(LVDS)

ADCin

(LVDS)

MAGclk

MAGout

Active Only in Dual Antenna Mode

GC5328

SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

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The CFR block has four serial stages of peak detection and cancellation. The CFR block cancellation filter can be programmed as real or complex. The CFR peak-reduced output is routed to the Farrow resampler. The Farrow resampler resamples the CFR output to the DPD clock rate. The Farrow resampler block also has a complex mixer for composite carrier frequency offset.

The DPD subsystem has a circular limiter, nonlinear DPD correction, and a transmit equalizer. The DPD correction can reduce the follow-on circuitry distortion products. The DPD output is sent to the BUC. The BUC provides a post-DPD interpolation, and also provides a complex mixer for frequency offset. The DAC interface converts the BUC signal output to the interleaved IQ or parallel IQ output signals for the DAC5682Z or DAC5688.

The CB block captures the selected internal reference signal, and the feedback block in two up to 4K capture buffers. The signal capture can be based on an externally timed event (standard capture buffer), delay after a timed event, or signal statistics (smart capture buffer). Normally the DPD input and feedback output are selected. The capture buffers are stored and read by the microprocessor.

The FB block receives the LVDS ADC information and performs signal processing to downconvert the received signal to 0IF. The FB block also has a feedback-path receive equalizer.

Figure 2. GC5328 Functional Block Diagram

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AVAILABLE OPTIONS

–40°C to 85°C GC5328IZER

484-Ball PBGA Package, 23 mm × 23 mm

PACKAGED DEVICE

REFERENCES

1. GC532x Architecture Datasheet (NDA, obtain through local TI field application engineer)

2. GC5328 EVM User Guide, Schematic Diagram (obtain through local TI field application engineer)

3. GC5325 EVM User Guide, Schematic Diagram TI Web site under GC5325

4. GC5322 DPD Host Interface Guide (obtain through local TI Field Application Engineer)

5. GC5328 configuration (obtain through local TI Field Application Engineer)

6. DSP – TMS320C672x DSP Universal Host Port Interface Reference Guide (SPRU719)

7. DSP – TMS320C672x DSP External Memory Interface (EMIF) User's Guide (SPRU711)

GC5328 INTRODUCTION

The GC5328 is a flexible transmit sector processor that includes a digital upconverter (DUC) block, a crest factor reduction (CFR) block, and a digital predistortion (DPD) block and its associated feedback chain. The GC5328 processes composite input bandwidths of up to 20 MHz and processes DPD expansion bandwidths of up to 100 MHz. By reducing both the peak-to-average ratio (PAR) of the input signals using the CFR block and linearizing the power amplifier (PA) using the DPD block, the GC5328 reduces the costs of multicarrier PAs (MCPA) for wireless infrastructure applications. The GC5328 applies CFR and DPD while a separate microprocessor (a Texas Instruments TMS320C6727 DSP) is used to optimize performance levels and maintain target PA performance levels.

By including the GC5328 in their system architecture, manufacturers of BTS equipment can realize significant savings on power amplifier bill of materials (BOM) and overall operational costs due to the PA efficiency improvement. The GC5328 meets multicarrier 3G performance standards (PCDE, composite EVM, and ACLR) at PAR levels down to 6.5 dB and improves the ACLR, at the PA output, by 20 dB or more. The GC5328 integrates easily into the transmit signal chain between baseband processors (such as the Texas Instruments TMS320C64x™ DSP family) and TI high-performance data converters.

A typical GC5328 system application would include the following transmit-chain components:

• TMS320C6727B digital signal processor (DSP)

• DAC5682 16-bit, 1-Gsps DAC; DAC5688 16-bit, 800-Msps DAC (transmit path)

• CDCM7005, CDCE72010 clock generator

• TRF3761 integrated VCO/PLL synthesizer

• TRF3703 quadrature modulator

• ADS6149 14-bit, 250-Msps ADC or ADS5517 11-bit 200-Msps (feedback path)

• AMC7823 analog monitoring and control circuit with GPIO and SPI

BASEBAND INTERFACE

The GC5328 baseband interface block accepts baseband signals over an interleaved parallel interface at a data rate of up to 70 MHz. The input interface supports up to 12 separate baseband carriers. The baseband interface sends the interleaved IQ data to the DUC, or in DUC bypass to the sum chain, with up to 35-Mhz composite BW. The baseband interface has 18-bit data (top16) BBData[15.0], BBFrame, and two additional (bottom two data) MFIO(18,19).

Product Folder Link(s): GC5328

GC532x

BBFR

TXSYNCREFERENCE

DGND

SYNC A

SYNC B

SYNC C

CustomerLOGIC

BBDATA[17:2]

B0370-01

BBCLK

START_FRAME

TIME

DIVISON

MULTIPLEXED

BASEBAND

DATA

TXSYNC

REFERENCE

TXSYNC2

REFERENCE

BASEBANDCLOCK(CMOS)

LOWJITTER

BBCLK

START ofMUX-FRAME

BBDATA[1:0]

TXSYNC2REFERENCE

BBDATA[15:0]

MFIO[19:18]

GC5328

SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

Figure 3. Baseband and Sync Interface to GC5328

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BASEBAND CLOCK INPUT

The baseband clock input is a CMOS, low-jitter clock.

GAIN/PILOT INSERTION/AntCal INSERTION/POWER METER

Baseband gain can be applied on a per-carrier basis to control the individual channel power accurately through the system. A UMTS pilot sequence at a programmable gain can be added for antenna calibration. Each individual baseband channel has an integrated I2+ Q2power accumulator. The baseband power meters have a common integration counter and interval counter for all channels. The GPP block has an IPDL detection and control section to select one of four CFR memories when IPDL autoselection is used. Normally, IPDL 0 is manually selected.

DIGITAL UPCONVERTERS (DUCs)

The GC5328 DUC block has interpolation filters, programmable delays, and complex mixers for each channel. There are two DUC blocks within the GC5328. The sum chain after the DUC channel combines the DUC channel streams or the bypass stream and sends the data to the CFR block. Each DUC can operate in one wide, two medium, or six CDMA channels. Each DUC has a PFIR for spectral shaping, a CFIR for interpolation and image rejection, and a bulk interpolation CIC.

The 2 DUCs can support:

• (6 channel/DUC mode) up to 12 – 1.23(8) Mhz CDMA, 1xEVDO, or TDSCDMA carriers

• (2 channel/DUC mode) up to 4 – WCDMA or LTE-5 carriers

• (1 channel/DUC mode) up to 2 – Wibro, Wimax, LTE 10 carriers

• (1 channel/DUC mode) 1 – Wimax or LTE20 carrier Users can specify the filter characteristics of the DUC. The filters are the programmable finite impulse response

(PFIR), compensating finite impulse response (CFIR), and cascade integrator comb (CIC) filters. Users can also specify the center frequencies of each carrier with a resolution of 0.25 mHz. Additional controls available in the DUCs include bulk and fractional-time delay adjustments, phase adjustments, and equalization. The maximum DUC output bandwidth is 40 MHz.

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CREST FACTOR REDUCTION (CFR)

The GC5328 CFR block selectively reduces the peak-to-average ratio (PAR) of wideband digital signals. There are four peak detection cancellation sections in series in the CFR block. Each stage compares the estimated peak at the stage input with the target, and subtracts a scaled cancellation peak from the signal. There are 24 cancellers pooled among the four stages. The CFR interpolation filter must have at least 1.6× bandwidth, typical is 2× BBClock to signal bandwidth.

There are four canceller memories and an update shadow memory that can be used for the auto-IPDL UMTS select cancellation filter. The shadow memory allows the user to update one of the four filter banks during operation. The CFR block has a composite RMS meter that can select the CFR input or output for monitoring.

The CFR block for WCDMA reduces TM1, TM3 signals for four adjacent carriers to 6.5 db PAR within the 3GPP limit. The Wimax 10 reduction for two adjacent carriers is to 8.5 db PAR. TDSCDMA and CDMA performance is limited by the carrier allocations and carrier coding.The CFR processing complex BW is limited to 62.5% of the baseband clock rate.

FRACTIONAL FARROW RESAMPLER (FR)

The fractional resampler block takes the peak-reduced composite signals from CFR and resamples this through fractional interpolation to the DPD processing rate. The user-programmable Farrow resampler supports upsampling rates from 1× to 64×, with 16-bit precision on the interpolation ratio. After the fractional interpolation, a complex mixer is available to provide a composite carrier IF offset frequency. A peak I or Q monitor is provided.

DIGITAL PREDISTORTION (DPD)

The DPD block provides predistortion for up to Nth-order nonlinearities, and can correct multiple orders and lengths of PA memory effects. The circular hard limiter provides a circular clipper that limits the magnitude-squared value to –6 dbFS. This is optimized for hardware, and for the allowed gain expansion in the nonlinear DPD correction.

The DPD has an RMS power meter, and a peak I or Q monitor. The predistortion is performed for the nonlinear correction in the DPD section. The linear correction is performed

in the Tx equalizer. The predistortion correction terms are computed by an external processor (TMS320C6727 DSP) based on capture buffer information and the DPD software.

The DSP sets up the condition for collecting capture buffer data, retrieves the captured data over the EMIF bus, and then performs calculations to compute the error and corrections to be used for the transmit path.

The host interface controls the mode of operation of the software in the TI DSP. TI provides a base delivery of 'C6727 software to GC5328 customers that achieves a typical ACLR improvement of 20 dB or more when compared to a PA without DPD.

DPD CLOCK INPUT

The DPD clock input is an LVDS, low-jitter clock.

BULK UPCONVERTER (BUC)

The bulk upconverter block can interpolate the DPD block output by 1×, 1.5×, 2×, or 3× with a complex output. The BUC interpolation blocks of 2 and 1.5 can provide 1×, 2×, or 3× interpolation for complex signals. The 1.5× interpolation after DPD is performed by interpolating by 3 in the BUC and decimating by 2 in the OFMT block. The BUC mixer can translate the composite IQ predistorted Tx output if the BUC Interpolation is > 1. Note: the BUC interpolation of 1, 1.5, or 2 is recommended.

OUTPUT FORMATTER AND DAC INTERFACE (OFMT)

The output format and DAC interface presents the GC5328 output in the proper format for the different output interfaces. The output formatter supports a test pattern for testing the DAC5682Z interface. The two output interfaces supported for the GC5328 are:

• DAC5682 interleaved IQ

• DAC5688 parallel IQ or interleaved IQ

Product Folder Link(s): GC5328

DAC5682Z

DCLK,DCLKC

CLKIN,CLKINC

DAC Clock

D[15:0]P,D[15:0]N

TX21, TX20

SYNCP, SYNCN

GC532x

B0371-01

DifferentialData

ExtPullup/

PullDown

ExtPullup

(2)

ExtTerm

(1)

DPD Clock

DataClock

TX[]

(SeeHWDataSheet)

TXENABLE

Single-Ended

1.8-VCMOS

TX18

DAC5688

DCLK,DCLKC

CLKIN,CLKINC

DAC Clock

DACA[15:0]

TX21, TX20

GC532x

B0372-01

ExtTerm

(1)

ExtTerm1

(2)

ExtTerm1

(2)

ExtTerm1

(2)

DPD Clock

DataClock

TX[]-DACI[]

(SeeHWDataSheet)

Single-Ended

1.8-VCMOS

Single-Ended

1.8-VCMOS

DACB[15:0]

TX[]-DACQ[]

(SeeHWDataSheet)

GC5328

SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

(1) ExtTerm – see DAC data sheet. (2) ExtPullup, 500 Ω to 1.8 V, only required when DAC Data Clock > 337 MHz

Figure 4. GC5328 to DAC5682Z Interface

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(1) ExtTerm – see DAC data sheet. (2) ExtTerm1 – tester uses 50 Ω to 0.9 V for termination.

Figure 5. GC5328 to DAC5688 Interface

Product Folder Link(s): GC5328

GC532x

FB[1:0]

ADC

MSB ALigned

ADCDDRData

B0373-01

ADC[7P,7N,0P,0N]

FB[17:2] (SeeHWDataSheet)

ADC_OutClkP,N

DDR Clock

GC5328

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SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

FEEDBACK PATH (FB)

The feedback path has two LVDS input ports. The A port is preferred (it has better timing). The external ADC Input is converted or processed to generate a complex signal. The feedback equalizer has eight complex taps as a receive equalizer. The feedback path has a mixer to translate the complex IF to the 0IF reference. The ADC feedback rate is at the same rate as the DPD clock (fS). The typical feedback is fS/4, fS3/4 (m), or fS5/4 IF. The feedback equalizer can provide (m) inverted spectral output, if needed.

The FB complex mixer translates the frequency of the complex input signal to 0IF. The feedback path has the capability for nonlinear correction with a lookup table. TI ADCs that connect to the feedback path are the SDR type ADS5444, DDR type ADS5445 (6149, 5517), DDR with reversed data phase ADSC217. The ADC feedback path has modified connections for shared feedback path operation (see GC5325 schematic, User's Guide, in

References ). The GC5328 simplifies timing by providing a FIFO for each ADC port.

NOTE

There are eight LVDS data lanes and 1 LVDS clock lane. If the ADC has < 8 LVDS data lanes the MSB of the ADC is connected to LVDS lane 7 (MSB) of the A feedback port.

MICROPROCESSOR (MPU) INTERFACE

The MPU interface is designed to interface with external memory interface (EMIF) ports on TI DSPs operating in asynchronous mode. It consists of a 16-bit bidirectional data bus, a 10-bit address bus, and RDB, WRB, OEB, and CEB control signals. The CEB and OEB signals to the GC5328 require additional logic outside the TMS320C6727B; see Table 1.

6727 DSP EMIF GC5328 NOTES

EM_D[15.0] UPDATA[15.0] EM_A[8.0] UPADDR[9.1] EM_BA[1] UPADDR[0] EM_CS2 CEB Note: DSP HD[22.20] are used for logic for multiple chip-select, inverted outputs. EM_RWB OEB Invert RWB send to OEB EM_WEB WRB EM_OEB RDB AXRO[7] Interrupt Note: DSP [HD22.20] can also be used with a multiplexer to select GC5328 interrupt.

Figure 6. LVDS DDR ADC to GC5328 FB Interface

Table 1. EMIF to GC5328 Microprocessor Interface

Product Folder Link(s): GC5328

FirstGC532x

DSP JTAG

DSP RST

BOOTMODE

Multiplex

Address

HalfData

UHPI

EMIF Addr

CntlSDRAM

EMIFData

UPDATA[]

UPADDRESS[]

andCNTL CS2-2

EMIF Addr

CntlGC5322

INTROUT

Inv

RDB,CS2[]

HOST UHPI

INTERFACE

To/From

OtherGC5322

INTROUT(2)

CS2-1

Note:OneDSP is

sharedWith

GC532xs

B0374-01

TI6727

DSP

SDRAM

INTROUT

UPDATA[]

UPADDRESS[] andCNTL

r e s

GPIO

Ant

SelCode

GC5328

SLWS218A –OCTOBER 2009–REVISED OCTOBER 2009

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Figure 7. 6727 DSP to GC5328 EMIF Interface

CAPTURE BUFFERS (SCB)

The GC5328 has two capture buffers of 4096 complex words. The capture buffers are normally used to capture the Tx reference signal and the feedback output signal. Capture buffer A can capture:

• The TX reference from the DPD after the circular hard limiter

• The feedback output; this represents the waveform as seen by the PA.

• The error output

• Testbus(31:16)

• QRD error output Capture buffer B can capture:

• The TX reference from the DPD after the circular hard limiter

• The feedback output; this represents the waveform as seen by the PA.

• The error output

• Testbus(15:0) Standard capture mode – The capture buffers can be armed to collect the 4K complex samples after a

programmable delay following a sync event. Smart capture mode – There are two trigger conditions that combine the number of samples greater than a

threshold; these are used to find a number of peak events while the transmit signal is above a threshold. In this case, the magnitude and magnitude-squared of the signal are compared against a threshold and counted. If the capture buffer finds the trigger condition, the capture logic captures the programmed capture-buffer depth after the trigger. This is a combination of DSP software and the GC5328 hardware.

Capture buffer A has a special mode to source data for diagnostic testing. The DSP host-interface software has a function to select and get capture-buffer data.

The complex data is then passed from the GC5328 to the EMIF bus, to the DSP, and back to the host processor.

The DSP host software has a signal-power monitoring function. This uses the capture-buffer data to perform special monitoring, power measurement, and error measurements.

NOTE

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There are special DSP software PA protection modes that use the capture buffer to determine the DPD correction applied to the signal, the error between the DPD reference input and the feedback signal. The capture buffers are also used in the initial bulk delay and fractional delay alignment.

INPUT SYNCS AND OUTPUT SYNC

The GC5328 features multiple user-programmable input syncs. There are three syncs sampled with the BBClock, (A, B, and C), and the Sync D,DC as an LVDS sync sampled by the DPD clock. Internally, the GC5328 can also generate timed and software-controlled syncs. The sync A input is required for the GC5328 hardware to initialize. It should ideally be the start of the frame or frame downlink. The output sync is a test signal used for debugging.

The input syncs can be used to trigger:

• Power measurements

• DUC channel delay, dither, and mixer-phase alignment

• Initializing/loading the DUC, feedback, equalizer, LUTs, etc.

• Feedback path tuner alignment

• Capturing and sourcing of data through SCBs

NOTE

The sync A external synchronization should match the customer Tx frame (total Tx period – i.e., 5 ms).

See the baseband interface figure, these synchronization signals must meet the timing of the BBClk.

POWER METERS AND PEAK I–or–Q MONITORS

There are three integrated I2+ Q2power meters in the GC5328:

• GPP – each baseband input channel

• CFR – the CFR input or output, and which antenna stream (0, 1)

• DPD – the input to the DPD nonlinear correction after the DPDL gain, and which antenna stream (0, 1) There are several peak I or Q monitors within the GC5328.

• FRW– The resampled combined IQ interleaved input to the DPD

• DPD – The input to the DPD nonlinear correction after the DPDL gain

• DPD – After the nonlinear correction in DPD, and separately after the linear correction in DPD

• FDBK – There is a peak monitor at the output of the feedback path.

NOTE

The DSP host software has a HW POWER meter setup and Get(Monitor) function to configure and get data from the integrated I2+Q2values.

Product Folder Link(s): GC5328

+ 18 hidden pages

Texas Instruments GC5328 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual