TEXAS INSTRUMENTS GC5018 Technical data

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1 Introduction

1.1 FEATURES

• Four 16-Bit CMOS ADC Input Ports

• Programmable Closed Loop VGA Control With

6-Bit Outputs for Each ADC Input Port

• Provide Received Total Wide Band Power

(RTWP) Measurement for the Composite Power Across Carriers With Programmable Time Window for Measurement

• 8 UMTS Digital Down Converter (DDC)

Channels or 16 CDMA or 16 TD-SCDMA DDC Channels With Programmable 18 Bit Filter Coefficients

• Each DDC channel includes

– Real or Complex DDC Inputs

GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

– 115 dB SFDR NCO – UMTS Mode Rx Filtering: 6 Stage CIC (m=1

or 2), Up to 40 Tap CFIR, Up to 64 Tap PFIR

– CDMA Mode Rx Filtering: 6 Stage CIC (m=1

or 2), Up to 64 Tap CFIR, Up to 64 Tap PFIR – Power Measurements – Final AGC

• 1.5V Digital Core Supply, 3.3V Digital I/O

Supply

• 305 Ball Plastic BGA (19 mm x 19 mm) With

1,0 mm Pitch

• Power Dissipation: ~2W

1.2 APPLICATIONS

• Wireless Base Station Receiver

• Multi-Carrier Digital Receiver

• UMTS (4 Carriers-1 Sector With Diversity)

• CDMA (8 Carriers-1 Sector With Diversity)

• TD-SCDMA (16 Carriers-1 Sector Without

Diversity, 8 Carriers-1-Sector With Diversity)

• Digital Radio Receivers

• Wide Band Receivers

• Software Radios

• Wireless Local Loop

• Intelligent Antenna Systems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document.

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

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PRODUCT PREVIEW

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

Contents

1 Introduction ............................................... 1 5.1 Digital Receive Section Signals .................... 105

1.1 FEATURES ........................................... 1 5.2 Microprocessor Signals ............................ 108

1.2 APPLICATIONS ...................................... 1 5.3 JTAG Signals ...................................... 109

2 General Description ..................................... 2 5.4 Factory Test and No Connect Signals ............. 109

3 RECEIVE DIGITAL SIGNAL PROCESSING ......... 3 5.5 Power and Ground Signals ........................ 110

3.1 Receive Input Interface ............................... 4 5.6 Digital Supply Monitoring .......................... 110

3.2 DDC Organization ................................... 15 5.7 JTAG ............................................... 110

4 GC5018 GENERAL CONTROL ....................... 42 6 SPECIFICATIONS ..................................... 111

4.1 Microprocessor Interface Control Data, Address,

and Strobes ......................................... 43

4.2 Synchronization Signals ............................. 45

4.3 Interrupt Handling ................................... 46

4.4 GC5018 Programming .............................. 47

5 GC5018 PINS ........................................... 105

2 General Description

The GC5018 is a multi-channel communications signal processor that provides digital downconversion optimized for cellular base transceiver systems. The device supports UMTS, CDMA-1X and TD-SCDMA air interface cellular standards.

6.1 ABSOLUTE MAXIMUM RATINGS ................. 111

6.2 RECOMMENDED OPERATING CONDITIONS ... 111

6.3 THERMAL CHARACTERISTICS .................. 111

6.4 DC CHARACTERISTICS .......................... 112

6.5 AC TIMING CHARACTERISTICS ................. 112

The chip provides up to 8 UMTS digital downconverter channels (DDC), 16 CDMA DDCs or 16 TD-SCDMA DDCs. The DDC channels are independent and operate simultaneously.

The GC5018 has four 16-bit inputs. Each DDC channel can be programmed to accept data from any one (or two for complex input mode) of the four input ports.

2 Contents

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sync

DDC0

2 CDMA2000−1X,

2 TD−SCDMA or 1 UMTS

rxin_a adcclk_a

rxin_b adcclk_b

Digital receive

data ports

JTAG

tdo

trst_n

tck

tdi

tms

Control and Sync

d(15:0)16a(5:0)6rd_n wr_n ce_n

rx_sync a−d

reset_n

interrupt rx_sync_out

rxclk

6 6 6 6

dvga_a

dvga_b

dvga_c

dvga_d

Receive Input

Interface

Power

Measurements and

WidebandAGC

DDC1

2 CDMA2000−1X,

2 TD−SCDMA or 1 UMTS

DDC2

2 CDMA2000−1X,

2 TD−SCDMA or 1 UMTS

DDC3

2 CDMA2000−1X,

2 TD−SCDMA or 1 UMTS

DDC5

2 CDMA2000−1X,

2 TD−SCDMA or 1 UMTS

DDC4

2 CDMA2000−1X,

2 TD−SCDMA or 1 UMTS

rxin_c adcclk_c

rxin_d adcclk_d

DDC7

2 CDMA2000−1X,

2 TD−SCDMA or 1 UMTS

DDC6

2 CDMA2000−1X,

2 TD−SCDMA or 1 UMTS

sync

Output Format

Parallel

or Serial

rxout_X_X

rx_sync_out_X

rxclk_out

8-CHANNEL WIDEBAND RECEIVER

GC5018

SLWS169 – MAY 2005

3 RECEIVE DIGITAL SIGNAL PROCESSING

The down conversion section of the GC5018 consists of the receive input interface, the rx_distribution bus, and 8 digital downconverter blocks.

The purpose of the receive input interface is to accept signal data from four 16 bit input ports, measure the input signal power, control the digital VGA and to distribute the data to the DDC blocks. The input interface also has a user-controlled test generator and noise source.

The rx_distribution bus distributes the four channels of signal data to each of the 8 DDC blocks. Each DDC block selects one of the four channels (or 2 for complex input data) from the rx_distribution bus

and then performs downconversion tuning, programmable delay, channel filtering with decimation, power measurement, fixed gain adjust and/or automatic gain control. Each DDC block can support 1 UMTS channel, 2 CDMA channels or 2 TD-SCDMA channels. An optional mode permits stacking two DDC blocks in UMTS mode to provide double-length final pulse shaping filtering.

Tuned, filtered, and decimated signal data is output in bit serial or parallel format.

RECEIVE DIGITAL SIGNAL PROCESSING 3

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PRODUCT PREVIEW

FIFO

16rxin_a 16

dual real or

single complex

Power Meter

FIFO

16rxin_b 16

FIFO

16rxin_c 16

FIFO

16rxin_d 16

dual real or

single complex

Power Meter

dual real or

single complex

AGC

dual real or

single complex

AGC

dvga_c

dvga_d

dvga_a

dvga_b

rx_distribution

bus to DDC

channels

test & noise

signal

generator

test & noise

signal

generator

test & noise

signal

generator

test & noise

signal

generator

to testbus

test bus select

and decimation

testbus

sources

1 to 64 sample

delay

line

delay_a

1 to 64 sample

delay

line

delay_b

1 to 64

sample

delay

line

delay_c

1 to 64

sample

delay

line

delay_d

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

3.1 Receive Input Interface

The GC5018’s receive input data interface accepts data from two sources:

• Signal data presented at the four 16-bit digital data input ports.

• A LFSR test signal generator allows the GC5018 to be tested using a known repetitive data sequence.

Signal data can be provided in binary or 2’s complement form. The location of the ADC’s MSB can be programmed to allow for additional AGC headroom if desired. For example, a 14-bit ADC may be connected with the MSBs aligned, or shifted down to allow the AGC additional gain range before clipping the signal.

Signal data can be accepted at rates up to rxclk in UMTS mode for either 8 normal channels or 4 double length final pulse shaping filter channels. In CDMA mode the maximum input rate is rxclk for real inputs, or rxclk/2 for complex inputs. For maximum filter performance, higher clock rates generally allow longer filters.

Complex signal data is input with I data driving one input port and Q data driving another. This means that there are only two signal data ports available when using complex input mode. The mapping of I and Q data onto the four input ports is programmable.

Signal input data is clocked into 8-stage FIFOs using a matching external clock signal adcclk_a/b/c/d. Signal data is clocked out of the FIFO from a gated rxclk (the GC5018 receive section clock). The FIFO allows arbitrary phase relationship between adcclk_a/b/c/d and rxclk. The frequency relationship is mandated by the programmed configuration.

The test and noise generator can supply test sequences or add noise to the input signal data. The test sequences, when combined with the checksum generators, are useful for initial board debug or power-on self-test.

For applications that require receiver desensitization, the noise generator can add noise to input data streams.

Many internal chip signals can be routed to the testbus for evaluation and debug purposes. When the testbus is enabled, the rxin_c and rxin_d ports are driven as digital outputs.

4 RECEIVE DIGITAL SIGNAL PROCESSING

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GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

Each of the four outputs to the DDC channels includes a 1 to 64 sample delay line.

PROGRAMMING

VARIABLE DESCRIPTION

ssel_ddc(2:0) Selects the sync source for the DDC data input mux and mixer. This sets the sync source for DDC input clock

offset_bin_X Selects offset binary input when set, 2’s complement input when cleared. X={a,b,c,d} msb_pos_X(2:0) Identifies the connection location of the ADC’s MSB. Programmed values of {0..7} corresponds to msb at {rxin_x_15..

3.1.1 Receive FIFO

The receive FIFO consists of an 8 stage memory and 2 counters generating the input write pointer and output read pointer. When the FIFO receives a sync signal, the input and output pointers are initialized with a write to read pointer offset of four samples. Input samples from rxin_X (writes) are clocked with the adcclk_X input clock rising edges, and the input pointer advances on each clock rising edge. Output samples (reads) and the output pointer are clocked with the rxclk input signal rising edges, divided by the programmed sample rate loaded into the rate_sel(1:0) control register.

VARIABLE DESCRIPTION

adc_fifo_bypass When set, bypasses the input FIFOs and input data is latched directly using the rxclk. When cleared, input data is

ssel_adc_fifo(2:0) Selects the sync source for the FIFO state machines. This sync signal initializes the FIFO input and output

rate_sel(1:0) This selects the FIFO input and output rate; {rxclk, rxclk/2, rxclk/4 or rxclk/8 }. For example, with rxclk at

adc_fifo_strap_ab When set, the rxin_a and rxin_b FIFO input and output pointers are synchronized to support complex input

adc_fifo_strap_cd When set, the rxin_c and rxin_d FIFO input and output pointers are synchronized to support complex input

generation and synchronization for all DDC channels.

rxin_x_8}. X={a,b,c,d}

PROGRAMMING

latched using the adcclk_a/b/c/d inputs.

pointers.

153.6MHz, set rate_sel to 0, 1, 2 or 3 respectively for adcclk_a/b/c/d 153.6, 76.8, 38.4 or 19.2MHz.

signals.

RECEIVE DIGITAL SIGNAL PROCESSING 5

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PRODUCT PREVIEW

from rxin_a FIFO output

from rxin_b FIFO output

pmeter_iq0

pmeter_iq1

from rxin_c FIFO output

from rxin_d FIFO output

pmeter_iq2

pmeter_iq3

from rxin_a

from rxin_b

power meter 0 results

power meter 1 results

power meter 0

power meter 1

from rxin_c

from rxin_d

power meter 2 results

power meter 3 results

power meter 2

power meter 3

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

3.1.2 Receive Input Power Meters

Four Receive Input RMS power meters are provided. For real inputs, the four power meters can be used to measure the RMS power of the combined carriers in each of the four input signals (the Q input is held at zero). For complex inputs, two power meters can be use to measure the combined complex power and two can be disabled.

6 RECEIVE DIGITAL SIGNAL PROCESSING

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21−bit

integration

counter

clear

sync

delay

sync

event

58−bit

Integrator

58−bit

9−bit

sync delay

counter

21−bit

interval

counter

transfer

sync

delay

(in 8 sample

increments)

integration

(in 8 sample

increments)

21219

RMS power

integration time

interval time

integration

start

integration

start

integration

start

interval

(in 8 sample

increments)

integration time integration time

8-CHANNEL WIDEBAND RECEIVER

GC5018

SLWS169 – MAY 2005

Power is calculated by squaring each 18 bit I (I and Q for complex inputs) sample, summing, and then integrating the summed-squared results into a 58 bit accumulator over a programmable integration period. The integration period is programmed into the 21 bit counter, in 8 sample increments. The power read is:

power = [ (I2) x (Xx8 + 1) ] for real inputs where X is the integration count. power = [ (I2+ Q2)x (Xx8 + 1) ] for complex inputs where X is the integration count.

A programmable 21 bit interval counter sets the power measurement interval (how often power will be measured) in 8 sample increments. A measurement integration period is started at the beginning of each interval period.

The process begins with a sync event starting the 9 bit delay counter. After (8xsync_delay + 2) samples, the integration interval is started. Integration continues until the integration count is met, at which point the 58 bit integrator results are transferred to the read only register and an interrupt is generated. A new measurement period will start at the end of the interval period.

Each of the four composite RMS power meter blocks has its own delay sync, interval, and integration period counters, as well as separate sync source registers.

The 21-bit counters in 8 sample increments allow up to 104.8mS interval times at 160MHz clock.

NOTE

RECEIVE DIGITAL SIGNAL PROCESSING 7

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PRODUCT PREVIEW

freeze control register bit

freeze from sync source

clear control register bit

clear sync source

Map

Table

MSBs

Gain

Map

Table

Filter

update

Map

Table

clip_hi_thresh

clip_low_thresh

clip detect controls

delay adjust

sd_thresh

signal detect

mode controls

128w x 8b ram

update

sync

delay

Samples

from

ADC FIFO

integrate and dump signal power measurement

enable corner

no_signal

err_shift

acc_shift

limit

{127..0}

−

DVGA

Map

Table

Gain

Map

Table

Highpass

Filter

Error

Map

Table

Mag

Clip

Detect

clip_error

Signal

64w x 22b RAM

update interval

loop accumulator

to DVGA

pins

to DDC

channels

acc_shift

shift

limit

Delay

acc_offset

limit

{127..0}

−

Level

Detect

error shift

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

PROGRAMMING

VARIABLE DESCRIPTION

recv_pmeterX (57:0) 58 bit power measurement result. X= {0,1,2,3}. recv_pmeterX_sqr_sum(20:0) 21 bit integration (square and sum) period. X= {0,1,2,3}. recv_pmeterX_sync_delay(8:0) Power meter delay sync period. X= {0,1,2,3}. recv_pmeterX_strt_intrvl(20:0) 21 bit measurement interval. X= {0,1,2,3}. The strt_intrvl value must be greater than the sqr_sum value. ssel_recv_pmeter_X(2:0) Sync source. X= {0,1,2,3}. pmeterX_iq Selects complex power measurement input mode when set. X= {0,1,2,3}. recv_pmeterX_ena Enables power meter when set. X= {0,1,2,3}.

3.1.3 Receive Input AGC (RAGC)

Input signals from the ADCs can be used to create a front end composite AGC loop when combined with a digitally controlled variable gain amplifier (DVGA) connected before the ADCs. The AGC system operates by integrating the square of the ADC samples over a programmable interval and applying a table driven error signal to a loop integrator based on the squared integration output. The error table maps the signal power to a user programmed error value. The loop integrator output is used to drive map tables to control the DVGA output pins and a gain adjustment multiplier. Fast updates can be enabled if desired, to cause the loop integrator to quickly adjust to interfering signals. The ADC input signals can also be passed through a high pass filter to remove DC offset before squaring the input.

The programmable error table, integrator mapping tables, and clip thresholds, when combined with the user programmable interval timers provide a highly flexible AGC function.

8 RECEIVE DIGITAL SIGNAL PROCESSING

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GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

The AGC measurement interval timer is a 24-bit timer initialized by a sync after a programmable 8-bit delay. During the integration interval, the squared input signal is shifted by the programmed value and accumulated. At the end of the interval time, an update pulse is generated, and the selected 7 bits of the 55-bit accumulated power is upper limit checked and transferred to the power holding register. A programmable offset is applied, and the following limit check produces a 7 bit address value for the error map table RAM. The user programmable error map table and following gain shift setting are used to determine the loop error signal to be added to the 32-bit AGC loop accumulator. The error value is only added to the loop accumulator once per update. The loop accumulator upper 6 MSBs are used as the address for the programmable DVGA map table and gain map table. The gain map table address can be delayed from 0 to 31 clock cycles to align DVGA changes to signal level changes at the output of the AGC.

The AGC includes four sources for freezing the loop and holding the loop accumulator constant. A general sync source can be used to directly control the freeze; when the selected sync source is high, the AGC will be held, and when low, the AGC will operate. A control register bit freezes the AGC in the same fashion; when the bit is set, the AGC is held, and when cleared, the AGC will operate. A signal level detector is provided that can be used to automatically freeze the AGC loop in the event of input signal loss. A programmable signal detection threshold value, number of samples below the signal detection threshold, and window timer are used to determine when no signal is present. Finally, a programmable number of AGC updates after sync can be programmed, and the AGC will he held until the next sync event. Freeze holds the loop accumulator constant, the integrate and dump accumulator constant and the interval timer constant. When freeze is released, the interval timer will resume counting.

A sync event will always reinitialize the integrate and dump interval timer, and terminate the pending update to the loop accumulator from the current integrate and dump measurement interval. For example, if a sync event occurs during an integrate and dump interval, that interval will be terminated without updating the loop, and the integrate and dump accumulator will be cleared. After the programmed sync delay, a new interval will start.

The AGC includes a dual threshold clip detect function, using two programmable 16-bit thresholds and programmable counters. The clip detector will cause immediate loop accumulator updates while the clip event is active. The 16-bit clip error value is aligned at the MSBs of the loop accumulator. Clip events are qualified when a programmed number of samples are above the high clip threshold during the programmable clip window time. For example, a clip event can be defined as 8 samples above the clip high threshold in a 256 sample window; the clip high threshold, the number of samples above the high clip threshold and the sample window time are programmable. Once the clip event has occurred, the clip duration is controlled by the clip low threshold value, clip low samples value and clip low timer. The clip event is cleared when the number of samples below the low clip threshold exceeds the programmed value within the clip low timer window. The clip low threshold, number of clip low samples and the clip low window timer are programmable.

The AGC blocks can be paired together, rxin_a with rxin_b, and rxin_c with rxin_d, to produce a complex input AGC mode. The clip detector output from the rxin_b/d AGCs is logically OR’ed with the rxin_a/c clip detect outputs. The squared input function before the integrate and dump and signal level detector is replaced with a I2+ Q

power calculation. The accumulator MSBs from the rxin_a/c AGCs are connected to the rxin_c/d DVGA map table and gain map table inputs. This arrangement allows the AGCs to operate in a direct conversion receiver system by controlling the I2+ Q

complex signal level.

The highpass filter is a 32 bit accumulator followed by an adjustable shift to control the corner frequency, a subtractor to remove the accumulated offset and a final limiter to produce a 16 bit result. The highpass filter function is enabled by setting hp_ena; clearing hp_ena holds the accumulator reset.

RECEIVE DIGITAL SIGNAL PROCESSING 9

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PRODUCT PREVIEW

hp_corner

shift

limit

16 16

limit

−

Samples

from

ADC FIFO

Samples to

X2 block

hp_ena

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

VARIABLE DESCRIPTION

ragc_bypass_X Bypasses the entire receive AGC circuit when set. X = {0,1,2,3} hp_ena_X Enables high pass filter when set hp_corner_X(2:0) Adjusts the corner frequency of the high pass filter integ_interval_X(23:0) Integrate and dump signal power measurement interval in samples. acc_shift_X(4:0) Shift down amount following the integrate and dump accumulator. acc_offset_X(5:0) Offset value applied to the shifted integrate and dump output. ragc_sync_delay_X(7:0) AGC sync delay interval, from 1 to 256 samples. ssel_ragc_interval_X(2:0) Sync source selection for the interval timer. ssel_ragc_freeze_X(2:0) Sync source selection for AGC freeze ssel_ragc_clear_X(2:0) Sync source selection for the AGC loop accumulator clear ragc_freeze_X Register bit to freeze the AGC when set ragc_clear_X Register bit to clear the AGC accumulator when set ragc_update_X(7:0) Sets the number of updates per sync event, after which no further updates will occur until the next sync

sd_ena_X Enables freezing the AGC with the signal detector when set sd_thresh_X(15:0) Signal detection threshold for AGC channel X. This 16 bit word is lined up with bits 23 down to 8 of the

sd_samples_X(15:0) The number of samples below the signal detect threshold within the signal detect sample timer window

sd _timer_X(15:0) Window timer to qualify signal detection. clip_hi_thresh_X(15:0) Clip detector high threshold clip_lo_thresh_X(15:0) Clip detector low threshold clip_hi_samples_X(7:0) A clip event is detected when this number of samples above the clip high threshold within the clip high

clip_lo_samples_X(7:0) A clip event ends when this number of samples below the clip low threshold within the clip low sample

clip_hi_timer_X(15:0) Window timer to qualify clip events. clip_lo_timer_X(15:0) Window timer to determine when the clip event ends. clip_error_X(15:0) Error signal applied to the AGC accumulator when a clip event is active. This data is MSB aligned, and

ragc_error_map_X 128w x 8b memory holding the log to error look up table. dvga_map_X 64w x 6b memory holding the accumulator to DVGA look up table gain_map_X 64w x 16b memory holding the accumulator to GAIN look up table (256 decibels is unity gain). delay_adj_X(4:0) Delay between DVGA output updates and gain map updates to compensate for ADC pipeline delays,

err_shift_X(4:0) Error map table output shift up before adding to loop accumulator complex_01 Enables complex AGC mode on inputs rxin_a and rxin_b when set complex_23 Enables complex AGC mode on inputs rxin_c and rxin_d when set

10 RECEIVE DIGITAL SIGNAL PROCESSING

PROGRAMMING

event. Program to 0x00 to continually update.

square output. The smallest signal level is that can be programmed is therefor 16 LSBs on the ADC input, and the largest is 4095 LSBs at the ADC input.

required to freeze on the AGC.

sample timer window exceeds this value.

timer window exceeds this value.

therefor can cause immediate changes to the accumulator.

etc.

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LFSR

0522

initialized on sync event − each of the four generators has a different seed

adcclk_X

sync lfsr(22:0)

8-CHANNEL WIDEBAND RECEIVER

PROGRAMMING

VARIABLE DESCRIPTION

ragc_accum_X(31:0) 32-bit read only register holding the current contents of the loop accumulator. tristate(10:7) 3-state controls for the dvga_d/c/b/a output pins; pins are in tristate when the 3-state bits are set. ragc_mpu_ram_read What set, the receive AGC map rams are readable via the MPU control interface. The GC5018 signal

path is not operational when this bit is set, it is intended for debug purposes only.

3.1.4 Test and Noise Signal Generator

The test and noise generator can generate test signals to replace the rxin_a/b/c/d inputs as a tool for debug, evaluation and self test. Checksum generators included in the individual DDC channels at the outputs can be used in conjunction with the noise generator and the internal sync timer block to create the built in self test function.

The test and noise signal source included in this block is a 23-bit linear feedback shift register (LFSR) with a fixed polynomial and fixed initialization state. A sync input is required to initialize the LFSR, and the sync source is connected to the ddc_counter output signal.

GC5018

SLWS169 – MAY 2005

Receive Input Port LFSR Seed Value, MSB to LSB

rxin_a 100 0000 0000 0000 0001 0000 (0x400010) rxin_b 010 0110 1110 0110 1100 1110 (0x26E6CE) rxin_c 110 1110 1010 0010 1001 1000 (0x6EA298) rxin_d 000 1011 0001 1110 1011 0111 (0x0B1EB7)

11RECEIVE DIGITAL SIGNAL PROCESSING

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PRODUCT PREVIEW

lfsr(22) lfsr(20)

lfsr(22) lfsr(16)

lfsr(22) lfsr(15)

lfsr(22) lfsr(14)

lfsr(22) lfsr(13)

lfsr(22) lfsr(12)

lfsr(22) lfsr(11)

dout(15)

dout(14)

dout(13)

dout(12)

dout(11)

dout(10)

lfsr(19)

lfsr(18)

lfsr(17)

lfsr(16)

lfsr(15)

lfsr(14)

lfsr(13)

lfsr(12)

lfsr(11)

lfsr(10)

dout(9)

dout(8)

dout(7)

dout(6)

dout(5)

dout(4)

dout(3)

dout(2)

dout(1)

dout(0)

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

The 23-bit LFSR output signal if used to create a 16-bit “dout(15:0)” test signal using XOR combinations of the LFSR bits.

To enable the test signal generator, the slf_tst_ena control bit is set. The rxin_a/b/c/d signals will be then replaced by the four generator output streams. To use this test signal generator as a signal source for self test, the user must also set the adc_fifo_bypass control bit. Setting the adc_fifo_bypass control bit causes the adcclk_a/b/c/d input clocks to be internally replaced with rxclk/N, where N is as programmed with the rate_sel(1:0) control bits to {1,2,4 or 8}.

The test signal generators can also output a programmable constant value. All four test signal generators output the same programmable constant value.

12 RECEIVE DIGITAL SIGNAL PROCESSING

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data to FIFO for rxin_a

data to FIFO for rxin_b

data to FIFO for rxin_c

data to FIFO for rxin_d

rxin_a

Test and

Noise

Generator

sync

rxin_b

rxin_c

rxin_d

slf_tst_ena

rduz_sens_ena

Test and

Noise

Generator

Test and

Noise

Generator

Test and

Noise

Generator

lfsr(17) lfsr(16)

rxin_X(15:0)

lfsr(15:0)

to FIFO for rxin_X

nz_pwr_mask(15:0)

16 XORs

16 ANDs

rduz_sens_ena

8-CHANNEL WIDEBAND RECEIVER

GC5018

SLWS169 – MAY 2005

slf_tst_ena When set, the test signal generators replace the rxin_a/b/c/d input signals with internally generated

rduz_sens_ena Enables the LFSR, adding noise to the ADC input data when set. nz_pwr_mask(15:0) Selects the power of the noise added to the ADC input data. adc_fifo_bypass When set, the FIFO is essentially bypassed, and the adcclk_a/b/c/d clock input ports are ignored. ddc_counter(31:0) 32 bit general purpose counter interval ddc_counter_width(7:0) 8 bit general purpose counter timeout width pulse ssel_ddc_counter(2:0) Sync source selection for the general purpose counter self_test_constant(17:0) 18-bit self test constant value applied to all 4 rxin_a/b/c/d inputs when self_test_const_ena is set. self_test_const_ena Enables the self test constant value for rxin_a/b/c/d

The LFSR circuits can also be used to add noise to the rxin_a/b/c/d input signals by setting the rduz_sens_ena control register bit. The magnitude of the noise added can be adjusted by programming the nz_pwr_mask(15:0) control register. In the figure below, X = {a,b,c or d}.

VARIABLE DESCRIPTION

psuedo random sequences. The fifo_bypass bit must be set when this bit is set.

PROGRAMMING

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PRODUCT PREVIEW

DDC0

MUX

Receive Interface

rxin_a& rxin_bFIFO outputs

DDC1

DECIMATE

tst_decim17

tst_decim_delay

(35:20) (19:18) (17:2) (1:0) tst_clk tst_aflag tst_sync

rxin_d(15:0)

rxin_c(15:0)

dvga_c(3:2)

dvga_c(5:4)

dvga_d(5) dvga_c(0)

dvga_c(1)

sync

pfiroutput

cfiroutput

zeros

tadjchannel A

tadjchannel B

ncosin

ncocos

cicoutput

mixer i*cos& i*sin

mixer q*cos& q*sin

ddcmuxchannel A

ddcmuxchannel B

ddc_tst_sel(5:0)

DDC2

DDC3

DDC4

DDC5

DDC6

DDC7

MUX

tst_select(3:0)

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

3.1.5 Sample Delay Lines

The four sample delay line blocks each consist of a 64 register memory and a state machine. The state machine uses a counter to control the write (input) pointer, and the programmed read offset register data to create the read (output) pointer. Programming larger read offset register values increases the effective delay at a resolution equal to the sample rate.

The read offset registers, delay_line_X, are double buffered. Writes to these registers may occur anytime, but the actual values used by the circuit will not be updated until a delay line sync event occurs.

PROGRAMMING

VARIABLE DESCRIPTION

delay_line_X(5:0) Read offset into the 64 element memory for each delay line. X= {0,1,2,3}. ssel_delay_line_X(2:0) Selects the sync source used to update the double buffered delay line register.

3.1.6 Test Bus

When the test bus is enabled, the rxin_c(15:0) and rxin_d(15:0) ports become outputs, and the dvga_c and dvga_d pins are combined with these pins to allow 36 bit wide signals from the DDC channels and the receive input interface to be multiplexed to this test output port. Many of these sources can be decimated to reduce the output sample rates.

RECEIVE DIGITAL SIGNAL PROCESSING14

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DDC5

DDC4

DDC3

DDC2

DDC1

4 to 2 (complex) or

4 to 1 (real) switch

4 to 2 (complex) or

4 to 1 (real) switch

CDMA DDC A

CDMA DDC B

Output

Interface

or 1 UMTS DDC

DDC0

18 18 18 18

DDC6

DDC7

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

PROGRAMMING

VARIABLE DESCRIPTION

ssel_tst_decim(2:0) Selects the sync source for the testbus decimator tst_decim_delay(3:0) Sets the testbus decimator delay from sync tst_decim17 When set the decimation factor of the test bus output block is 17X. When cleared, the decimation factor

is 16X if the fuse is blown, 1X (no decimation) with the fuse intact.

tst_on Enables the test bus; rxin_c(15:0) and rxin_d(15:0) are changed from inputs to outputs, dvga_c(5:0) and

dvga_d(5) are used as part of the test bus. tst_select(3:0) Selects the source block for the testbus output; DDC0-7 or Receive Interface. ddc_tst_sel(5:0) Selects the signal to be output from the DDC block tst_rate_sel(4:0) Sets the testbus output clock tst_clk period to (tst_rate_sel + 1) rxclk cycles.

3.2 DDC Organization

GC5018

The GC5018 provides downconversion for up to 8 UMTS receive channels, 16 CDMA2000 receive channels or 16 TD-SCDMA receive channels. Downconversion channels are organized into 8 DDC blocks. Each individual DDC block provides 2 CDMA2000 or 2 TD-SCDMA DDC channels, A and B, or 1 UMTS channel.

Both CDMA DDC channels in a DDC block can be independently tuned, though they would likely be used as diversity pairs and tuned to the same frequency. Filter coefficients are shared between the two CDMA DDC channels within a block.

Two adjacent DDC blocks (for example, DDC0 and DDC1) can be strapped together to form a single UMTS DDC channel with double-length final pulse shaping filtering. The GC5018 can therefore provide 4 UMTS DDC channels with double-length final PFIR filtering as shown in the following diagram.

RECEIVE DIGITAL SIGNAL PROCESSING 15

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PRODUCT PREVIEW

DDC6 plus DDC7

DDC4 plus DDC5

4 to 2 (complex) or

4 to 1 (real) switch

4 to 2 (complex) or

4 to 1 (real) switch

CDMA DDC A

CDMA DDC B

Output

Interface

4 UMTSDDCs with up to 128 tap PFIR

DDC0

18 18 18 18

4 to 2 (complex) or

4 to 1 (real) switch

4 to 2 (complex) or

4 to 1 (real) switch

CDMA DDC A

CDMA DDC B

Output

Interface

or 1 UMTS DDC

DDC1

DDC2 plus DDC3

DDC0 plus DDC1

4 to 2 Select

18 18 18 18

32 16

Frequency

Phase

NCO

Delay

Adjust

Zero

Pad

Six Stage

CIC Filter

Dec 4 to 32

CFIR Filter

Dec by 2

PFIR Filter

Dec by 1

AGC

Serial

Interface

RMS Power

Measure

serial I, Q up to 18 (25−bits with

AGC disabled)

from

rx_distribution

bus

Checksum Generator

parallel I, Q

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

VARIABLE DESCRIPTION

ddc_ena When set, turns on the DDC. cdma_mode When set, puts the DDC block in dual channel CDMA mode. gbl_ddc_write When set, all subsequent programming (writes only) for DDC0 and DDC1 is also written to DDC2/4/6 and DDC3/5/7.

3.2.1 Downconverter Function Blocks

Each GC5018 downconversion block can process two CDMA carriers or a single UMTS carrier. Signal data is selected from one of four ports for real inputs, or two of four ports for complex inputs. Data from the selected port(s) is multiplied with a complex, programmable numerically controlled oscillator (NCO)

PROGRAMMING

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3.2.2 DDC Mixer

4 to 2

Select

18 18 18 18

Demux

and

Round

from

rx_distribution

bus

18 18

sin

cos

from NCO

18 18 18 18

channel

delay

mixer_gain

GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

which tunes the signal of interest to baseband. The delay adjust and zero pad blocks permits adjustment of the delay in the end-to-end channel. Zero padding interpolates the signal to the rxclk rate. Filtering consists of a six stage CIC filter which decimates the tuned data by a factor from 4 to 32, a compensating FIR filter (CFIR) which decimates by a factor of two, followed by a programmable FIR filter (PFIR) which does not decimate. The output interface block can be programmed to decimate by 2 if desired.

The RMS power meter measures the power within the channel’s bandwidth. The AGC automatically drives the gain and keeps the magnitude of the signal at a user-specified level. This allows fewer bits to represent the signal. The serial output interface formats and rounds the output data. Each of the above blocks is described in greater detail in the following sections.

The receive mixer translates the input (from one of the input signal sources) to baseband where subsequent filtering is performed to isolate the signal of interest. The mixer is a complex multiplier that accepts 18 bit I and 18 bit Q signal data from the receive input interface and 20 bit Sine and Cosine sequences from the NCO. The NCO generates a mixing frequency (sometimes referred to as a local oscillator, or LO) specified by the user so that the desired signal of interest is tuned to 0 Hertz.

A DDC channel can support one UMTS signal directly, or two CDMA channels at half the input rate. When in CDMA mode each channel may set independently; the path selection and the mixer tuning and phase. The mixer output produces two complex streams; one representing the signal path for the A-side DDC, the other the B-side. Each of these streams drives a channel delay and zero pad block.

The maximum input rate for UMTS is rxclk for either real or complex input data. The maximum input rate in CDMA mode with real inputs is rxclk (remix_only is set, see below). The maximum input rate in CDMA mode with complex inputs is rxclk/2 due to sharing of multiplier

resources.

PROGRAMMING

VARIABLE DESCRIPTION

ddcmux_sel_a(3:0) Programs the I and Q complex input data routing onto two of the four input ports for stream A of CDMA DDC ddcmux_sel_b(3:0) Programs the I and Q complex input data routing onto two of the four input ports for stream B of CDMA DDC remix_only For CDMA mode only, set this bit for real input data at the rxclk rate.

For complex inputs in CDMA mode, the maximum input data rate is rxclk/2, and this bit must be cleared. For CDMA mode with real inputs at the rxclk/2 rate or lower, this bit must be cleared

zero_qsample When set, the Q samples used by the mixer are always zero. This bit should be set for real only inputs in UMTS

ch_rate_sel(1:0) Specifies the input channel data rate (rxclk, rxclk/2, rxclk/4, or rxclk/8 MSPS). mixer_gain When asserted, adds 6dB of gain in the mixer. This gain is highly recommended.

mode, or real only inputs in CDMA mode when the input sample rate is rxclk/2 or lower.

RECEIVE DIGITAL SIGNAL PROCESSING 17

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PRODUCT PREVIEW

Reg

Frequency Word

Frequency Sync

Reg

Zero Phase Sync

Clear

Reg

Phase Offset

Phase Offset Sync

Aligned

to top

32 bits

sin/cos

table

Dither

Generator

Dither Sync

Aligned

to bottom

5 bits

cos

sin

a) Worst Case Spectrum Without Dither

b) Spectrum With Dither (Tuned to Same Frequency

GC5018 8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

3.2.3 DDC Number Controlled Oscillator (NCO)

The NCO is a digital complex oscillator that is used to translate (or downconvert) an input signal of interest to baseband. The block produces programmable complex digital sinusoids by accumulating a frequency word which is programmed by the user. The output of the accumulator is a phase argument that indexes into a sin/cos ROM table which produces the complex sinusoid. A phase offset can be added prior to indexing if desired for channel calibration purposes. This will change the sin/cos phase with respect to other channels’ NCOs.

A 5-bit dither generator is provided and generates a small level of digital pseudo-noise that is added to the phase argument below the bottom bits and is useful for reducing NCO spurious outputs. This dither generation is enabled by setting the dither_ena bit; the magnitude of the dither can be reduced by setting one or both of the dither_mask bits

VARIABLE DESCRIPTION

dither_ena When set turns dither on. Clearing turns dither off. dither_mask(1:0) Masks the MSB and MSB-1 dither bits, respectively, when set.

The NCO spurious levels are better than –115 dBC. Added phase dither randomizes the periodic nature of the phase accumulation process and reduces low-level spurious energy. For some frequencies (KxFs/24) dither is ineffective – in these cases an initial phase of 4 reduces NCO spurs. The figures below show the spur level performance of the NCO without dither, with dither, and with a phase offset value.

DITHER PROGRAMMING

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a) Plot Without Dither or Phase Initialization

b) Plot With Dither or Phase Initialization

GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

The tuning frequency is specified as a 32 bit Frequency Word and is programmed as two sequential 16 bit words over the control port. The NCO frequency resolution is Fclk/ 232. As an example, at an input clock rate of 61.44 MHz, the frequency step size would be approximately 14 milli-Hertz. The Frequency Word is determined by the formula:

Frequency Word (in decimal)= 2

Note that frequency tuning words can be positive or negative valued. Specifying a positive frequency value translates complex negative frequencies upwards towards 0 Hertz. Specifying a negative tuning frequency translates complex positive frequencies downwards towards 0 Hertz.

x Tuning Frequency / F

clk

FREQUENCY PROGRAMMING

VARIABLE DESCRIPTION

phase_add_a(31:0) 32 bit tuning frequency word for the A-side DDC when in CDMA mode. Also for UMTS mode. phase_add_b(31:0) 32 bit tuning frequency word for the B-side DDC when in CDMA mode. Not used in UMTS mode.

Each of the 16 CDMA DDC channels can be loaded with unique frequency words. The phase of the NCO’s Sin/Cos output can be adjusted relative to the phase of other channel NCOs by

specifying a Phase Offset. The Phase Offset is programmed as a 16 bit word, yielding a step size of about

5.5 m°. The Phase Offset Word is determined by the formula: Phase Offset Word = 2 Phase Offset Word = 2

VARIABLE DESCRIPTION

phase_offset_a(15:0) 16 bit phase offset word for the A-side DDC when in CDMA mode. Also for UMTS mode. phase_offset_b(15:0) 16 bit phase offset word for the B-side DDC when in CDMA mode. Not used in UMTS mode.

x Offset_in_Degrees / 360 or,

x Offset_in_Radians / 2 π

PHASE PROGRAMMING

Each of the 16 CDMA DDC channels can be loaded with unique phase offset words. Various synchronization signals are available which are used to synchronize the NCOs of all channels

with respect to each other. Frequency Sync and Phase Offset Sync determine when frequency and phase offset changes occur. For example, generating a Frequency Sync after programming the two frequency words will cause the NCO (or multiple NCOs) to change frequency at that time, rather than after each of the three frequency words is programmed over the control bus. The Zero Phase Sync signal is used to force the sine and cosine oscillators to their zero phase state. Dither Sync can be used to synchronize the dither generators of multiple NCOs. The NCOs used in the transmit section are identical to what is described for the receive section. Note that there is one set of sync’s provided for each DDC. When one DDC is used to process two CDMA signals, the syncs are shared between them.

RECEIVE DIGITAL SIGNAL PROCESSING 19

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PRODUCT PREVIEW

Delay Adjust

Zero Pad

Interp by {1,2,4,8}

Six Stage

CIC Filter

Dec by {4 −32}

CFIR Filter

Dec by 2

PFIR Filter

no decimation

Output Interface

Dec by {1,2}

Delay Adjust

Zero Pad

Interp by {1,2,4,8}

Six Stage

CIC Filter

Dec by {4 −32}

CFIR Filter

Dec by 2

PFIR Filter

no decimation

From

Mixer

GC5018 8-CHANNEL WIDEBAND RECEIVER

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SYNC PROGRAMMING

VARIABLE DESCRIPTION

ssel_nco(2:0) Sync source for NCO accumulator reset ssel_dither(2:0) Sync source for NCO dither reset ssel_freq(2:0) Sync source for NCO frequency register loading ssel_phase(2:0) Sync source for NCO phase register loading

3.2.4 DDC Filtering and Decimation

The purpose of the receive filter chain is to isolate the signal of interest (and reject all other others) that has been previously translated to baseband via the mixer and NCO. The overall decimation through the chain needs to be considered. The goal, generally, is to output the isolated signal at a rate that is twice (2X) the signal’s chip rate. For UMTS this would be 7.68 MSPS and for CDMA the output rate should be

2.4576 MSPS. TD-SCDMA systems require the output rate be the chip rate of 1.28 MSPS. The output

interface is programmed to decimate by 2 for the TD-SCDMA case. Receive filtering and decimation is performed in several stages:

• Zero padding to interpolate the input sample rate (if needed) up to the rxclk rate

• High rate decimation (4 to 32) using a six stage cascade-integrate-comb filter (CIC)

• Decimate by two compensation filtering using the programmable compensating FIR filter (CFIR)

• Pulse-shape filtering via the programmable FIR filter (PFIR) with no decimation

• Output interface, serial or parallel format, with no decimation or decimate by 2

The table below contains some examples of decimation and sample rates at the output of each block for UMTS, CDMA and TD-SCDMA standards at various supported input samples. For each example, the differential ADC clocks are provided to the GC5018 at the input sample rate and the rxclk is provided at the zero pad output rate.

20 RECEIVE DIGITAL SIGNAL PROCESSING

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input rate

samples from

Mixer

read offset

insert offset

sync (zero stuff moment)

Zero

Pad

Delay Memory

I:8 slots x 18−bits

Q:8 slots x 18−bits

18 18

full rxclk rate

samples to

CIC Filter

sync (offset registers)

interpolation

(number of zeros stuffed between samples)

GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

Table 3-1. Examples of Decimation and Sample Rates

Input Zeros rxclk(MHz) and CIC CIC Out- CFIR CFIR PFIR PFIR Out- Output

Sample Added Zero Pad Decimation put Rate Decimation Output Decimation put Rate Decimation

Rate Output Rate (MSPS) Rate (MSPS)

(MSPS) (MSPS) (MSPS)

UMTS 122.88 0 122.88 8 15.36 2 7.68 1 7.68 1 UMTS 92.16 0 92.16 6 15.36 2 7.68 1 7.68 1 UMTS 76.80 1 153.6 10 15.36 2 7.68 1 7.68 1 UMTS 61.44 1 122.88 8 15.36 2 7.68 1 7.68 1

CDMA 122.88 0 122.88 25 4.9152 2 2.4576 1 2.4576 1 CDMA 78.6432 0 78.6432 16 4.9152 2 2.4576 1 2.4576 1 CDMA 78.6432 1 157.2864 32 4.9152 2 2.4576 1 2.4576 1 CDMA 61.44 1 122.88 25 4.9152 2 2.4576 1 2.4576 1

TD-SCDMA 92.16 0 92.16 18 5.12 2 2.56 1 2.56 2 TD-SCDMA 81.92 0 81.92 16 5.12 2 2.56 1 2.56 2 TD-SCDMA 76.80 0 76.80 15 5.12 2 2.56 1 2.56 2 TD-SCDMA 76.80 1 153.6 30 5.12 2 2.56 1 2.56 2 TD-SCDMA 1 122.88 24 5.12 2 2.56 1 2.56 2

(1)

(1) The DDC output interfaces, both serial and parallel formats, can be programmed to decimate by 2. For the TD-SCDMA examples listed

above, the DDC output rate is 1.28Msps (1x chip rate).

3.2.5 DDC Channel Delay Adjust and Zero Insertion

The Receive Channel Delay Adjust function is used to add programmable delays in the channel downconvert path. Adjusting channel delay can be used to compensate for analog elements external to the GC5018 digital downconversion such as cables, splitters, analog downconverters, filters, etc.

The Delay Memory block consists of an 8 register memory and a state machine. The state machine uses a counter to control the write (input) pointer, and the programmed read offset register data to create a read (output) pointer. Programming larger read offset register values increases the effective delay at a resolution equal to the input sample rate.

The Zero Pad block is used in conjunction with the Delay Memory for delay adjustments. For example, with input rates of rxclk/8, the Zero Pad block interpolates the input data to rxclk by inserting 7 zeros. The Zero Pad’s sync insert offset 3-bit control specifies when the zeros are inserted relative to the Sync signal. This permits a fine adjustment at the rxclk resolution.

RECEIVE DIGITAL SIGNAL PROCESSING 21

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PRODUCT PREVIEW

−1

−m1

−1

−m2

−m 3

−m 4

−m5

−m 6

Shift

m1, m2,m3, m4, m5, m6 = 1 or 2

Decimate

by 4−32

Round

Limit

Shift 0−31

GC5018 8-CHANNEL WIDEBAND RECEIVER

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The read offset register, tadf_offset_course_a/b, and the insert offset register, tadj_offset_fine_a/b, are double buffered. Writes to these registers may occur anytime, but the actual values used by the circuit will not be updated until a register sync

PROGRAMMING

VARIABLE DESCRIPTION

tadj_offset_coarse_a(2:0) Read offset into the 8 element memory for the UMTS or CDMA mode A channel DDC. tadj_offset_coarse_b(2:0) Read offset into the 8 element memory for the CDMA mode B channel DDC when in CDMA mode. tadj_offset_fine_a(2:0) Controls the zero pad (or stuff) insert offset (fine adjust) for the UMTS or CDMA mode A channel of the

tadj_offset_fine_b(2:0) Controls the zero pad (or stuff) insert offset (fine adjust) for the CDMA mode B channel of the DDC

tadj_interp(2:0) The interpolation value (1, 2, 4, or 8). Same used for both the A and B channels when in CDMA mode.

ssel_tadj_fine(2:0) Selects the sync source for the fine time adjust zero stuff moment. Same for A and B channels when in

ssel_tadj_reg(2:0) Selects the sync source used to update the double buffer course and fine delay selection registers.

3.2.6 DDC CIC Filter

DDC.

when in CDMA mode.

Selects the number of zeros to be inserted.

CDMA mode.

Same for A and B channels when in CDMA mode.

The CIC filter provides the first stage of filtering and large-value decimation. The filter consists of six stages and decimates over a range from 4 to 32.

I data and Q data are handled separately with two CIC filters. In addition, when in CDMA mode (two CDMA channels processed within a single DDC), another pair of CIC filters handles the B-side channel.

The filter response is 6x(Sin(x)/x) in character where the key attribute is that the resulting response nulls reject signal aliases from decimation. A consequence of this desirable behavior is that only a small portion of the passband can be used, less than 25% generally. This means that the CIC decimation value should be chosen so that the signal exiting the CIC filter is oversampled by at least a factor of four.

The filter is equivalent to 6 stages of a FIR filter with uniform coefficients (6 combined boxcar filter stages). Each filter would be of length N if m=1, or 2N if m=2.

The filter is made up of six banks of 54 bit accumulator sections followed by six banks of 24 bit subtractor sections. Each of the subtractor sections can be independently programmed with a differential delay of either one or two. A shift block follows the last integration stage and can shift the 54 bit accumulated data down by 36-rcic_shift (a programmable factor from 0 to 31 bits).

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GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

The CIC filter exhibits a droop across its frequency response. The following CFIR filter compensates for the CIC droop with a gradually rising frequency response. It is also possible to compensate for CIC droop in the PFIR filter.

The gain of the receive CIC filter is:

Ncic

(number of stages where M=2)

x 2

There is no rollover protection internal to the CIC or at the final round so the user must guarantee no sample exceeds full scale prior to rounding. For practical purposes this means the CIC gain can only compensate for peak gain less than one or must be less than or equal to one. A fixed gain of +12 dB at the output of the CIC can also be programmed.

VARIABLE DESCRIPTION

cic_decim(4:0) The CIC decimation ratio (4 to 32). The ratio is cic_decim + 1. This ratio applies to both A and B channels of

cic_scale_a(4:0) The shift value for the A channel. A value of 0 is no shift, each increment in value increases the amplitude of

cic_scale_b(4:0) The shift value for the B channel. A value of 0 is no shift, each increment in value increases the amplitude of

cic_gain_ddc When asserted, adds a gain of 12 dB at the CIC output. cic_m2_ena_a(5:0) Sets the differential delay value M for each of the CIC subtractor stages for the UMTS or CDMA mode A

cic_m2_ena_b (5:0) Sets the differential delay value M for each of the CIC subtractor stages for the CDMA mode B channel. cic_bypass Bypasses the CIC filter when set, for factory testing. ssel_cic(2:0) Sets syncing (1 of 8 sources) for the CIC decimation moment.

the DDC block in CDMA mode.

the shifter output by a factor of 2.

channel.

(–36+RCIC_SHIFT)

x 2

PROGRAMMING

where RCIC_SHIFT is 0 to 31.

3.2.7 DDC Compensating FIR Filter (CFIR)

The receive compensating FIR filter (CFIR) decimates the output of the CIC filter by a fixed factor of two. Filter coefficient size, input data size, and output data size are 18 bits. The CFIR length can be programmed. This permits “turning off” taps and saving power if shorter filters are appropriate (the CFIR power dissipation is proportional to its length).

The filter is organized in two partial filter blocks, each containing a data RAM, a coefficient RAM and a dual multiplier, a common state machine and output accumulator.

RECEIVE DIGITAL SIGNAL PROCESSING 23

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PRODUCT PREVIEW

MPU control

interface

complex

input

samples

COEF RAM 32x18

DATA

RAM 64x36

reg

complex

output

samples

crastarttap

State Machine

output

sample

valid

read pointer

write

pointer

write pointer

MUX

read pointer

mpu

ram_read

read data

write data

COEF

RAM

32x18

DATA

RAM

64x36

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The maximum CFIR filter length is a function of GC5018 clock rate, output sample rate and the number of coefficient memory registers. The maximum number of taps is 64 and the minimum number is 14. Lengths between these limits can be specified in increments of 2.

Subject to the above minimum and maximum values, in the general case, the number of taps available is:

UMTS Mode: 2 x (rxclk ÷ output sample rate)

Mode rxclk CIC CFIR CFIR COMMENTS

UMTS 153.60 10 40 14 UMTS UMTS 122.88 8 32 14 UMTS CDMA 157.2864 32 64 14 CDMA2000 CDMA 122.88 25 48 14 CDMA2000 CDMA 78.6432 16 32 14 CDMA2000 low power configuration CDMA 153.60 30 60 14 TD-SCDMA CDMA 81.92 16 32 14 TD-SCDMA CDMA 76.80 15 28 14 TD-SCDMA low power configuration

CDMA Mode if cic_decim is even (decimating by an odd number): 2 x (cic_decim) CDMA Mode if cic_decim is odd (decimating by an even number): 2 x (cic_decim + 1)

Example CFIR filter lengths available based on mode and rxclk frequency:

(MHz) DECIMATION MAX LENGTH MIN LENGTH

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GC5018

8-CHANNEL WIDEBAND RECEIVER

SLWS169 – MAY 2005

A single set of programmed tap values are used for both the A-side and B-side DDC channels (two CDMA channels) within a single DDC block when in CDMA mode.

After the CFIR filter performs the convolution, gain is applied at full precision, the signal is rounded, and then hard limited. A shifter at the output of the filter then scales the data by either 2e-19 or 2e-18. The gain through the filter is therefore:

Sum(CFIR coefficients) x 2

Coefficients are organized in two groups of 32 words, each 18 bits wide. For fully utilized filters, the 64 coefficients are loaded 0 through 31 into the first RAM, and 32 through 63 into the second RAM. The 16 bit MSBs and 2 bit LSBs are written into the RAMs using different page register values. Shorter filters require the coefficients be loaded into the 2 rams equally, starting from address 0.

For example, a CFIR coefficient set for a symmetric 58 tap TD-SCDMA CFIR is:

Taps Coefficient Taps Coefficient

0 = 57 –13 15 = 42 –4975 1 = 56 –20 16 = 41 –4649 2 = 55 14 17 = 40 –232 3 = 54 101 18 = 39 6581 4 = 53 184 19 = 38 11266 5 = 52 133 20 = 37 8917 6 = 51 –147 21 = 36 –1957 7 = 50 –562 22 = 35 –16736 8 = 49 –768 23 = 34 –25469

9 = 48 –364 24 = 33 – 17599 10 = 47 719 25 = 32 11560 11 = 46 1905 26 = 31 56455 12 = 45 2126 27 = 30 102215 13 = 44 567 28 = 29 131071 14 = 43 –2416

–(18 or 19)

The first 29 coefficients are loaded into addresses 0 through 28 in the first coefficient RAM, and the remaining 29 are loaded into addresses 0 through 28 in the second coefficient RAM. Loading the 18 bit coefficients requires 2 writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.

To program this coefficient set for the DDC2 CFIR, the following control microprocessor interface sequence would be used.

Step Address Data Description

1 0x21 0x0480 Page register for DDC2 CFIR Coefficient RAM 0-31, LSBs. 2 0x00 0x0003 2 lower bits of coefficient 0 3 0x01 0x0000 2 lower bits of coefficient 1 4 0x02 0x0002 2 lower bits of coefficient 2 5 0x03 0x0001 2 lower bits of coefficient 3 6 0x04 0x0000 2 lower bits of coefficient 4 7 0x05 0x0001 2 lower bits of coefficient 5 8 0x06 0x0001 2 lower bits of coefficient 6

9 0x07 0x0002 2 lower bits of coefficient 7 10 0x08 0x0000 2 lower bits of coefficient 8 11 0x09 0x0000 2 lower bits of coefficient 9 12 0x0A 0x0003 2 lower bits of coefficient 10

a[5:0] d[15:0]

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Step Address Data Description

13 0x0B 0x0001 2 lower bits of coefficient 11 14 0x0C 0x0002 2 lower bits of coefficient 12 15 0x0D 0x0003 2 lower bits of coefficient 13 16 0x0E 0x0000 2 lower bits of coefficient 14 17 0x0F 0x0001 2 lower bits of coefficient 15 18 0x10 0x0003 2 lower bits of coefficient 16 19 0x11 0x0000 2 lower bits of coefficient 17 20 0x12 0x0001 2 lower bits of coefficient 18 21 0x13 0x0002 2 lower bits of coefficient 19 22 0x14 0x0001 2 lower bits of coefficient 20 23 0x15 0x0003 2 lower bits of coefficient 21 24 0x16 0x0000 2 lower bits of coefficient 22 25 0x17 0x0003 2 lower bits of coefficient 23 26 0x18 0x0001 2 lower bits of coefficient 24 27 0x19 0x0000 2 lower bits of coefficient 25 28 0x1A 0x0003 2 lower bits of coefficient 26 29 0x1B 0x0003 2 lower bits of coefficient 27 30 0x1C 0x0003 2 lower bits of coefficient 28 31 0x1D 0x0000 2 lower bits of unused coefficient RAM location 32 0x1E 0x0000 2 lower bits of unused coefficient RAM location 33 0x1F 0x0000 2 lower bits of unused coefficient RAM location 34 0x21 0x04A0 Page register for DDC2 CFIR Coefficient RAM 32-63, LSBs. 35 0x00 0x0003 2 lower bits of coefficient 29 36 0x01 0x0003 2 lower bits of coefficient 30 37 0x02 0x0003 2 lower bits of coefficient 31 38 0x03 0x0000 2 lower bits of coefficient 32 39 0x04 0x0001 2 lower bits of coefficient 33 40 0x05 0x0003 2 lower bits of coefficient 34 41 0x06 0x0000 2 lower bits of coefficient 35 42 0x07 0x0003 2 lower bits of coefficient 36 43 0x08 0x0001 2 lower bits of coefficient 37 44 0x09 0x0002 2 lower bits of coefficient 38 45 0x0A 0x0001 2 lower bits of coefficient 39 46 0x0B 0x0000 2 lower bits of coefficient 40 47 0x0C 0x0003 2 lower bits of coefficient 41 48 0x0D 0x0001 2 lower bits of coefficient 42 49 0x0E 0x0000 2 lower bits of coefficient 43 50 0x0F 0x0003 2 lower bits of coefficient 44 51 0x10 0x0002 2 lower bits of coefficient 45 52 0x11 0x0001 2 lower bits of coefficient 46 53 0x12 0x0003 2 lower bits of coefficient 47 54 0x13 0x0000 2 lower bits of coefficient 48 55 0x14 0x0000 2 lower bits of coefficient 49 56 0x15 0x0002 2 lower bits of coefficient 50 57 0x16 0x0001 2 lower bits of coefficient 51 58 0x17 0x0001 2 lower bits of coefficient 52 59 0x18 0x0000 2 lower bits of coefficient 53 60 0x19 0x0001 2 lower bits of coefficient 54

a[5:0] d[15:0]

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Step Address Data Description

61 0x1A 0x0002 2 lower bits of coefficient 55 62 0x1B 0x0000 2 lower bits of coefficient 56 63 0x1C 0x0003 2 lower bits of coefficient 57 64 0x1D 0x0000 2 lower bits of unused coefficient RAM location 65 0x1E 0x0000 2 lower bits of unused coefficient RAM location 66 0x1F 0x0000 2 lower bits of unused coefficient RAM location 67 0x21 0x04C0 Page register for DDC2 CFIR Coefficient RAM 0-31, MSBs. 68 0x00 0xFFFC Upper 16 bits of coefficient 0 69 0x01 0xFFFB Upper 16 bits of coefficient 1 70 0x02 0x0003 Upper 16 bits of coefficient 2 71 0x03 0x0019 Upper 16 bits of coefficient 3 72 0x04 0x002E Upper 16 bits of coefficient 4 73 0x05 0x0021 Upper 16 bits of coefficient 5 74 0x06 0xFFDB Upper 16 bits of coefficient 6 75 0x07 0xFF73 Upper 16 bits of coefficient 7 76 0x08 0xFF40 Upper 16 bits of coefficient 8 77 0x09 0xFFA5 Upper 16 bits of coefficient 9 78 0x0A 0x00B3 Upper 16 bits of coefficient 10 79 0x0B 0x01DC Upper 16 bits of coefficient 11 80 0x0C 0x0213 Upper 16 bits of coefficient 12 81 0x0D 0x008D Upper 16 bits of coefficient 13 82 0x0E 0xFDA4 Upper 16 bits of coefficient 14 83 0x0F 0xFB24 Upper 16 bits of coefficient 15 84 0x10 0xFB75 Upper 16 bits of coefficient 16 85 0x11 0xFFC6 Upper 16 bits of coefficient 17 86 0x12 0x066D Upper 16 bits of coefficient 18 87 0x13 0x0B00 Upper 16 bits of coefficient 19 88 0x14 0x08B5 Upper 16 bits of coefficient 20 89 0x15 0xFE16 Upper 16 bits of coefficient 21 90 0x16 0xEFA8 Upper 16 bits of coefficient 22 91 0x17 0xE720 Upper 16 bits of coefficient 23 92 0x18 0xEED0 Upper 16 bits of coefficient 24 93 0x19 0x0B4A Upper 16 bits of coefficient 25 94 0x1A 0x3721 Upper 16 bits of coefficient 26 95 0x1B 0x63D1 Upper 16 bits of coefficient 27 96 0x1C 0x7FFF Upper 16 bits of coefficient 28 97 0x1D 0x0000 Upper 16 bits of unused coefficient RAM location 98 0x1E 0x0000 Upper 16 bits of unused coefficient RAM location 99 0x1F 0x0000 Upper 16 bits of unused coefficient RAM location

100 0x21 0x04E0 Page register for DDC2 CFIR Coefficient RAM 32-63, MSBs. 101 0x00 0x7FFF Upper 16 bits of coefficient 29 102 0x01 0x63D1 Upper 16 bits of coefficient 30 103 0x02 0x3721 Upper 16 bits of coefficient 31 104 0x03 0x0B4A Upper 16 bits of coefficient 32 105 0x04 0xEED0 Upper 16 bits of coefficient 33 106 0x05 0xE720 Upper 16 bits of coefficient 34 107 0x06 0xEFA8 Upper 16 bits of coefficient 35 108 0x07 0xFE16 Upper 16 bits of coefficient 36

a[5:0] d[15:0]

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Step Address Data Description

109 0x08 0x08B5 Upper 16 bits of coefficient 37 110 0x09 0x0B00 Upper 16 bits of coefficient 38 111 0x0A 0x066D Upper 16 bits of coefficient 39 112 0x0B 0xFFC6 Upper 16 bits of coefficient 40 113 0x0C 0xFB75 Upper 16 bits of coefficient 41 114 0x0D 0xFB24 Upper 16 bits of coefficient 42 115 0x0E 0xFDA4 Upper 16 bits of coefficient 43 116 0x0F 0x008D Upper 16 bits of coefficient 44 117 0x10 0x0213 Upper 16 bits of coefficient 45 118 0x11 0x01DC Upper 16 bits of coefficient 46 119 0x12 0x00B3 Upper 16 bits of coefficient 47 120 0x13 0xFFA5 Upper 16 bits of coefficient 48 121 0x14 0xFF40 Upper 16 bits of coefficient 49 122 0x15 0xFF73 Upper 16 bits of coefficient 50 123 0x16 0xFFDB Upper 16 bits of coefficient 51 124 0x17 0x0021 Upper 16 bits of coefficient 52 125 0x18 0x002E Upper 16 bits of coefficient 53 126 0x19 0x0019 Upper 16 bits of coefficient 54 127 0x1A 0x0003 Upper 16 bits of coefficient 55 128 0x1B 0xFFFB Upper 16 bits of coefficient 56 129 0x1C 0xFFFC Upper 16 bits of coefficient 57 130 0x1D 0x0000 Upper 16 bits of unused coefficient RAM location 131 0x1E 0x0000 Upper 16 bits of unused coefficient RAM location 132 0x1F 0x0000 Upper 16 bits of unused coefficient RAM location 133 0x21 0x0500 Page register for DDC2 control registers 0-31 134 0x00 0x8EE0 DDC2 FIR_MODE register; cdma_mode enabled, 60 tap PFIR, 58 tap CFIR 135 0x01 0x2000 DDC2 PFIR gain = sum(taps)x2^–18 and CFIR gain = sum(taps)x2^–19

a[5:0] d[15:0]

VARIABLE DESCRIPTION

crastarttap_cfir(4:0) Number of DDC CFIR filter taps is 2x(crastarttap + 1) mpu_ram_read What set, the PFIR and CFIR coefficient rams are readable via the MPU control interface. The GC5018 signal

cfir_gain 0 = 2e The CFIR filter’s 18 bit coefficients are loaded in two 32 word memories. Note: CFIR filter coefficients are shared between A and B channels of a DDC block in CDMA mode.

3.2.8 DDC Programmable FIR Filter (PFIR)

path is not operational when this bit is set, it is intended for debug purposes only.

The receive programmable FIR filter (PFIR) provides final pulse shaping of the baseband signal data. It does not perform any decimation. Filter coefficient size, input, and output data size is 18 bits. A special strapped mode can be employed for UMTS where two adjacent DDCs (2k & 2k+1, k=0 to 7) can be combined to yield a filter with twice the number of coefficients. This means the GC5018 can support 4 UMTS DDC channels with double-length filter coefficients (up to 128 taps).

The filter is organized in four partial filter blocks, each containing a data RAM, a coefficient RAM and a dual multiplier, a common state machine and output accumulator.

28 RECEIVE DIGITAL SIGNAL PROCESSING

PROGRAMMING

–19

, 1 = 2e

–18

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reg

complex

output

samples

output

sample

valid

read pointer

write

pointer

read pointer

to adjacent DDC (if double_tap=“10”)

MPU control

interface

complex input

samples from cfir

(or adjacent DDC if

double_tap=”01”

COEF

RAM

16x18

DATA

RAM

32x36

complex

output

samples

crastarttap State Machine

output

sample

valid

write pointer

MUX

mpu

ram_read

read data

write data

to adjacent DDC (if double_tap=“10”)

from adjacent DDC

(if double_tap=”10”)

Filter cell 1

cell 2 cell 3 cell 4

8-CHANNEL WIDEBAND RECEIVER

GC5018

SLWS169 – MAY 2005

Mode rxclk CIC PFIR PFIR COMMENTS

UMTS 153.60 10 64 32 UMTS, 1 to 6 DDC channels UMTS 122.88 8 64 32 UMTS, 1 to 6 DDC channels UMTS 153.60 10 128 64 Strapped UMTS double length PFIR configuration; 1, 2 or 3 DDC

UMTS 122.88 8 128 64 Strapped UMTS double length PFIR configuration; 1, 2 or 3 DDC

The PFIR length is programmable. This permits turning off taps and saving power if short filters are appropriate. The filter’s output data can be shifted over a range of 0 to 7 bits where it is then rounded and hard limited to 18 bits. The shift range results in a gain that ranges from 2e

–19

–12

to 2e

. The gain of the PFIR block is: sum(coefficients) x 2-shift, where shift ranges from 12 to 19. The maximum PFIR filter length is a function of GC5018 clock rate and output sample rate and is limited

by the number of coefficient memory registers. The maximum number of taps is 64 and the minimum number is 32 (for both CDMA and UMTS). Lengths between these limits can be specified in increments of

4. For strapped UMTS with double length filters, the range of taps available is 64 to 128 in increments of

8. Subject to the above minimum and maximum values, the number of maximum taps available is:

UMTS Mode: 4 x (rxclk ÷ output sample rate) Strapped UMTS Mode: 8 x (rxclk ÷ output sample rate)

CDMA Mode: 2 x (rxclk ÷ output sample rate) PFIR coefficients and gain shift values are shared between both A and B CDMA channels in a DDC block. Example PFIR filter lengths available based on mode and rxclk frequency:

(MHz) DECI- MAX LENGTH MIN LENGTH

MATION

channels.

channels

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Mode rxclk CIC PFIR PFIR COMMENTS

CDMA 157.2864 32 64 32 CDMA2000 CDMA 122.88 25 64 32 CDMA2000 CDMA 78.6432 16 64 32 CDMA2000 low power configuration CDMA 153.60 30 64 32 TD-SCDMA CDMA 81.92 16 64 32 TD-SCDMA CDMA 76.80 15 60 32 TD-SCDMA low power configuration

(MHz) DECI- MAX LENGTH MIN LENGTH

MATION

Coefficients are organized in four groups of 16 words, each 18 bits wide. For fully utilized filters, the 64 coefficients are loaded 0 through 31 into the first and second RAMs, and 32 through 63 into the third and fourth RAMs. The 16 bit MSBs and 2 bit LSBs are written into the RAMs using different page register values. Shorter filters require the coefficients be loaded into the 4 rams equally, starting from address 0 and address 16.

For example, a CFIR coefficient set for a symmetric 60 tap TD-SCDMA PFIR is:

Taps Coefficient Taps Coefficient

0 = 59 –2 15 = 44 420 1 = 58 1 16 = 43 –331 2 = 57 4 17 = 42 –319 3 = 56 –8 18 = 41 744 4 = 55 –2 19 = 40 –440 5 = 54 21 20 = 39 –1005 6 = 53 –13 21 = 38 2389 7 = 52 –28 22 = 37 514 8 = 51 46 23 = 36 –6182

9 = 50 1 24 = 35 1845 10 = 49 –85 25 = 34 12959 11 = 48 96 26 = 33 –8691 12 = 47 82 27 = 32 –27246 13 = 46 –266 28 = 31 34166 14 = 45 38 29 = 30 131071

The first 15 coefficients are loaded into addresses 0 through 14 in the first coefficient RAM, the second group of 15 are loaded into addresses 16 through 30 corresponding to the second coefficient RAM, the third group of 15 are loaded into the third coefficient ram at addresses 0 through 14, and the fourth group of 15 are loaded into addresses 16 through 30 in the fourth coefficient RAM. Loading the 18 bit coefficients requires 2 writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.

To program this coefficient set for the DDC2 PFIR, the following control microprocessor interface sequence would be used.

Step Address Data Description

a[5:0] d[15:0]

1 0x21 0x0400 Page register for DDC2 CFIR Coefficient RAMs 0-15 and 16-31, LSBs. 2 0x00 0x0002 2 lower bits of coefficient 0 3 0x01 0x0001 2 lower bits of coefficient 1 4 0x02 0x0000 2 lower bits of coefficient 2 5 0x03 0x0000 2 lower bits of coefficient 3 6 0x04 0x0002 2 lower bits of coefficient 4

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