Texas Instruments FX011Z, TPS51225BRUK, TPS51225CRUK, TPS51225RUK Schematic [ru]

TPS51225, TPS51225B, TPS51225C

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SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

Dual Synchronous, Step-Down Controller with 5-V and 3.3-V LDOs

Check for Samples: TPS51225, TPS51225B, TPS51225C

1

FEATURES

2

• Input Voltage Range: 5.5 V to 24 V

• Output Voltages: 5 V and 3.3 V (Adjustable • Netbook, Tablet Computers
Range ±10%)

• Built-in, 100-mA, 5-V and 3.3-V LDOs

• Clock Output for Charge-Pump

• ±1% Reference Accuracy

• Adaptive On-time D-CAP™ Mode Control
Architecture with 300kHz/355kHz Frequency
Setting

• Auto-skip Light Load Operation (TPS51225/C)

• OOA Light Load Operation (TPS51225B)

• Internal 0.8-ms Voltage Servo Soft-Start

• Low-Side R
4500 ppm/°C Temperature Coefficient

• Built-in Output Discharge Function

• Separate Enable Input for Switchers
(TPS51225/B/C)

• Dedicated OC Setting Terminals

• Power Good Indicator

• OVP/UVP/OCP Protection

• Non-latch UVLO/OTP Protection

• 20-Pin, 3 mm × 3 mm, QFN (RUK)

ORDERABLE

DEVICE NUMBER

TPS51225RUKR Tape and Reel 3000
TPS51225RUKT Mini reel 250
TPS51225BRUKR Tape and Reel 3000
TPS51225BRUKT Mini reel 250
TPS51225CRUKR Tape and Reel 3000
TPS51225CRUKT Mini reel 250

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

Current Sensing Scheme with

DS(on)

ORDERING INFORMATION

ENABLE OUTPUT

FUNCTION SUPPLY

EN1/ EN2 Auto-skip VREG3

EN1/ EN2 OOA VREG3

EN1/ EN2 Auto-skip VREG3 & VREG5

SKIP MODE ALWAYS ON-LDO PACKAGE QUANTITY

APPLICATIONS

• Notebook Computers

DESCRIPTION

The TPS51225/B/C is a cost-effective, dual­synchronous buck controller targeted for notebook
system-power supply solutions. It provides 5-V and

3.3-V LDOs and requires few external components.
The 260-kHz VCLK output can be used to drive an
external charge pump, generating gate drive voltage
for the load switches without reducing the main
converter efficiency. The TPS51225/B/C supports
high efficiency, fast transient response and provides a
combined power-good signal. Adaptive on-time, D­CAP™ control provides convenient and efficient
operation. The device operates with supply input
voltage ranging from 5.5 V to 24 V and supports
output voltages of 5.0 V and 3.3 V. The
TPS51225/B/C is available in a 20-pin, 3 mm × 3
mm, QFN package and is specified from –40°C to
85°C.

(1)

PLASTIC Quad

Flat Pack

(20 pin QFN)

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2D-CAP, Out-of-Audio are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2012, Texas Instruments Incorporated

VIN

VBST1

TPS51225 C

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1EN 5 V

VCLK

VREG5

V

IN

5.5 V to 24 V

V

OUT

5 V

V

OUT

15 V

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

EN 3.3 V

V

OUT

3.3 V

PGOOD

3.3-V Always ON

UDG-12001

1 mF

1 mF

5 V
Always ON

VIN

VBST1

TPS51225

TPS51225 B

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1EN-5V

VCLK

VREG5

V

IN

5.5 V to 24 V

V

OUT

5 V

V

OUT

15 V

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

EN 3.3 V

V

OUT

3.3 V

PGOOD

3.3-V Always ON

UDG-11182

1 mF

5 V

1 mF

TPS51225, TPS51225B, TPS51225C

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

TYPICAL APPLICATION DIAGRAM (TPS51225/TPS51225B)

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TYPICAL APPLICATION DIAGRAM (TPS51225C)

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TPS51225, TPS51225B, TPS51225C

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ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VBST1, VBST2 –0.3 32
VBST1, VBST2
SW1, SW2 –6.0 26

Input voltage

(2)

VIN –0.3 26 V
EN1, EN2 –0.3 6
VFB1, VFB2 –0.3 3.6
VO1 –0.3 6
DRVH1, DRVH2 –6.0 32
DRVH1, DRVH2
DRVH1, DRVH2

Output voltage

(2)

DRVL1, DRVL2 –0.3 6 V
DRVL1, DRVL2 (pulse width < 20 ns) –2.5 6
PGOOD, VCLK, VREG5 –0.3 6
VREG3, CS1, CS2 –0.3 3.6

Electrostatic
discharge

Junction temperature, T
Storage temperature, T

HBM QSS 009-105 (JESD22-A114A) 2
CDM QSS 009-147 (JESD22-C101B.01) 1

J

ST

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted
(3) Voltage values are with respect to SW terminals.

(3)

(3)
(3)

(pulse width < 20 ns) –2.5 6

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

VALUE

MIN MAX

UNIT

–0.3 6

–0.3 6

kV

150 °C
–55 150 °C

THERMAL INFORMATION

TPS51225

(1)

θ

θ

θ

ψ

ψ

θ

JA
JCtop
JB

JT
JB

JCbot

THERMAL METRIC

Junction-to-ambient thermal resistance 94.1
Junction-to-case (top) thermal resistance 58.1
Junction-to-board thermal resistance 64.3
Junction-to-top characterization parameter 31.8
Junction-to-board characterization parameter 58.0
Junction-to-case (bottom) thermal resistance 5.9

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

TPS51225B
TPS51225C

20-PIN RUK

UNITS

°C/W

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Product Folder Links :TPS51225 TPS51225B TPS51225C

TPS51225, TPS51225B, TPS51225C

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

Supply voltage VIN 5.5 24

VBST1, VBST2 –0.1 30
VBST1, VBST2
SW1, SW2 –5.5 24 V

Input voltage

(1)

EN1, EN2 –0.1 5.5
VFB1, VFB2 –0.1 3.5
VO1 –0.1 5.5
DRVH1, DRVH2 –5.5 30
DRVH1, DRVH2

Output voltage

(1)

DRVL1, DRVL2 –0.1 5.5 V
PGOOD, VCLK, VREG5 –0.1 5.5
VREG3, CS1, CS2 –0.1 3.5

Operating free-air temperature, T

(1) All voltage values are with respect to the network ground terminal unless otherwise noted.
(2) Voltage values are with respect to the SW terminal.

(2)

(2)

A

–0.1 5.5

–0.1 5.5

–40 85 °C

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Product Folder Links :TPS51225 TPS51225B TPS51225C

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ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V
noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

SUPPLY CURRENT

I

VIN1

I

VIN2

I

VO1

I

VIN(STBY)

I

VIN(STBY)

INTERNAL REFERENCE

V

FBx

VREG5 OUTPUT

V

VREG5

I

VREG5

R

V5SW

VREG3 OUTPUT

V

VREG3

I

VREG3

DUTY CYCLE and FREQUENCY CONTROL

f

SW1

f

SW2

t

OFF(MIN)

MOSFET DRIVERS

R

DRVH

R

DRVL

t

D

INTERNAL BOOT STRAP SWITCH

R

VBST (ON)

I

VBSTLK

CLOCK OUTPUT

R

VCLK (PU)

R

VCLK (PD)

f

CLK

(1) Ensured by design. Not production tested.

VIN supply current-1 TA= 25°C, No load, V
VIN supply current-2 TA= 25°C, No load 30 μA
VO1 supply current TA= 25°C, No load, V

VIN stand-by current 95 μA

VIN stand-by current 180 μA

VFB regulation voltage

VREG5 output voltage V

VREG5 current limit V
5-V switch resistance V

VREG3 output voltage 5.5 V < V

VREG3 current limit V

CH1 frequency
CH2 frequency

(1)
(1)

Minimum off-time TA= 25°C 200 300 500 ns

DRVH resistance Ω

DRVL resistance Ω

Dead time ns

Boost switch on-resistance TA= 25°C, I
VBST leakage current TA= 25°C 1 µA

VCLK on-resistance (pull-up) TA= 25°C 10
VCLK on-resistance (pull-down) TA= 25°C 10
Clock frequency TA= 25°C 260 kHz

TPS51225, TPS51225B, TPS51225C

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

= 12 V, V

VIN

TA= 25°C, No load, V
V

= V

EN1

EN2

TA= 25°C, No load, V
(TPS51225C)

TA= 25°C 1.99 2.00 2.01 V

No load, V

> 7 V , V

VIN

V

> 5.5 V , V

VIN

= 7 V, V

VIN

= 5 V, I

VO1

No load, V
V

> 7 V , V

VIN

V

> 5.5 V, V

VIN

V

> 5.5 V, V

VIN

= 0 V, V

VO1

TA= 25°C, V
TA= 25°C, V

Source, (V
Sink, (V

DRVH

Source, (V
Sink, V

DRVL

DRVH-off to DRVL-on 12
DRVL-off to DRVH-on 20

= 0 V

= 5 V, V

VO1

VO1

VFB1
VO1

VO1

= V

VFB1

VFB2

= 2 V, V

EN1

= V

= 3.3 V (unless otherwise

EN2

=0 V 860 μA

= V

=2.05 V 900 μA

VFB2

= 0 V,

TPS51225

TPS51225B

=0 V, V

EN1=VEN2

=0V

1.98 2.00 2.02 V

= 0 V, TA= 25°C 4.9 5.0 5.1

VO1

= 0 V, I

VO1

= 0 V, I

VO1

= 0 V, V

VO1

= 50 mA, TA= 25°C 1.8 Ω

VREG5

= 0 V, TA= 25°C 3.267 3.300 3.333

VO1

= 0 V, I

VO1

, V

= 0 V, I

VIN

VO1

= 0 V, I

VO1

= 5 V, I

VO1

= 3.0 V, V

VREG3

= 20 V 240 300 360 kHz

VIN

= 20 V 280 355 430 kHz

VIN

– V

VBST

DRVH

– VSW) = 0.25 V, (V

– V

VREG5

= 0.25 V, V

= 10 mA 13 Ω

VBST

< 100 mA 4.85 5.00 5.10 V

VREG5

< 35 mA 4.85 5.00 5.10

VREG5

= 4.5 V 100 150 mA

VREG5

< 100 mA 3.217 3.300 3.383

VREG3

< 35 mA 3.234 3.300 3.366 V

VREG3

< 35 mA, 0°C ≤ TA≤ 85°C 3.267 3.300 3.333

VREG3

< 35 mA, 0°C ≤ TA≤ 85°C 3.267 3.300 3.333

VREG3

= 7 V 100 150 mA

VIN

) = 0.25 V, (V

) = 0.25 V, V

DRVL

= 5 V 0.9

VREG5

– VSW) = 5 V 3.0

VBST

– VSW) = 5 V 1.9

VBST

= 5 V 3.0

VREG5

Ω

Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links :TPS51225 TPS51225B TPS51225C

TPS51225, TPS51225B, TPS51225C

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, V
noted)

PARAMETER TEST CONDITION MIN TYP MAX UNIT

OUTPUT DISCHARGE

R

DIS1

R

DIS2

R

DIS2

SOFT START OPERATION

t

SS

t

SSRAMP

POWER GOOD

V

PGTH

I

PGMAX

I

PGLK

t

PGDEL

CURRENT SENSING

I

CS

TC

CS

V

CS

V

ZC

LOGIC THRESHOLD

V

ENX(ON)

V

ENX(OFF)

I

EN

OUTPUT OVERVOLTAGE PROTECTION

V

OVP

t

OVPDLY

OUTPUT UNDERVOLTAGE PROTECTION

V

UVP

t

UVPDLY

t

UVPENDLY

UVLO

V

UVL0VIN

V

UVLO5

V

UVLO3

OVER TEMPERATURE PROTECTION

T

OTP

CH1 discharge resistance 35 Ω

CH2 discharge resistance 75 Ω
CH2 discharge resistance TA= 25°C, V

Soft-start time From ENx="Hi" and V
Soft-start time (ramp-up) V

PG threshold

PG sink current V
PG leak current V
PG delay From PG lower threshold (95%=typ) to PG flag high 0.7 ms

CS source current TA= 25°C, VCS= 0.4 V 9 10 11 μA
CS current temperature coefficient
CS Current limit setting range 0.2 2 V
Zero cross detection offset TA= 25°C –1 1 3 mV

EN threshold high-level SMPS on level 1.6 V
EN threshold low-level SMPS off level 0.3 V
EN input current V

OVP trip threshold 112.5% 115.0% 117.5%
OVP propagation delay TA= 25°C 0.5 µs

UVP trip Threshold 55% 60% 65%
UVP prop delay 250 µs
UVP enable delay From ENx ="Hi", V

VIN UVLO Threshold

VREG5 UVLO Threshold

VREG3 UVLO Threshold

OTP threshold

(1)

= 12 V, V

VIN

TA= 25°C, V
V

TA= 25°C, V
V

Lower (rising edge of PG-in) 92.5% 95.0% 97.5%
Hysteresis 5%
Upper (rising edge of PG-out) 107.5% 110.0% 112.5%
Hysteresis 5%

(1)

On the basis of 25°C 4500 ppm/°C

Wake up 4.58 V
Hysteresis 0.5 V
Wake up 4.38 V
Hysteresis 0.4 V
Wake up 3.15 V
Hysteresis 0.15 V

Shutdown temperature 155
Hysteresis 10

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= 5 V, V

VO1

= 0.5 V

VO1

= V

EN1

EN1

OUT

PGOOD
PGOOD

ENx

= 0 V

EN2

= 0.5 V

SW2

= V

= 0 V

EN2

= 0.5 V, V

SW2

VREG5

= 0% to V

OUT

= 95%, V

= 0.5 V 6.5 mA
= 5.5 V 1 µA

= 3.3 V –1 1 µA

VREG5

= V

VFB1

EN1

> V

VREG5

= V

UVLO5

= 2 V, V

VFB2

= 0 V (TPS51225C) 70 Ω

EN2

to V

= 95% 0.91 ms

OUT

= 5 V 0.78 ms

EN1

= V

= 3.3 V (unless otherwise

EN2

= 5 V 1.35 ms

°C

(1) Ensured by design. Not production tested.

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Product Folder Links :TPS51225 TPS51225B TPS51225C

1

2

3

4

5

6

7

8 9

10

11

12

13

14

15

16

17

1819

20

TPS51225

Thermal Pad

TPS51225B
TPS51225C

CS1

VFB1

VREG3

VFB2

CS2

EN2

PGOOD

SW2

VBST2

DRVH2

DRVL2

VIN

VREG5

VO1

DRVL1

DRVH1

VBST1

SW1

VCLK

EN1

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TPS51225, TPS51225B, TPS51225C

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

DEVICE INFORMATION

RUK PACKAGE

20 PINS

(TOP VIEW)

PIN FUNCTIONS

PIN NO.

TPS51225
TPS51225B
TPS51225C

Supply input for high-side MOSFET (bootstrap terminal). Connect capacitor from this pin to SW
terminal.

Voltage feedback Input

Power conversion voltage input. Apply the same voltage as drain voltage of high-side MOSFETs of

— — GND terminal, solder to the ground plane

channel 1 and channel 2.

Product Folder Links :TPS51225 TPS51225B TPS51225C

NAME I/O DESCRIPTION

CS1 1 O Sets the channel 1 OCL trip level.
CS2 5 O Sets the channel 2OCL trip level.
DRVH1 16 O High-side driver output
DRVH2 10 O High-side driver output
DRVL1 15 O Low-side driver output
DRVL2 11 O Low-side driver output
EN1 20 I Channel 1 enable.
EN2 6 I Channel 2 enable.
PGOOD 7 O Power good output flag. Open drain output. Pull up to external rail via a resistor
SW1 18 O Switch-node connection.
SW2 8 O Switch-node connection.
VBST1 17 I
VBST2 9 I
VCLK 19 O Clock output for charge pump.
VFB1 2 I
VFB2 4 I

VIN 12 I
VO1 14 I Output voltage input, 5-V input for switch-over.

VREG3 3 O 3.3-V LDO output.
VREG5 13 O 5-V LDO output.
Thermal

pad

Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7

VIN

VBST1

TPS51225
TPS51225 B
TPS51225 C

DRVH1

SW1

DRVL1

VO1

VFB1

CS1

EN1

VCLK

VREG5

VBST2

DRVH2

SW2

DRVL2

VFB2

CS2

EN2

PGOOD

VREG3

UDG-12002

+ +

+

+

+

155°C/145°C

+

4.5 V/4.0 V

VO_OK

EN

FAULT

REF

PGOOD

DCHG

VIN VDDVDRV

GNDPGND

Switcher

Controller

(CH1)

EN

FAULT

REF

PGOOD

DCHG

VINVDD VDRV

GND PGND

Switcher

Controller

(CH2)

+

2 V

Osc

GND

(Thermal Pad)

TPS51225, TPS51225B, TPS51225C

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

FUNCTIONAL BLOCK DIAGRAM (TPS51225/B/C)

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Product Folder Links :TPS51225 TPS51225B TPS51225C

DCHG

SW

TPS51225
TPS51225B
TPS51225C

NOC

ZC

XCON

VO_OK

DRVL

PWM

Control Logic

UDG-12007

+

+

V

REF

+15%

+

+

SKIP

UV

OV

V

REF

–40%

+

VIN

GND

REF

One-Shot

Discharge

10 µA

VBST

DRVH

FAULT

PGOOD

CS

+

VFB

OC

+

+

SS Ramp Comp

V

REF

+5%/10%

V

REF

–5%/10%

+

+

EN

VDD

HS

LS

VDRV

PGND

PGOOD

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SWITCHER CONTROLLER BLOCK DIAGRAM

TPS51225, TPS51225B, TPS51225C

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

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Product Folder Links :TPS51225 TPS51225B TPS51225C

( )

( )

- ´

= ´

´ ´

IN OUT OUT

OUT LL

SW IN

V V V

1

I

2 L f V

TPS51225, TPS51225B, TPS51225C

SLUSAV0B –JANUARY 2012–REVISED SEPTEMBER 2012

DETAILED DESCRIPTION

PWM Operations

The main control loop of the switch mode power supply (SMPS) is designed as an adaptive on-time pulse width
modulation (PWM) controller. It supports a proprietary D-CAP™ mode. D-CAP™ mode does not require external
conpensation circuit and is suitable for low external component count configuration when used with appropriate
amount of ESR at the output capacitor(s).

At the beginning of each cycle, the synchronous high-side MOSFET is turned on, or enters the ON state. This
MOSFET is turned off, or enters the ‘OFF state, after the internal, one-shot timer expires. The MOSFET is turned
on again when the feedback point voltage, V

, decreased to match the internal 2-V reference. The inductor

VFB

current information is also monitored and should be below the overcurrent threshold to initiate this new cycle. By
repeating the operation in this manner, the controller regulates the output voltage. The synchronous low-side
(rectifying) MOSFET is turned on at the beginning of each OFF state to maintain a minimum of conduction loss.
The low-side MOSFET is turned off before the high-side MOSFET turns on at next switching cycle or when
inductor current information detects zero level. This enables seamless transition to the reduced frequency
operation during light-load conditions so that high efficiency is maintained over a broad range of load current.

Adaptive On-Time/ PWM Frequency Control

Bacause the TPS51225/B/C does not have a dedicated oscillator for control loop on board, switching cycle is
controlled by the adaptive on-time circuit. The on-time is controlled to meet the target switching frequency by
feed-forwarding the input and output voltage into the on-time one-shot timer. The target switching frequency is
varied according to the input voltage to achieve higher duty operation for lower input voltage application. The
switching frequency of CH1 (5-V output) is 300 kHz during continuous conduction mode (CCM) operation when
VIN= 20 V. The CH2 (3.3-V output) is 355 kHz during CCM when VIN= 20 V.

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Light Load Condition in Auto-Skip Operation (TPS51225/C)

The TPS51225/C automatically reduces switching frequency during light-load conditions to maintain high
efficiency. This reduction of frequency is achieved smoothly and without an increase in output voltage ripple. A
more detailed description of this operation is as follows. As the output current decreases from heavy-load
condition, the inductor current is also reduced and eventually approaches valley zero current, which is the
boundary between continuous conduction mode and discontinuous conduction mode. The rectifying MOSFET is
turned off when this zero inductor current is detected. As the load current further decreases, the converter runs in
discontinuous conduction mode and it takes longer and longer to discharge the output capacitor to the level that
requires the next ON cycle. The ON time is maintained the same as that in the heavy-load condition. In reverse,
when the output current increase from light load to heavy load, the switching frequency increases to the preset
value as the inductor current reaches to the continuous conduction. The transition load point to the light load
operation I

OUT(LL)

as shown in Equation 1.

where

• fSWis the PWM switching frequency (1)

Switching frequency versus output current during light-load conditions is a function of inductance (L), input
voltage (VIN) and output voltage (V
I

.

OUT(LL)

(i.e. the threshold between continuous and discontinuous conduction mode) can be calculated

), but it decreases almost proportional to the output current from the

OUT

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Product Folder Links :TPS51225 TPS51225B TPS51225C