Texas Instruments TPS51216RUKR, FX004Z Schematics

12
17
16
6
15
14
13
11
V5IN
TPS51216
S3
S5
VREF
DRVH
SW
DRVL
8
10
REFIN
PGND
7
19
GND
MODE
18 TRIP
20
9
2
3
PGOOD
VDDQSNS
VLDOIN
VTT
1
4
5
VTTSNS
VTTGND
VTTREF
UDG-10138
VDDQ
VTT
PGND
S3
S5
PGND
5VIN
PGND
VIN
VTTREF
AGND
AGND
Powergood
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Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous Buck
Controller, 2-A LDO, Buffered Reference
Check for Samples: TPS51216
1

FEATURES

2
Synchronous Buck Controller (VDDQ) – Conversion Voltage Range: 3 V to 28 V – Output Voltage Range: 0.7 V to 1.8 V – 0.8% V – D-CAP™ Mode for Fast Transient Response – Selectable 300 kHz/400 kHz Switching
Frequencies
– Optimized Efficiency at Light and Heavy
Loads with Auto-skip Function – Supports Soft-Off in S4/S5 States – OCL/OVP/UVP/UVLO Protections – Powergood Output
2-A LDO(VTT), Buffered Reference(VTTREF) – 2-A (Peak) Sink and Source Current – Requires Only 10-μF of Ceramic Output
Capacitance
– Buffered, Low Noise, 10-mA VTTREF
Output – 0.8% VTTREF, 20-mV VTT Accuracy – Support High-Z in S3 and Soft-Off in S4/S5
Thermal Shutdown
20-Pin, 3 mm × 3 mm, QFN Package
Accuracy
REF
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

DESCRIPTION

The TPS51216 provides a complete power supply for DDR2, DDR3 and DDR3L memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered low noise reference (VTTREF). The TPS51216 employs D-CAP™ mode coupled with 300 kHz/400 kHz frequencies for ease-of-use and fast transient response. The VTTREF tracks VDDQ/2 within excellent 0.8% accuracy. The VTT, which provides 2­A sink/source peak current capabilities, requires only 10-μF of ceramic capacitance. In addition, a dedicated LDO supply input is available.
The TPS51216 provides rich useful functions as well as excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft­off) in S4/S5 state. Programmable OCL with low-side MOSFET R
DS(on)
thermal shutdown protections are also available. The TPS51216 is available in a 20-pin, 3 mm × 3
mm, QFN package and is specified for ambient temperature from –40°C to 85°C.
sensing, OVP/UVP/UVLO and

APPLICATIONS

DDR2/DDR3/DDR3L Memory Power Supplies
SSTL_18, SSTL_15, SSTL_135 and HSTL Termination
1
2D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2010–2013, Texas Instruments Incorporated
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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ORDERING INFORMATION
T
A
PACKAGE PINS
–40°C to 85°C Plastic Quad Flat Pack (20 pin QFN) 20
ORDERABLE DEVICE OUTPUT MINIMUM
NUMBER SUPPLY QUANTITY
TPS51216RUKR Tape and reel 3000 TPS51216RUKT Mini reel 250
(1)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
MIN MAX
VBST –0.3 36
(3)
VBST SW –5 30
Input voltage range
(2)
VLDOIN, VDDQSNS, REFIN –0.3 3.6 V VTTSNS –0.3 3.6 PGND, VTTGND –0.3 0.3 V5IN, S3, S5, TRIP, MODE –0.3 6 DRVH –5 36
(3)
DRVH
(3)
Output voltage range
DRVH VTTREF, VREF –0.3 3.6
(2)
VTT –0.3 3.6
(duty cycle < 1%) –2.5 6
DRVL –0.3 6 DRVL (duty cycle < 1%) –2.5 6
PGOOD –0.3 6 Junction temperature range, T Storage temperature range, T
J
STG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal unless otherwise noted. (3) Voltage values are with respect to the SW terminal.
–0.3 6
–0.3 6
V
125 °C
–55 150 °C

THERMAL INFORMATION

THERMAL METRIC UNITS
θ
θ
θ
ψ
ψ
θ
JA JCtop JB
JT JB
JCbot
Junction-to-ambient thermal resistance 94.1 Junction-to-case (top) thermal resistance 58.1 Junction-to-board thermal resistance 64.3 Junction-to-top characterization parameter 31.8 Junction-to-board characterization parameter 58.0 Junction-to-case (bottom) thermal resistance 5.9
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TPS51216
QFN (20) PINS
°C/W
TPS51216
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RECOMMENDED OPERATING CONDITIONS

Supply voltage V5IN 4.5 5.5 V
VBST –0.1 33.5
(1)
VBST SW -3 28
(2)
Input voltage range V
Output voltage range VTTREF, VREF –0.1 3.5 V
T
A
(1) Voltage values are with respect to the SW terminal. (2) This voltage should be applied for less than 30% of the repetitive period.
SW VLDOIN, VDDQSNS, REFIN –0.1 3.5 VTTSNS –0.1 3.5 PGND, VTTGND –0.1 0.1 S3, S5, TRIP, MODE –0.1 5.5 DRVH –3 33.5
(1)
DRVH
(2)
DRVH
VTT –0.1 3.5 DRVL –0.1 5.5 PGOOD –0.1 5.5 Operating free-air temperature –40 85 °C
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
MIN TYP MAX UNIT
–0.1 5.5
–4.5 28
–0.1 5.5 –4.5 33.5
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, V otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
I
V5IN(S0)
I
V5IN(S3)
I
V5INSDN
I
VLDOIN(S0)
I
VLDOIN(S3)
I
VLDOINSDN
VREF OUTPUT
V
VREF
I
VREFOCL
VTTREF OUTPUT
V
VTTREF
V
VTTREF
I
VTTREFOCLSRC
I
VTTREFOCLSNK
I
VTTREFDIS
VTT OUTPUT
V
VTT
V
VTTTOL
I
VTTOCLSRC
I
VTTOCLSNK
I
VTTLK
I
VTTSNSBIAS
I
VTTSNSLK
I
VTTDIS
VDDQ OUTPUT
V
VDDQSNS
V
VDDQSNSTOL
I
VDDQSNS
I
REFIN
I
VDDQDIS
I
VLDOINDIS
SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY
f
SW
t
ON(min)
t
OFF(min)
(1) Ensured by design. Not production tested.
V5IN supply current, in S0 TA= 25°C, No load, VS3= VS5= 5 V 590 μA V5IN supply current, in S3 TA= 25°C, No load, VS3= 0 V, VS5= 5 V 500 μA V5IN shutdown current TA= 25°C, No load, VS3= VS5= 0 V 1 μA VLDOIN supply current, in S0 TA= 25°C, No load, VS3= VS5= 5 V 5 μA VLDOIN supply current, in S3 TA= 25°C, No load, VS3= 0 V, VS5= 5 V 5 μA VLDOIN shutdown current TA= 25°C, No load, VS3= VS5= 0 V 5 μA
I
= 30 μA, TA= 25°C 1.8000
VREF
Output voltage 0 μA I
0 μA I
Current limit V
VREF
<300 μA, TA= –10°C to 85°C 1.7856 1.8144 V
VREF
<300 μA, TA= –40°C to 85°C 1.7820 1.8180
VREF
= 1.7 V 0.4 0.8 mA
Output voltage V
|I
| <100 μA, 1.2 V V
Output voltage tolerance to V
VDDQ
Source current limit V Sink current limit V
VTTREF
|I
| <10 mA, 1.2 V V
VTTREF VDDQSNS VDDQSNS
= 1.8 V, V = 1.8 V, V
= 0 V 10 18 mA
VTTREF VTTREF
VTTREF discharge current TA= 25°C, VS3= VS5= 0 V, V
1.8 V 49.2% 50.8%
VDDQSNS
1.8 V 49% 51%
VDDQSNS
= 1.8 V 10 17 mA
= 0.5 V 0.8 1.3 mA
VTTREF
Output voltage V
|I
| 10 mA, 1.2 V V
VTT
|I
| 1 A, 1.2 V
Output voltage tolerance to VTTREF mV
Source current limit 2 3 Sink current limit V
VTT
|I
| 2 A, 1.4 V V
VTT
|I
| 1.5 A, 1.2 V V
VTT
V
VDDQSNS
I
= 0 A
VTTREF
VDDQSNS
= 1.8 V, V
= 1.8V, V
VDDQSNS
VDDQSNS
VDDQSNS
VTT
= V
VTT
Leakage current TA= 25°C , VS3= 0 V, VS5= 5 V, V VTTSNS input bias current VS3= 5 V, VS5= 5 V, V VTTSNS leakage current VS3= 0 V, VS5= 5 V, V
VTT Discharge current 7.8 mA
TA= 25°C, VS3= VS5= 0 V, V V
= 0.5 V, I
VTT
VTTREF
VTTSNS VTTSNS
= 0 A
VDDQSNS
1.8 V, I
= V
VTTSNS
VTTSNS
1.8 V, I
1.8 V, I
1.4 V, I
= 0.7 V,
= 1.1 V, I
VTT
= V
VTTREF
= V
VTTREF
VDDQSNS
= 0 A –20 20
VTTREF
= 0 A –30 30
VTTREF
= 0 A –40 40
VTTREF
= 0 A –40 40
VTTREF
= 0 A 2 3
VTTREF
= V
VTTREF
–0.5 0.0 0.5 μA
= 1.8 V,
VDDQ sense voltage V VDDQSNS regulation voltage
tolerance to REFIN VDDQSNS input current V REFIN input current V
VDDQ discharge current 12 mA
VLDOIN discharge current 1.2 A
VDDQ switching frequency kHz
Minimum on time DRVH rising to falling
TA= 25°C –3 3 mV
= 1.8 V 39 μA
VDDQSNS
= 1.8 V –0.1 0.0 0.1 μA
REFIN
VS3= VS5= 0 V, V down to GND through 47kΩ (Non-tracking)
VS3= VS5= 0 V, V down to GND through 100kΩ (Non-tracking)
VIN= 12 V, V VIN= 12 V, V
VDDQSNS VDDQSNS
= 0.5 V, MODE pin pulled
VDDQSNS
= 0.5 V, MODE pin pulled
VDDQSNS
= 1.8 V, R = 1.8 V, R
(1)
MODE MODE
= 100 kΩ 300 = 200 kΩ 400
Minimum off time DRVH falling to rising 200 320 450
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=0V, VS3=VS5=5V (unless
MODE
/2 V
VDDQSNS
VTTREF
–1 0 1
REFIN
60
V
A
5
ns
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SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, V otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VDDQ MOSFET DRIVER
R
R
t
DEAD
DRVH
DRVL
DRVH resistance
DRVL resistance
Dead time ns
INTERNAL BOOT STRAP SW
V
FBST
I
VBSTLK
Forward Voltage V VBST leakage current TA= 25°C, V
LOGIC THRESHOLD
I
MODE
V
THMODE
V
IL
V
IH
V
IHYST
V
ILK
MODE source current 14 15 16 μA
MODE threshold voltage mV
S3/S5 low-level voltage 0.5 S3/S5 high-level voltage 1.8 V S3/S5 hysteresis voltage 0.25 S3/S5 input leak current –1 0 1 μA
SOFT START
t
SS
VDDQ soft-start time 1.1 ms
PGOOD COMPARATOR
V
THPG
I
PG
t
PGDLY
t
PGSSDLY
VDDQ PGOOD threshold
PGOOD sink current V
PGOOD delay time
PGOOD start-up delay C
Source, I Sink, I Source, I Sink, I DRVH-off to DRVL-on 10 DRVL-off to DRVH-on 20
V5IN-VBST
MODE 0 580 600 620 MODE 1 829 854 879 MODE 2 1202 1232 1262 MODE 3 1760 1800 1840
Internal soft-start time, C S5 rising to V
PGOOD in from higher 106% 108% 110% PGOOD in from lower 90% 92% 94% PGOOD out to higher 114% 116% 118% PGOOD out to lower 82% 84% 86%
PGOOD
Delay for PGOOD in 0.8 1 1.2 ms Delay for PGOOD out, with 100 mV over drive 330 ns
VREF
= –50 mA 1.6 3.0
DRVH
= 50 mA 0.6 1.5
DRVH
= –50 mA 0.9 2.0
DRVL
= 50 mA 0.5 1.2
DRVL
, TA= 25°C, IF= 10 mA 0.1 0.2 V
= 33 V, VSW= 28 V 0.01 1.5 μA
VBST
= 0.1 μF,
VREF
> 0.99 × V
VDDQSNS
REFIN
= 0.5 V 3 5.9 mA
= 0.1 μF, S5 rising to PGOOD rising 2.5 ms
TPS51216
=0V, VS3=VS5=5V (unless
MODE
Ω
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, V otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
PROTECTIONS
I
TRIP
TC
ITRIP
V
TRIP
V
OCL
V
OCLN
V
ZC
V
UVLO
V
OVP
t
OVPDLY
V
UVP
t
UVPDLY
t
UVPENDLY
V
OOB
THERMAL SHUTDOWN
T
SDN
TRIP source current TA= 25°C, V TRIP source current temperature
coefficient V
Current limit threshold V
Negative current limit threshold V
(2)
voltage range 0.2 3 V
TRIP
V
= 3.0 V 360 375 390
TRIP
= 1.6 V 190 200 210 mV
TRIP
V
= 0.2 V 20 25 30
TRIP
V
= 3.0 V –390 –375 –360
TRIP
= 1.6 V –210 –200 –190 mV
TRIP
V
= 0.2 V –30 –25 –20
TRIP
= 0.4 V 9 10 11 μA
TRIP
Zero cross detection offset 0 mV
V5IN UVLO threshold voltage V
Wake-up 4.2 4.4 4.5
Shutdown 3.7 3.9 4.1 VDDQ OVP threshold voltage OVP detect voltage 118% 120% 122% VDDQ OVP propagation delay With 100 mV over drive 430 ns VDDQ UVP threshold voltage UVP detect voltage 66% 68% 70% VDDQ UVP delay 1 ms VDDQ UVP enable delay 1.2 ms OOB Threshold voltage 108%
Thermal shutdown threshold °C
Shutdown temperature
Hysteresis
(2)
(2)
=0V, VS3=VS5=5V (unless
MODE
4700 ppm/°C
140
10
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(2) Ensured by design. Not production tested.
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1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
17
1819
20
TPS51216
PowerPAD™
VTTSNS
VLDOIN
VTT
VTTGND
VTTREF
VREF
GND
REFIN
VDDQSNS
PGND
DRVL
V5IN
SW
DRVH
VBST
S5
S3
TRIP
MODE
PGOOD
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

DEVICE INFORMATION

RUK PACKAGE (TOP VIEW)
PIN FUNCTIONS
PIN
NAME NO.
DRVH 14 O High-side MOSFET gate driver output. DRVL 11 O Low-side MOSFET gate driver output. GND 7 Signal ground. MODE 19 I Connect resistor to GND to configure switching frequency and discharge mode. (See Table 2) PGND 10 Gate driver power ground. R PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
REFIN 8 I SW 13 I/O High-side MOSFET gate driver return. R
S3 17 I S3 signal input. (See Table 1) S5 16 I S5 signal input. (See Table 1) TRIP 18 I Connect resistor to GND to set OCL at V VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin. VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF. VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application. VREF 6 O 1.8-V reference output. VTT 3 O VTT 2-A LDO output. Need to connect 10μF or larger capacitance for stability. VTTGND 4 Power ground for VTT LDO. VTTREF 5 O Buffered VTT reference output. Need to connect 0.22μF or larger capacitance for stability. VTTSNS 1 I VTT output voltage feedback. V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers. Thermal
pad
I/O DESCRIPTION
current sensing input(+).
DS(on)
Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation.
current sensing input(–).
DS(on)
/8. Output 10-μA current at room temperature, TC= 4700 ppm/°C.
TRIP
Connect to GND
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1013PGND
SW
TPS51216
OC
ZC
XCON
15
VBST
12 V5IN
PWM
9
REFIN
TRIP
Delay
20 PGOOD
Control Logic
UDG-10135
10 mA
+
+
V
REFIN
+20%
+
+
8
VDDQSNS
+ +
18
14 DRVH
11 DRVL
t
ON
One­Shot
UV
OV
V
REFIN
–32%
16S5
Soft-Start
+
NOC
+
8 R
6VREF Reference
R
7GND
17S3
5VTTREF
1VTTSNS
4 VTTGND
3 VTT
+
+
+
+
2 VLDOIN
7 R
R
VTT Discharge
VTTREF Discharge
On-Time
Discharge Type
Selection
15 mA
19 MODE
V
REFIN
+8/16 %
V
REFIN
–8/16 %
+
+
VDDQ Discharge
V5OK
+
4.4 V/3.9 V
UVP
OVP
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

FUNCTIONAL BLOCK DIAGRAM

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50
60
70
80
90
100
110
120
130
140
150
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
OVP/UVP Threshold (%)
OVP UVP
0
3
6
9
12
15
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
VDDQSNS Discharge Current (mA)
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
VLDOIN Suppy Current (µA)
4
6
8
10
12
14
16
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
TRIP Source Current (µA)
0
200
400
600
800
1000
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
V5IN Suppy Current (µA)
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
V5IN Shutdown Current (µA)
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Figure 1. V5IN Supply Current vs Junction Temperature Figure 2. V5IN Shutdown Current vs Junction Temperature
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

TYPICAL CHARACTERISTICS

Figure 3. VLDOIN Supply Current vs Junction Temperature Figure 4. Current Sense Current vs Junction Temperature
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Figure 5. OVP/UVP Threshold vs Junction Temperature Figure 6. VDDQSNS Discharge Current vs Junction
Temperature
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0
100
200
300
400
500
600
700
800
0 2 4 6 8 10 12 14 16 18 20
VDDQ Output Current (A)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 200 k
VIN = 12 V
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
0 2 4 6 8 10 12 14 16 18 20
VDDQ Output Current (A)
VDDQ Output Voltage (V)
R
MODE
= 200 k
VIN = 12 V
200
300
400
500
600
700
800
6 8 10 12 14 16 18 20 22
Input Voltage (V)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 200 k
I
VDDQ
= 10 A
0
100
200
300
400
500
600
700
800
0 2 4 6 8 10 12 14 16 18 20
VDDQ Output Current (A)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 100 k
VIN = 12 V
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
VTT Discharge Current (mA)
200
300
400
500
600
700
800
6 8 10 12 14 16 18 20 22
Input Voltage (V)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 100 k
I
VDDQ
= 10 A
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
Figure 7. VTT Discharge Current vs Junction Temperature Figure 8. Switching Frequency vs Input Voltage
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Figure 9. Switching Frequency vs Input Voltage Figure 10. Switching Frequency vs Load Current
Figure 11. Switching Frequency vs Load Current Figure 12. Load Regulation
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0.710
0.720
0.730
0.740
0.750
0.760
0.770
0.780
0.790
−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 VTT Current (V)
VTT Voltage (V)
V
VDDQ
= 1.5 V
0.635
0.645
0.655
0.665
0.675
0.685
0.695
0.705
0.715
−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 VTT Current (V)
VTT Voltage (V)
V
VDDQ
= 1.35 V
0.650
0.655
0.660
0.665
0.670
0.675
0.680
0.685
0.690
0.695
−10 −5 0 5 10 VTTREF Current (mA)
VTTREF Voltage (V)
V
VDDQ
= 1.35 V
0.580
0.585
0.590
0.595
0.600
0.605
0.610
0.615
0.620
−10 −5 0 5 10 VTTREF Current (mA)
VTTREF Voltage (V)
V
VDDQ
= 1.2 V
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
6 8 10 12 14 16 18 20 22
Input Voltage (V)
VDDQ Output Voltage (V)
I
VDDQ
= 0 A
I
VDDQ
= 20 A
R
MODE
= 200 k
0.730
0.735
0.740
0.745
0.750
0.755
0.760
0.765
0.770
−10 −5 0 5 10 VTTREF Current (mA)
VTTREF Voltage (V)
V
VDDQ
= 1.5 V
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
Figure 13. Line Regulation Figure 14. VTTREF Load Regulation
Figure 15. VTTREF Load Regulation Figure 16. VTTREF Load Regulation
Figure 17. VTT Load Regulation Figure 18. VTT Load Regulation
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
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0.560
0.570
0.580
0.590
0.600
0.610
0.620
0.630
0.640
−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 VTT Current (V)
VTT Voltage (V)
V
VDDQ
= 1.2 V
0
10
20
30
40
50
60
70
80
90
100
0.001 0.01 0.1 1 10 100 VDDQ Output Current (A)
Efficiency (%)
VIN = 20 V VIN = 12 V VIN = 8 V
V
VDDQ
= 1.5 V
R
MODE
= 200 k
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
Figure 19. VTT Load Regulation Figure 20. Efficiency
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Figure 21. 1.5-V Load Transient Response Figure 22. VTT Load Transient Response
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
Figure 23. 1.5-V Startup Waveforms Figure 24. 1.5-V Startup Waveforms (0.5-V Pre-Biased)
Figure 25. 1.5-V Soft-Stop Waveforms (Tracking Discharge) Figure 26. 1.5-V Soft-Stop Waveforms (Non-Tracking
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
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Discharge)
10000 100000 1000000 10000000
−80
−60
−40
−20
0
20
40
60
80
−180
−135
−90
−45
0
45
90
135
180
Frequency (Hz)
Gain (dB)
Phase (°)
Gain Phase
I
VTT
= −1 A
10000 100000 1000000 10000000
−80
−60
−40
−20
0
20
40
60
80
−180
−135
−90
−45
0
45
90
135
180
Frequency (Hz)
Gain (dB)
Phase (°)
Gain Phase
I
VTT
= 1 A
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
Figure 27. VTT Bode Plot (Sink) Figure 28. VTT Bode Plot (Source)
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Product Folder Links :TPS51216
700 ms400 ms 1.4 ms
S5
VREF
VDDQ
PGOOD
UDG-10137
TPS51216
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APPLICATION INFORMATION

VDDQ Switch Mode Power Supply Control

TPS51216 supports D-CAP™ mode which does not require complex external compensation networks and is suitable for designs with small external components counts. The D-CAP™ mode provides fast transient response with appropriate amount of equivalent series resistance (ESR) on the output capacitors. An adaptive on-time control scheme is used to achieve pseudo-constant frequency. The TPS51216 adjusts the on-time (tON) to be inversely proportional to the input voltage (VIN) and proportional to the output voltage (V switching frequency fairy constant over the variation of input voltage at the steady state condition.

VREF and REFIN, VDDQ Output Voltage

The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-μA (max) current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of
0.1-μF or larger should be attached close to the VREF terminal. The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range
between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See External
Components Selection section.) A few nano farads of capacitance from REFIN to GND is recommended for
stable operation.

Soft-Start and Powergood

TPS51216 provides integrated VDDQ soft-start functions to suppress in-rush current at start-up. The soft-start is achieved by controlling internal reference voltage ramping up. Figure 29 shows the start-up waveforms. The switching regulator waits for 400μs after S5 assertion. The MODE pin voltage is read in this period. A typical VDDQ ramp up duration is 700μs.
TPS51216 has a powergood open-drain output that indicates the VDDQ voltage is within the target range. The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The PGOOD comparator is enabled 1.1 ms after VREF is raised high and the start-up delay is 2.5 ms. Note that the time constant which is composed of the REFIN capacitor and a resistor divider needs to be short enough to reach the target value before PGOOD comparator enabled.
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
). This makes a
DDQ
Figure 29. Typical Start-up Waveforms
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

Power State Control

The TPS51216 has two input pins, S3 and S5, to provide simple control scheme of power state. All of VDDQ, VTTREF and VTT are turned on at S0 state (S3=S5=high). In S3 state (S3=low, S5=high), VDDQ and VTTREF voltages are kept on while VTT is turned off and left at high impedance state (high-Z). The VTT output floats and does not sink or source current in this state. In S4/S5 states (S3=S5=low), all of the three outputs are turned off and discharged to GND according to the discharge mode selected by MODE pin. Each state code represents as follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 1)
Table 1. S3/S5 Power State Control
STATE S3 S5 VREF VDDQ VTTREF VTT
S0 HI HI ON ON ON ON S3 LO HI ON ON ON OFF(High-Z)
S4/S5 LO LO OFF OFF(Discharge) OFF(Discharge) OFF(Discharge)

MODE Pin Configuration

The TPS51216 reads the MODE pin voltage when the S5 signal is raised high and stores the status in a register. A 15-μA current is sourced from the MODE pin during this time to read the voltage across the resistor connected between the pin and GND. Table 2 shows resistor values, corresponding switching frequency and discharge mode configurations.
Table 2. MODE Selection
MODE NO. DISCHARGE MODE
3 200 400 Tracking 2 100 300 1 68 300 Non-tracking 0 47 400
RESISTANCE BETWEEN SWITCHING
MODE AND GND ( kΩ) FREQUENCY (kHz)
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Discharge Control

In S4/S5 state, VDDQ, VTT, and VTTREF outputs are discharged based on the respective discharge mode selected above. The tracking discharge mode discharges VDDQ output through the internal VTT regulator transistors enabling quick discharge operation. The VTT output maintains tracking of the VTTREF voltage in this mode. (Please refer to Figure 25) After 4 ms of tracking discharge operation, the mode changes to non-tracking discharge. The VDDQ output must be connected to the VLDOIN pin in this mode. The non-tracking mode discharges the VDDQ and VTT pins using internal MOSFETs that are connected to corresponding output terminals. The non-tracking discharge is slow compared with the tracking discharge due to the lower current capability of these MOSFETs. (Please refer to Figure 26)
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Product Folder Links :TPS51216
= £
´
SW
0
OUT
f
1
f
2 ESR C 3
9
+
8
PWM
VDDQSNS
REFIN
6
VREF
Control
Logic
and
Driver
R1
R2
14
11
DRVH
DRVL
+
1.8 V
V
IN
Lx
ESR
C
OUT
R
LOAD
UDG-10136
High-Side MOSFET
Low-Side MOSFET
VDDQ
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D-CAP™ Mode

Figure 30 shows a simplified model of D-CAP™ mode architecture.
Figure 30. Simplified D-CAP™ Model
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage increase. The D-CAP™ mode offers flexibility on output inductance and capacitance selections and provides ease-of-use with a low external component count. However, it requires a sufficient amount of output ripple voltage for stable operation and good jitter performance.
The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, f0defined in
Equation 1, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.
Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that determine jitter performance in D-CAP™ mode is the down-slope angle of the VDDQSNS ripple voltage.
Figure 31 shows, in the same noise condition, a jitter is improved by making the slope angle larger.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 17
where
ESR is the effective series resistance of the output capacitor
C
fswis switching frequency (1)
is the capacitance of the output capacitor
OUT
Product Folder Links :TPS51216
( )
-
= ´ ´
´
IN OUT
OUT
LOAD(LL)
X IN SW
V V
V
1
I
2 L V f
´
³
´
OUT
SW X
V ESR
20mV
f L
V
VDDQSNS
V
REFIN
(1)
(2)
t
ON
t
OFF
Slope (2)
Jitter
20 mV
Slope (1)
Jitter
UDG-10139
V
REFIN
+Noise
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
Figure 31. Ripple Voltage Slope and Jitter Performance
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For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as shown in Figure 31 and Equation 2.
where
V
LXis the inductance (2)
is the VDDQ output voltage
OUT

Light-Load Operation

In auto-skip mode, the TPS51216 SMPS control logic automatically reduces its switching frequency to improve light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative inductor current by turning off the low-side MOSFET. Equation 3 shows the boundary load condition of this skip mode and continuous conduction operation.
(3)
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12
17
16
6
15
14
13
11
V5IN
TPS51216
S3
S5
VREF
VBST
DRVH
SW
DRVL
8
10
REFIN
PGND
719GND
MODE
18 TRIP
20
9
2
3
PGOOD
VDDQSNS
VLDOIN
VTT
1
4
5
VTTSNS
VTTGND
VTTREF
UDG-13089
VDDQ
S5
PGND
5VIN
PGND
VIN
AGND
Powergood
PGND
1 kW
PGND
PGND
0.22 mF
AGND
TPS51216
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VTT and VTTREF

TPS51216 integrates two high performance, low-drop-out linear regulators, VTT and VTTREF, to provide complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-μF (or larger) ceramic capacitor must be connected close to the VTTREF terminal for stable operation. The VTT responds quickly to track VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-μF (or larger) ceramic capacitor(s) need to be connected close to the VTT terminal for stable operation. To achieve tight regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to the positive node of VTT output capacitor(s) as a separate trace from the high-current line to the VTT pin. (Please refer to the Layout Considerations section for details.)
When VTT is not required in the design, the following treatments are strongly recommended.
Connect VLDOIN to VDDQ.
Tie VTTSNS to VTT, and remove capacitors from VTT to float.
Connect VTTGND to GND.
Select MODE 0 or MODE 1 shown in Table 2 (Select Non-tracking discharge mode).
Maintain a 0.22-µF capacitor connected at VTTREF.
Pull-down S3 to GND with 1-kΩ resistance.
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 19
Figure 32. Application Circuit When VTT Is Not Required
Product Folder Links :TPS51216
( )
( )
( )
æ ö æ ö
-
ç ÷ ç ÷
= + = + ´ ´
ç ÷ ç ÷
´ ´ ´
è ø è ø
IND ripple
IN OUT OUT
TRIP TRIP
OCL
X SW IN
DS on DS on
I
V V V
V V
1
I
8 R 2 8 R 2 L f V
= ´
TRIP TRIP TRIP
V R I
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

VDDQ Overvoltage and Undervoltage Protection

TPS51216 sets the overvoltage protection (OVP) when the VDDQSNS voltage reaches a level 20% (typ) higher than the REFIN voltage. When an OV event is detected, the controller latches DRVH low and DRVL high. VTTREF and VTT are turned off and discharged using the non-tracking discharge MOSFETs regardless of the tracking mode.
The undervoltage protection (UVP) latch is set when the VDDQSNS voltage remains lower than 68% (typ) of the REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and discharges the VDDQ, VTT and VTTREF outputs. UVP detection function is enabled after 1.2 ms of SMPS operation to ensure startup.
To release the OVP and UVP latches, toggle S5 or adjust the V5IN voltage down and up beyond the undervoltage lockout threshold.

VDDQ Overcurrent Protection

The VDDQ SMPS has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the off-state using the low-side MOSFET R the low-side MOSFET is larger than the overcurrent trip level. The current monitor circuit inputs are PGND and SW pins so that those should be properly connected to the source and drain terminals of low-side MOSFET. The overcurrent trip level, V
, is determined by Equation 4, where R
TRIP
between the TRIP pin and GND, and I room temperature, and has 4700ppm/°C temperature coefficient to compensate the temperature dependency of the low-side MOSFET R
DS(on)
.
Because the comparison is done during the off-state, V current OCL level, I
, can be calculated by considering the inductor ripple current as shown in Equation 5
OCL
and the controller maintains the off-state while the voltage across
DS(on)
is the value of the resistor connected
is the current sourced from the TRIP pin. I
TRIP
sets the valley level of the inductor current. The load
TRIP
TRIP
is 10 μA typically at
TRIP
www.ti.com
(4)
where
I
IND(ripple)
is inductor ripple current (5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.

VTT Overcurrent Protection

The LDO has an internally fixed constant overcurrent limiting of 3-A (typ) for both sink and source operation.

V5IN Undervoltage Lockout Protection

TPS51216 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5IN voltage is lower than UVLO threshold voltage, typically 3.93 V, VDDQ, VTT and VTTREF are shut off. This is a non-latch protection.

Thermal Shutdown

TPS51216 includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C (typ), VDDQ, VTT and VTTREF are shut off. The thermal shutdown state of VDDQ is open, VTT and VTTREF are high impedance (high-Z) respectively, and the discharge functions are disabled. This is a non-latch protection and the operation is restarted with soft-start sequence when the device temperature is reduced by 10°C (typ).
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´
³
´
OUT
SW X
V ESR
20mV
f L
£
´
SW
OUT
f
1
2 ESR C 3
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X
SW IN
TRIP
TRIP
V V
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8 I R
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)
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max
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DS on max
V V V
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1
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IN OUT OUT IN OUT OUT
max max
X
SW IN O SW IN
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V V V V V V
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=
æ ö ç ÷ ç ÷ ç ÷
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IND ripple
OUT
R1
R2
1.8 1
I ESR
V
2
TPS51216
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External Components Selection

The external components selection is simple in D-CAP™ mode.
1. DETERMINE THE VALUE OF R1 AND R2 The output voltage is determined by the value of the voltage-divider resistor, R1 and R2 as shown in
Figure 30. R1 is connected between VREF and REFIN pins, and R2 is connected between the REFIN pin
and GND. Setting R1 as 10-kΩ is a good starting point. Determine R2 using Equation 6.
2. CHOOSE THE INDUCTOR The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum
output current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio and helps stable operation.
The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room above peak inductor current before saturation. The peak inductor current can be estimated in Equation 8.
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
(6)
(7)
3. CHOOSE THE OCL SETTING RESISTANCE, R Combining Equation 4 and Equation 5, R
4. CHOOSE THE OUTPUT CAPACITORS Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to
meet small signal stability and recommended ripple voltage. A quick reference is shown in Equation 10 and
Equation 11.
TRIP
TRIP
can be obtained using Equation 9.
(8)
(9)
(10)
(11)
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links :TPS51216
´ ´
³ ³
´
SW
OUT SW OUT
20mV f L
3
ESR or ESR
V 2 f C
1
2
3
4
15
14
13
12
VTTSNS
U1
TPS51216RUK
VLDOIN
VTT
VTTGND
VBST
DRVH
SW
V5IN
5 11VTTREF DRVL
10987
PGND
VDDQSNS
REFIN
GND
6
VREF
16171819
S5
S3
TRIP
MODE
20
PGOOD
21
PwPad
C6 1 mF
UDG-10165
C7
0.1 mFC810 mFC910 mF
C10
10 mF
V
IN
8 V to 20 V
PGND
R6
0 W
C5
0.1 mF
R7 0 W
L1
0.56 mH
Q2 FDMS8670AS
Q3 FDMS8670AS
C11
330 mF
VDDQ_GND
PGND AGND
R5 49 kW
R4 10 kW
C3
0.1 mFC410 nF
C2
0.22 mF
C1
10 mF
C12
10 mF
PGND
VTT
0.75 V/2 A
VTTREF
0.75 V
VTTGND
S5 S3
R1 100 kW
R2 200 kW
R3 36 kW
V5IN
4.5 V to 5.5 V
Q1 FDMS8680
VDDQ
1.5 V/20 A
AGND
PGND
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

TPS51216 Application Circuit

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REFERENCE
DESIGNATOR
C8, C9, C10 3 10 µF, 25 V Taiyo Yuden TMK325BJ106MM C11 1 330 µF, 2V, 6 mΩ Panasonic EEFSX0D331XE L1 1 0.56 µH, 21 A, 1.56 mΩ Panasonic ETQP4LR56WFC Q1 1 30 V, 35 A, 8.5 mΩ Fairchild FDMS8680 Q2, Q3 2 30 V, 42 A, 3.5 mΩ Fairchild FDMS8670AS
For this example, the bulk output capacitor ESR requirement for D-CAP™ mode is described in Equation 12, whichever is greater.
22 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Figure 33. DDR3, 400-kHz Application Circuit, Tracking Discharge
Table 3. DDR3, 400-kHz Application Circuit, List of Materials
QTY SPECIFICATION MANUFACTURE PART NUMBER
Product Folder Links :TPS51216
(12)
TPS51216
DRVL
11
VIN
REFIN GND
V5IN
12
V
OUT
TRIP
MODE
10
7
PGND
VREF
19
18
4
3
VTT
UDG-10166
VTTGND
5
0.22 mF
VTTREF
2
86
10 mF
10 nF
0.1 mF
VTT
VTTGND
VLDOIN
1 mF
#1
#2
#3
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SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

Layout Considerations

Certain issues must be considered before designing a layout using the TPS51216.
TPS51216
Figure 34. DC/DC Converter Ground System
VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one side of the PCB (solder side). Other small signal components should be placed on another side (component side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the small signal traces from noisy power lines.
All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF and TRIP should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and components.
The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and
low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the VIN capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop #1 of
Figure 34)
– The second important loop is the path from the low-side MOSFET through inductor and VOUT
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET and negative node of VOUT capacitor(s) at ground as close as possible. (Refer to loop #2 of
Figure 34)
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the low-side MOSFET through ground. Connect negative node of V5IN capacitor, source of the low-side MOSFET and PGND at ground as close as possible. (Refer to loop #3 of Figure 34)
Because the TPS51216 controls output voltage referring to voltage across VOUT capacitor, VDDQSNS should be connected to the positive node of VOUT capacitor. In a same manner GND should be connected to the negative node of VOUT capacitor.
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links :TPS51216
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling to a high-voltage switching node.
Connect the frequency and mode setting resistor from MODE pin to ground, and make the connections as close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground should avoid coupling to a high-voltage switching node
Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5 mm (20 mils) diameter along this trace.
The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
VLDOIN should be connected to VDDQ output with short and wide traces. An input bypass capacitor should be placed as close as possible to the pin with short and wide connections.
The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to  avoid additional ESR and/or ESL of the trace.
VTTSNS should be connected to the positive node of the VTT output capacitor(s) as a separate trace from the high-current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to sense the voltage at the point of the load, it is recommended to attach the output capacitor(s) at that point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and the output capacitor(s).
Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitor(s) is larger than 2 mΩ.
VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference  voltage of VTTREF. Avoid any noise generative lines.
The negative node of the VTT output capacitor(s) and the VTTREF capacitor should be tied together by avoiding common impedance to high-current path of the VTT source/sink current.
GND pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR and/or ESL. GND and PGND should be connected together at a single point.
In order to effectively remove heat from the package, prepare the thermal land and solder to the package  thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading. Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder­side ground plane(s) should be used to help dissipation.
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CAUTION
Do NOT connect PGND pin directly to this thermal land underneath the package.
24 Submit Documentation Feedback Copyright © 2010–2013, Texas Instruments Incorporated
Product Folder Links :TPS51216
TPS51216
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REVISION HISTORY

Changes from Original (November 2010) to Revision A Page
Added specifications to ABSOLUTE MAXIMUM RATINGS table. ....................................................................................... 2
Added clarity to VTT and VTTREF section. ........................................................................................................................ 19
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links :TPS51216
PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device Status
FX004Z ACTIVE WQFN RUK 20 3000 Green (RoHS
TPS51216RUKR ACTIVE WQFN RUK 20 3000 Green (RoHS
TPS51216RUKT ACTIVE WQFN RUK 20 250 Green (RoHS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51216
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51216
CU NIPDAU Level-2-260C-1 YEAR -40 to 85 51216
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
9-Sep-2014
Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
9-Sep-2014
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
TPS51216RUKR WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS51216RUKT WQFN RUK 20 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
Package Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)B0(mm)K0(mm)P1(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Aug-2015
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51216RUKR WQFN RUK 20 3000 367.0 367.0 35.0
TPS51216RUKT WQFN RUK 20 250 210.0 185.0 35.0
Pack Materials-Page 2
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