Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous Buck
Controller, 2-A LDO, Buffered Reference
Check for Samples: TPS51216
1
FEATURES
2
•Synchronous Buck Controller (VDDQ)
– Conversion Voltage Range: 3 V to 28 V
– Output Voltage Range: 0.7 V to 1.8 V
– 0.8% V
– D-CAP™ Mode for Fast Transient Response
– Selectable 300 kHz/400 kHz Switching
Frequencies
– Optimized Efficiency at Light and Heavy
Loads with Auto-skip Function
– Supports Soft-Off in S4/S5 States
– OCL/OVP/UVP/UVLO Protections
– Powergood Output
•2-A LDO(VTT), Buffered Reference(VTTREF)
– 2-A (Peak) Sink and Source Current
– Requires Only 10-μF of Ceramic Output
Capacitance
– Buffered, Low Noise, 10-mA VTTREF
Output
– 0.8% VTTREF, 20-mV VTT Accuracy
– Support High-Z in S3 and Soft-Off in S4/S5
•Thermal Shutdown
•20-Pin, 3 mm × 3 mm, QFN Package
Accuracy
REF
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
DESCRIPTION
The TPS51216 provides a complete power supply for
DDR2, DDR3 and DDR3L memory systems in the
lowest total cost and minimum space. It integrates a
synchronous buck regulator controller (VDDQ) with a
2-A sink/source tracking LDO (VTT) and buffered low
noise reference (VTTREF). The TPS51216 employs
D-CAP™ mode coupled with 300 kHz/400 kHz
frequenciesforease-of-useandfasttransient
response.TheVTTREF tracksVDDQ/2within
excellent 0.8% accuracy. The VTT, which provides 2A sink/source peak current capabilities, requires only
10-μFofceramiccapacitance.Inaddition,a
dedicated LDO supply input is available.
The TPS51216 provides rich useful functions as well
as excellent power supply performance. It supports
flexible power state control, placing VTT at high-Z in
S3 and discharging VDDQ, VTT and VTTREF (softoff) in S4/S5 state. Programmable OCL with low-side
MOSFETR
DS(on)
thermal shutdown protections are also available.
The TPS51216 is available in a 20-pin, 3 mm × 3
mm, QFN package and is specified for ambient
temperature from –40°C to 85°C.
sensing,OVP/UVP/UVLOand
APPLICATIONS
•DDR2/DDR3/DDR3L Memory Power Supplies
•SSTL_18, SSTL_15, SSTL_135 and HSTL
Termination
1
2D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testingof all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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ORDERING INFORMATION
T
A
PACKAGEPINS
–40°C to 85°CPlastic Quad Flat Pack (20 pin QFN)20
ORDERABLE DEVICEOUTPUTMINIMUM
NUMBERSUPPLYQUANTITY
TPS51216RUKRTape and reel3000
TPS51216RUKTMini reel250
(1)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
PGOOD–0.36
Junction temperature range, T
Storage temperature range, T
J
STG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
DRVH14OHigh-side MOSFET gate driver output.
DRVL11OLow-side MOSFET gate driver output.
GND7–Signal ground.
MODE19IConnect resistor to GND to configure switching frequency and discharge mode. (See Table 2)
PGND10–Gate driver power ground. R
PGOOD20OPowergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
REFIN8I
SW13I/O High-side MOSFET gate driver return. R
S317IS3 signal input. (See Table 1)
S516IS5 signal input. (See Table 1)
TRIP18IConnect resistor to GND to set OCL at V
VBST15IHigh-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQSNS9IVDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
VLDOIN2IPower supply input for VTT LDO. Connect VDDQ in typical application.
VREF6O1.8-V reference output.
VTT3OVTT 2-A LDO output. Need to connect 10μF or larger capacitance for stability.
VTTGND4–Power ground for VTT LDO.
VTTREF5OBuffered VTT reference output. Need to connect 0.22μF or larger capacitance for stability.
VTTSNS1IVTT output voltage feedback.
V5IN12I5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal
pad
I/ODESCRIPTION
current sensing input(+).
DS(on)
Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for
stable operation.
current sensing input(–).
DS(on)
/8. Output 10-μA current at room temperature, TC= 4700 ppm/°C.
TPS51216 supports D-CAP™ mode which does not require complex external compensation networks and is
suitable for designs with small external components counts. The D-CAP™ mode provides fast transient response
with appropriate amount of equivalent series resistance (ESR) on the output capacitors. An adaptive on-time
control scheme is used to achieve pseudo-constant frequency. The TPS51216 adjusts the on-time (tON) to be
inversely proportional to the input voltage (VIN) and proportional to the output voltage (V
switching frequency fairy constant over the variation of input voltage at the steady state condition.
VREF and REFIN, VDDQ Output Voltage
The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-μA (max)
current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of
0.1-μF or larger should be attached close to the VREF terminal.
The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range
between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See External
Components Selection section.) A few nano farads of capacitance from REFIN to GND is recommended for
stable operation.
Soft-Start and Powergood
TPS51216 provides integrated VDDQ soft-start functions to suppress in-rush current at start-up. The soft-start is
achieved by controlling internal reference voltage ramping up. Figure 29 shows the start-up waveforms. The
switching regulator waits for 400μs after S5 assertion. The MODE pin voltage is read in this period. A typical
VDDQ ramp up duration is 700μs.
TPS51216 has a powergood open-drain output that indicates the VDDQ voltage is within the target range. The
target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay for
assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The
PGOOD comparator is enabled 1.1 ms after VREF is raised high and the start-up delay is 2.5 ms. Note that the
time constant which is composed of the REFIN capacitor and a resistor divider needs to be short enough to
reach the target value before PGOOD comparator enabled.
The TPS51216 has two input pins, S3 and S5, to provide simple control scheme of power state. All of VDDQ,
VTTREF and VTT are turned on at S0 state (S3=S5=high). In S3 state (S3=low, S5=high), VDDQ and VTTREF
voltages are kept on while VTT is turned off and left at high impedance state (high-Z). The VTT output floats and
does not sink or source current in this state. In S4/S5 states (S3=S5=low), all of the three outputs are turned off
and discharged to GND according to the discharge mode selected by MODE pin. Each state code represents as
follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF. (See Table 1)
The TPS51216 reads the MODE pin voltage when the S5 signal is raised high and stores the status in a register.
A 15-μA current is sourced from the MODE pin during this time to read the voltage across the resistor connected
between the pin and GND. Table 2 shows resistor values, corresponding switching frequency and discharge
mode configurations.
Table 2. MODE Selection
MODE NO.DISCHARGE MODE
3200400Tracking
2100300
168300Non-tracking
047400
RESISTANCE BETWEENSWITCHING
MODE AND GND ( kΩ)FREQUENCY (kHz)
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Discharge Control
In S4/S5 state, VDDQ, VTT, and VTTREF outputs are discharged based on the respective discharge mode
selected above. The tracking discharge mode discharges VDDQ output through the internal VTT regulator
transistors enabling quick discharge operation. The VTT output maintains tracking of the VTTREF voltage in this
mode. (Please refer to Figure 25) After 4 ms of tracking discharge operation, the mode changes to non-tracking
discharge. The VDDQ output must be connected to the VLDOIN pin in this mode. The non-tracking mode
discharges the VDDQ and VTT pins using internal MOSFETs that are connected to corresponding output
terminals. The non-tracking discharge is slow compared with the tracking discharge due to the lower current
capability of these MOSFETs. (Please refer to Figure 26)
Figure 30 shows a simplified model of D-CAP™ mode architecture.
Figure 30. Simplified D-CAP™ Model
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on
the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the
beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage
monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage
increase. The D-CAP™ mode offers flexibility on output inductance and capacitance selections and provides
ease-of-use with a low external component count. However, it requires a sufficient amount of output ripple
voltage for stable operation and good jitter performance.
The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, f0defined in
Equation 1, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.
Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that
determine jitter performance in D-CAP™ mode is the down-slope angle of the VDDQSNS ripple voltage.
Figure 31 shows, in the same noise condition, a jitter is improved by making the slope angle larger.
•ESR is the effective series resistance of the output capacitor
•C
•fswis switching frequency(1)
is the capacitance of the output capacitor
OUT
Product Folder Links :TPS51216
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INOUT
OUT
LOAD(LL)
XINSW
VV
V
1
I
2 LVf
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OUT
SWX
VESR
20mV
fL
V
VDDQSNS
V
REFIN
(1)
(2)
t
ON
t
OFF
Slope (2)
Jitter
20 mV
Slope (1)
Jitter
UDG-10139
V
REFIN
+Noise
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
Figure 31. Ripple Voltage Slope and Jitter Performance
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For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as
shown in Figure 31 and Equation 2.
where
•V
•LXis the inductance(2)
is the VDDQ output voltage
OUT
Light-Load Operation
In auto-skip mode, the TPS51216 SMPS control logic automatically reduces its switching frequency to improve
light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent negative
inductor current by turning off the low-side MOSFET. Equation 3 shows the boundary load condition of this skip
mode and continuous conduction operation.
TPS51216 integrates two high performance, low-drop-out linear regulators, VTT and VTTREF, to provide
complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and
tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-μF (or larger) ceramic capacitor
must be connected close to the VTTREF terminal for stable operation. The VTT responds quickly to track
VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-μF (or
larger) ceramic capacitor(s) need to be connected close to the VTT terminal for stable operation. To achieve tight
regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to
the positive node of VTT output capacitor(s) as a separate trace from the high-current line to the VTT pin.
(Please refer to the Layout Considerations section for details.)
When VTT is not required in the design, the following treatments are strongly recommended.
•Connect VLDOIN to VDDQ.
•Tie VTTSNS to VTT, and remove capacitors from VTT to float.
•Connect VTTGND to GND.
•Select MODE 0 or MODE 1 shown in Table 2 (Select Non-tracking discharge mode).
•Maintain a 0.22-µF capacitor connected at VTTREF.
Figure 32. Application Circuit When VTT Is Not Required
Product Folder Links :TPS51216
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INOUTOUT
TRIPTRIP
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
VDDQ Overvoltage and Undervoltage Protection
TPS51216 sets the overvoltage protection (OVP) when the VDDQSNS voltage reaches a level 20% (typ) higher
than the REFIN voltage. When an OV event is detected, the controller latches DRVH low and DRVL high.
VTTREF and VTT are turned off and discharged using the non-tracking discharge MOSFETs regardless of the
tracking mode.
The undervoltage protection (UVP) latch is set when the VDDQSNS voltage remains lower than 68% (typ) of the
REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and
discharges the VDDQ, VTT and VTTREF outputs. UVP detection function is enabled after 1.2 ms of SMPS
operation to ensure startup.
To release the OVP and UVP latches, toggle S5 or adjust the V5IN voltage down and up beyond the
undervoltage lockout threshold.
VDDQ Overcurrent Protection
The VDDQ SMPS has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the
off-state using the low-side MOSFET R
the low-side MOSFET is larger than the overcurrent trip level. The current monitor circuit inputs are PGND and
SW pins so that those should be properly connected to the source and drain terminals of low-side MOSFET. The
overcurrent trip level, V
, is determined by Equation 4, where R
TRIP
between the TRIP pin and GND, and I
room temperature, and has 4700ppm/°C temperature coefficient to compensate the temperature dependency of
the low-side MOSFET R
DS(on)
.
Because the comparison is done during the off-state, V
current OCL level, I
, can be calculated by considering the inductor ripple current as shown in Equation 5
OCL
and the controller maintains the off-state while the voltage across
DS(on)
is the value of the resistor connected
is the current sourced from the TRIP pin. I
TRIP
sets the valley level of the inductor current. The load
TRIP
TRIP
is 10 μA typically at
TRIP
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(4)
where
•I
IND(ripple)
is inductor ripple current(5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.
VTT Overcurrent Protection
The LDO has an internally fixed constant overcurrent limiting of 3-A (typ) for both sink and source operation.
V5IN Undervoltage Lockout Protection
TPS51216 has a 5-V supply undervoltage lockout protection (UVLO) threshold. When the V5IN voltage is lower
than UVLO threshold voltage, typically 3.93 V, VDDQ, VTT and VTTREF are shut off. This is a non-latch
protection.
Thermal Shutdown
TPS51216 includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C (typ),
VDDQ, VTT and VTTREF are shut off. The thermal shutdown state of VDDQ is open, VTT and VTTREF are high
impedance (high-Z) respectively, and the discharge functions are disabled. This is a non-latch protection and the
operation is restarted with soft-start sequence when the device temperature is reduced by 10°C (typ).
The external components selection is simple in D-CAP™ mode.
1. DETERMINE THE VALUE OF R1 AND R2
The output voltage is determined by the value of the voltage-divider resistor, R1 and R2 as shown in
Figure 30. R1 is connected between VREF and REFIN pins, and R2 is connected between the REFIN pin
and GND. Setting R1 as 10-kΩ is a good starting point. Determine R2 using Equation 6.
2. CHOOSE THE INDUCTOR
The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum
output current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio
and helps stable operation.
The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room
above peak inductor current before saturation. The peak inductor current can be estimated in Equation 8.
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
(6)
(7)
3. CHOOSE THE OCL SETTING RESISTANCE, R
Combining Equation 4 and Equation 5, R
4. CHOOSE THE OUTPUT CAPACITORS
Organic semiconductor capacitor(s) or specialty polymer capacitor(s) are recommended. Determine ESR to
meet small signal stability and recommended ripple voltage. A quick reference is shown in Equation 10 and
Table 3. DDR3, 400-kHz Application Circuit, List of Materials
QTYSPECIFICATIONMANUFACTUREPART NUMBER
Product Folder Links :TPS51216
(12)
TPS51216
DRVL
11
VIN
REFIN GND
V5IN
12
V
OUT
TRIP
MODE
10
7
PGND
VREF
19
18
4
3
VTT
UDG-10166
VTTGND
5
0.22 mF
VTTREF
2
86
10 mF
10 nF
0.1 mF
VTT
VTTGND
VLDOIN
1 mF
#1
#2
#3
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SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
Layout Considerations
Certain issues must be considered before designing a layout using the TPS51216.
TPS51216
Figure 34. DC/DC Converter Ground System
•VIN capacitor(s), VOUT capacitor(s) and MOSFETs are the power components and should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
•All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF and TRIP
should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH or VBST to avoid
coupling. Use internal layer(s) as ground plane(s) and shield feedback trace from power traces and
components.
•The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VIN capacitor(s) through the high and
low-side MOSFETs, and back to the capacitor(s) through ground. Connect the negative node of the VIN
capacitor(s) and the source of the low-side MOSFET at ground as close as possible. (Refer to loop #1 of
Figure 34)
– The second important loop is the path from the low-side MOSFET through inductor and VOUT
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
capacitor(s), and back to source of the low-side MOSFET through ground. Connect source of the low-side
MOSFET and negative node of VOUT capacitor(s) at ground as close as possible. (Refer to loop #2 of
Figure 34)
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows
from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the low-side
MOSFET through ground. Connect negative node of V5IN capacitor, source of the low-side MOSFET and
PGND at ground as close as possible. (Refer to loop #3 of Figure 34)
•Because the TPS51216 controls output voltage referring to voltage across VOUT capacitor, VDDQSNS
should be connected to the positive node of VOUT capacitor. In a same manner GND should be connected to
the negative node of VOUT capacitor.
•Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
•Connect the frequency and mode setting resistor from MODE pin to ground, and make the connections as
close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground
should avoid coupling to a high-voltage switching node
•Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and via(s) of at least 0.5
mm (20 mils) diameter along this trace.
•The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the
rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
•VLDOIN should be connected to VDDQ output with short and wide traces. An input bypass capacitor should
be placed as close as possible to the pin with short and wide connections.
•The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to
avoid additional ESR and/or ESL of the trace.
•VTTSNS should be connected to the positive node of the VTT output capacitor(s) as a separate trace from
the high-current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed
to sense the voltage at the point of the load, it is recommended to attach the output capacitor(s) at that
point. Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin
and the output capacitor(s).
•Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitor(s) is larger
than 2 mΩ.
•VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of VTTREF. Avoid any noise generative lines.
•The negative node of the VTT output capacitor(s) and the VTTREF capacitor should be tied together by
avoiding common impedance to high-current path of the VTT source/sink current.
•GND pin node represents the reference potential for VTTREF and VTT outputs. Connect GND to negative
nodes of VTT capacitor(s), VTTREF capacitor and VDDQ capacitor(s) with care to avoid additional ESR
and/or ESL. GND and PGND should be connected together at a single point.
•In order to effectively remove heat from the package, prepare the thermal land and solder to the package
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat
spreading. Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solderside ground plane(s) should be used to help dissipation.
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CAUTION
Do NOT connect PGND pin directly to this thermal land underneath the package.
Changes from Original (November 2010) to Revision APage
•Added specifications to ABSOLUTE MAXIMUM RATINGS table. ....................................................................................... 2
•Added clarity to VTT and VTTREF section. ........................................................................................................................ 19
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Package Type Package
(1)
Drawing
Pins Package
Qty
Eco Plan
(2)
& no Sb/Br)
& no Sb/Br)
& no Sb/Br)
Lead/Ball Finish
(6)
CU NIPDAULevel-2-260C-1 YEAR-40 to 8551216
CU NIPDAULevel-2-260C-1 YEAR-40 to 8551216
CU NIPDAULevel-2-260C-1 YEAR-40 to 8551216
MSL Peak Temp
(3)
Op Temp (°C)Device Marking
(4/5)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
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lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
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Samples
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
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endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
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Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
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regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
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