Texas Instruments TPS51216RUKR, FX004Z Schematics

12
17
16
6
15
14
13
11
V5IN
TPS51216
S3
S5
VREF
DRVH
SW
DRVL
8
10
REFIN
PGND
7
19
GND
MODE
18 TRIP
20
9
2
3
PGOOD
VDDQSNS
VLDOIN
VTT
1
4
5
VTTSNS
VTTGND
VTTREF
UDG-10138
VDDQ
VTT
PGND
S3
S5
PGND
5VIN
PGND
VIN
VTTREF
AGND
AGND
Powergood
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Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous Buck
Controller, 2-A LDO, Buffered Reference
Check for Samples: TPS51216
1

FEATURES

2
Synchronous Buck Controller (VDDQ) – Conversion Voltage Range: 3 V to 28 V – Output Voltage Range: 0.7 V to 1.8 V – 0.8% V – D-CAP™ Mode for Fast Transient Response – Selectable 300 kHz/400 kHz Switching
Frequencies
– Optimized Efficiency at Light and Heavy
Loads with Auto-skip Function – Supports Soft-Off in S4/S5 States – OCL/OVP/UVP/UVLO Protections – Powergood Output
2-A LDO(VTT), Buffered Reference(VTTREF) – 2-A (Peak) Sink and Source Current – Requires Only 10-μF of Ceramic Output
Capacitance
– Buffered, Low Noise, 10-mA VTTREF
Output – 0.8% VTTREF, 20-mV VTT Accuracy – Support High-Z in S3 and Soft-Off in S4/S5
Thermal Shutdown
20-Pin, 3 mm × 3 mm, QFN Package
Accuracy
REF
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

DESCRIPTION

The TPS51216 provides a complete power supply for DDR2, DDR3 and DDR3L memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink/source tracking LDO (VTT) and buffered low noise reference (VTTREF). The TPS51216 employs D-CAP™ mode coupled with 300 kHz/400 kHz frequencies for ease-of-use and fast transient response. The VTTREF tracks VDDQ/2 within excellent 0.8% accuracy. The VTT, which provides 2­A sink/source peak current capabilities, requires only 10-μF of ceramic capacitance. In addition, a dedicated LDO supply input is available.
The TPS51216 provides rich useful functions as well as excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft­off) in S4/S5 state. Programmable OCL with low-side MOSFET R
DS(on)
thermal shutdown protections are also available. The TPS51216 is available in a 20-pin, 3 mm × 3
mm, QFN package and is specified for ambient temperature from –40°C to 85°C.
sensing, OVP/UVP/UVLO and

APPLICATIONS

DDR2/DDR3/DDR3L Memory Power Supplies
SSTL_18, SSTL_15, SSTL_135 and HSTL Termination
1
2D-CAP is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2010–2013, Texas Instruments Incorporated
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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ORDERING INFORMATION
T
A
PACKAGE PINS
–40°C to 85°C Plastic Quad Flat Pack (20 pin QFN) 20
ORDERABLE DEVICE OUTPUT MINIMUM
NUMBER SUPPLY QUANTITY
TPS51216RUKR Tape and reel 3000 TPS51216RUKT Mini reel 250
(1)
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
MIN MAX
VBST –0.3 36
(3)
VBST SW –5 30
Input voltage range
(2)
VLDOIN, VDDQSNS, REFIN –0.3 3.6 V VTTSNS –0.3 3.6 PGND, VTTGND –0.3 0.3 V5IN, S3, S5, TRIP, MODE –0.3 6 DRVH –5 36
(3)
DRVH
(3)
Output voltage range
DRVH VTTREF, VREF –0.3 3.6
(2)
VTT –0.3 3.6
(duty cycle < 1%) –2.5 6
DRVL –0.3 6 DRVL (duty cycle < 1%) –2.5 6
PGOOD –0.3 6 Junction temperature range, T Storage temperature range, T
J
STG
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to the network ground terminal unless otherwise noted. (3) Voltage values are with respect to the SW terminal.
–0.3 6
–0.3 6
V
125 °C
–55 150 °C

THERMAL INFORMATION

THERMAL METRIC UNITS
θ
θ
θ
ψ
ψ
θ
JA JCtop JB
JT JB
JCbot
Junction-to-ambient thermal resistance 94.1 Junction-to-case (top) thermal resistance 58.1 Junction-to-board thermal resistance 64.3 Junction-to-top characterization parameter 31.8 Junction-to-board characterization parameter 58.0 Junction-to-case (bottom) thermal resistance 5.9
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TPS51216
QFN (20) PINS
°C/W
TPS51216
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RECOMMENDED OPERATING CONDITIONS

Supply voltage V5IN 4.5 5.5 V
VBST –0.1 33.5
(1)
VBST SW -3 28
(2)
Input voltage range V
Output voltage range VTTREF, VREF –0.1 3.5 V
T
A
(1) Voltage values are with respect to the SW terminal. (2) This voltage should be applied for less than 30% of the repetitive period.
SW VLDOIN, VDDQSNS, REFIN –0.1 3.5 VTTSNS –0.1 3.5 PGND, VTTGND –0.1 0.1 S3, S5, TRIP, MODE –0.1 5.5 DRVH –3 33.5
(1)
DRVH
(2)
DRVH
VTT –0.1 3.5 DRVL –0.1 5.5 PGOOD –0.1 5.5 Operating free-air temperature –40 85 °C
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
MIN TYP MAX UNIT
–0.1 5.5
–4.5 28
–0.1 5.5 –4.5 33.5
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

ELECTRICAL CHARACTERISTICS

over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, V otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
I
V5IN(S0)
I
V5IN(S3)
I
V5INSDN
I
VLDOIN(S0)
I
VLDOIN(S3)
I
VLDOINSDN
VREF OUTPUT
V
VREF
I
VREFOCL
VTTREF OUTPUT
V
VTTREF
V
VTTREF
I
VTTREFOCLSRC
I
VTTREFOCLSNK
I
VTTREFDIS
VTT OUTPUT
V
VTT
V
VTTTOL
I
VTTOCLSRC
I
VTTOCLSNK
I
VTTLK
I
VTTSNSBIAS
I
VTTSNSLK
I
VTTDIS
VDDQ OUTPUT
V
VDDQSNS
V
VDDQSNSTOL
I
VDDQSNS
I
REFIN
I
VDDQDIS
I
VLDOINDIS
SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY
f
SW
t
ON(min)
t
OFF(min)
(1) Ensured by design. Not production tested.
V5IN supply current, in S0 TA= 25°C, No load, VS3= VS5= 5 V 590 μA V5IN supply current, in S3 TA= 25°C, No load, VS3= 0 V, VS5= 5 V 500 μA V5IN shutdown current TA= 25°C, No load, VS3= VS5= 0 V 1 μA VLDOIN supply current, in S0 TA= 25°C, No load, VS3= VS5= 5 V 5 μA VLDOIN supply current, in S3 TA= 25°C, No load, VS3= 0 V, VS5= 5 V 5 μA VLDOIN shutdown current TA= 25°C, No load, VS3= VS5= 0 V 5 μA
I
= 30 μA, TA= 25°C 1.8000
VREF
Output voltage 0 μA I
0 μA I
Current limit V
VREF
<300 μA, TA= –10°C to 85°C 1.7856 1.8144 V
VREF
<300 μA, TA= –40°C to 85°C 1.7820 1.8180
VREF
= 1.7 V 0.4 0.8 mA
Output voltage V
|I
| <100 μA, 1.2 V V
Output voltage tolerance to V
VDDQ
Source current limit V Sink current limit V
VTTREF
|I
| <10 mA, 1.2 V V
VTTREF VDDQSNS VDDQSNS
= 1.8 V, V = 1.8 V, V
= 0 V 10 18 mA
VTTREF VTTREF
VTTREF discharge current TA= 25°C, VS3= VS5= 0 V, V
1.8 V 49.2% 50.8%
VDDQSNS
1.8 V 49% 51%
VDDQSNS
= 1.8 V 10 17 mA
= 0.5 V 0.8 1.3 mA
VTTREF
Output voltage V
|I
| 10 mA, 1.2 V V
VTT
|I
| 1 A, 1.2 V
Output voltage tolerance to VTTREF mV
Source current limit 2 3 Sink current limit V
VTT
|I
| 2 A, 1.4 V V
VTT
|I
| 1.5 A, 1.2 V V
VTT
V
VDDQSNS
I
= 0 A
VTTREF
VDDQSNS
= 1.8 V, V
= 1.8V, V
VDDQSNS
VDDQSNS
VDDQSNS
VTT
= V
VTT
Leakage current TA= 25°C , VS3= 0 V, VS5= 5 V, V VTTSNS input bias current VS3= 5 V, VS5= 5 V, V VTTSNS leakage current VS3= 0 V, VS5= 5 V, V
VTT Discharge current 7.8 mA
TA= 25°C, VS3= VS5= 0 V, V V
= 0.5 V, I
VTT
VTTREF
VTTSNS VTTSNS
= 0 A
VDDQSNS
1.8 V, I
= V
VTTSNS
VTTSNS
1.8 V, I
1.8 V, I
1.4 V, I
= 0.7 V,
= 1.1 V, I
VTT
= V
VTTREF
= V
VTTREF
VDDQSNS
= 0 A –20 20
VTTREF
= 0 A –30 30
VTTREF
= 0 A –40 40
VTTREF
= 0 A –40 40
VTTREF
= 0 A 2 3
VTTREF
= V
VTTREF
–0.5 0.0 0.5 μA
= 1.8 V,
VDDQ sense voltage V VDDQSNS regulation voltage
tolerance to REFIN VDDQSNS input current V REFIN input current V
VDDQ discharge current 12 mA
VLDOIN discharge current 1.2 A
VDDQ switching frequency kHz
Minimum on time DRVH rising to falling
TA= 25°C –3 3 mV
= 1.8 V 39 μA
VDDQSNS
= 1.8 V –0.1 0.0 0.1 μA
REFIN
VS3= VS5= 0 V, V down to GND through 47kΩ (Non-tracking)
VS3= VS5= 0 V, V down to GND through 100kΩ (Non-tracking)
VIN= 12 V, V VIN= 12 V, V
VDDQSNS VDDQSNS
= 0.5 V, MODE pin pulled
VDDQSNS
= 0.5 V, MODE pin pulled
VDDQSNS
= 1.8 V, R = 1.8 V, R
(1)
MODE MODE
= 100 kΩ 300 = 200 kΩ 400
Minimum off time DRVH falling to rising 200 320 450
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=0V, VS3=VS5=5V (unless
MODE
/2 V
VDDQSNS
VTTREF
–1 0 1
REFIN
60
V
A
5
ns
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SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, V otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VDDQ MOSFET DRIVER
R
R
t
DEAD
DRVH
DRVL
DRVH resistance
DRVL resistance
Dead time ns
INTERNAL BOOT STRAP SW
V
FBST
I
VBSTLK
Forward Voltage V VBST leakage current TA= 25°C, V
LOGIC THRESHOLD
I
MODE
V
THMODE
V
IL
V
IH
V
IHYST
V
ILK
MODE source current 14 15 16 μA
MODE threshold voltage mV
S3/S5 low-level voltage 0.5 S3/S5 high-level voltage 1.8 V S3/S5 hysteresis voltage 0.25 S3/S5 input leak current –1 0 1 μA
SOFT START
t
SS
VDDQ soft-start time 1.1 ms
PGOOD COMPARATOR
V
THPG
I
PG
t
PGDLY
t
PGSSDLY
VDDQ PGOOD threshold
PGOOD sink current V
PGOOD delay time
PGOOD start-up delay C
Source, I Sink, I Source, I Sink, I DRVH-off to DRVL-on 10 DRVL-off to DRVH-on 20
V5IN-VBST
MODE 0 580 600 620 MODE 1 829 854 879 MODE 2 1202 1232 1262 MODE 3 1760 1800 1840
Internal soft-start time, C S5 rising to V
PGOOD in from higher 106% 108% 110% PGOOD in from lower 90% 92% 94% PGOOD out to higher 114% 116% 118% PGOOD out to lower 82% 84% 86%
PGOOD
Delay for PGOOD in 0.8 1 1.2 ms Delay for PGOOD out, with 100 mV over drive 330 ns
VREF
= –50 mA 1.6 3.0
DRVH
= 50 mA 0.6 1.5
DRVH
= –50 mA 0.9 2.0
DRVL
= 50 mA 0.5 1.2
DRVL
, TA= 25°C, IF= 10 mA 0.1 0.2 V
= 33 V, VSW= 28 V 0.01 1.5 μA
VBST
= 0.1 μF,
VREF
> 0.99 × V
VDDQSNS
REFIN
= 0.5 V 3 5.9 mA
= 0.1 μF, S5 rising to PGOOD rising 2.5 ms
TPS51216
=0V, VS3=VS5=5V (unless
MODE
Ω
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
ELECTRICAL CHARACTERISTICS (continued)
over operating free-air temperature range, VV5IN=5V, VLDOIN is connected to VDDQ output, V otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
PROTECTIONS
I
TRIP
TC
ITRIP
V
TRIP
V
OCL
V
OCLN
V
ZC
V
UVLO
V
OVP
t
OVPDLY
V
UVP
t
UVPDLY
t
UVPENDLY
V
OOB
THERMAL SHUTDOWN
T
SDN
TRIP source current TA= 25°C, V TRIP source current temperature
coefficient V
Current limit threshold V
Negative current limit threshold V
(2)
voltage range 0.2 3 V
TRIP
V
= 3.0 V 360 375 390
TRIP
= 1.6 V 190 200 210 mV
TRIP
V
= 0.2 V 20 25 30
TRIP
V
= 3.0 V –390 –375 –360
TRIP
= 1.6 V –210 –200 –190 mV
TRIP
V
= 0.2 V –30 –25 –20
TRIP
= 0.4 V 9 10 11 μA
TRIP
Zero cross detection offset 0 mV
V5IN UVLO threshold voltage V
Wake-up 4.2 4.4 4.5
Shutdown 3.7 3.9 4.1 VDDQ OVP threshold voltage OVP detect voltage 118% 120% 122% VDDQ OVP propagation delay With 100 mV over drive 430 ns VDDQ UVP threshold voltage UVP detect voltage 66% 68% 70% VDDQ UVP delay 1 ms VDDQ UVP enable delay 1.2 ms OOB Threshold voltage 108%
Thermal shutdown threshold °C
Shutdown temperature
Hysteresis
(2)
(2)
=0V, VS3=VS5=5V (unless
MODE
4700 ppm/°C
140
10
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(2) Ensured by design. Not production tested.
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1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
17
1819
20
TPS51216
PowerPAD™
VTTSNS
VLDOIN
VTT
VTTGND
VTTREF
VREF
GND
REFIN
VDDQSNS
PGND
DRVL
V5IN
SW
DRVH
VBST
S5
S3
TRIP
MODE
PGOOD
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

DEVICE INFORMATION

RUK PACKAGE (TOP VIEW)
PIN FUNCTIONS
PIN
NAME NO.
DRVH 14 O High-side MOSFET gate driver output. DRVL 11 O Low-side MOSFET gate driver output. GND 7 Signal ground. MODE 19 I Connect resistor to GND to configure switching frequency and discharge mode. (See Table 2) PGND 10 Gate driver power ground. R PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
REFIN 8 I SW 13 I/O High-side MOSFET gate driver return. R
S3 17 I S3 signal input. (See Table 1) S5 16 I S5 signal input. (See Table 1) TRIP 18 I Connect resistor to GND to set OCL at V VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin. VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF. VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application. VREF 6 O 1.8-V reference output. VTT 3 O VTT 2-A LDO output. Need to connect 10μF or larger capacitance for stability. VTTGND 4 Power ground for VTT LDO. VTTREF 5 O Buffered VTT reference output. Need to connect 0.22μF or larger capacitance for stability. VTTSNS 1 I VTT output voltage feedback. V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers. Thermal
pad
I/O DESCRIPTION
current sensing input(+).
DS(on)
Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for stable operation.
current sensing input(–).
DS(on)
/8. Output 10-μA current at room temperature, TC= 4700 ppm/°C.
TRIP
Connect to GND
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1013PGND
SW
TPS51216
OC
ZC
XCON
15
VBST
12 V5IN
PWM
9
REFIN
TRIP
Delay
20 PGOOD
Control Logic
UDG-10135
10 mA
+
+
V
REFIN
+20%
+
+
8
VDDQSNS
+ +
18
14 DRVH
11 DRVL
t
ON
One­Shot
UV
OV
V
REFIN
–32%
16S5
Soft-Start
+
NOC
+
8 R
6VREF Reference
R
7GND
17S3
5VTTREF
1VTTSNS
4 VTTGND
3 VTT
+
+
+
+
2 VLDOIN
7 R
R
VTT Discharge
VTTREF Discharge
On-Time
Discharge Type
Selection
15 mA
19 MODE
V
REFIN
+8/16 %
V
REFIN
–8/16 %
+
+
VDDQ Discharge
V5OK
+
4.4 V/3.9 V
UVP
OVP
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

FUNCTIONAL BLOCK DIAGRAM

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50
60
70
80
90
100
110
120
130
140
150
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
OVP/UVP Threshold (%)
OVP UVP
0
3
6
9
12
15
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
VDDQSNS Discharge Current (mA)
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
VLDOIN Suppy Current (µA)
4
6
8
10
12
14
16
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
TRIP Source Current (µA)
0
200
400
600
800
1000
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
V5IN Suppy Current (µA)
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
V5IN Shutdown Current (µA)
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Figure 1. V5IN Supply Current vs Junction Temperature Figure 2. V5IN Shutdown Current vs Junction Temperature
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013

TYPICAL CHARACTERISTICS

Figure 3. VLDOIN Supply Current vs Junction Temperature Figure 4. Current Sense Current vs Junction Temperature
Copyright © 2010–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
Figure 5. OVP/UVP Threshold vs Junction Temperature Figure 6. VDDQSNS Discharge Current vs Junction
Temperature
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0
100
200
300
400
500
600
700
800
0 2 4 6 8 10 12 14 16 18 20
VDDQ Output Current (A)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 200 k
VIN = 12 V
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
0 2 4 6 8 10 12 14 16 18 20
VDDQ Output Current (A)
VDDQ Output Voltage (V)
R
MODE
= 200 k
VIN = 12 V
200
300
400
500
600
700
800
6 8 10 12 14 16 18 20 22
Input Voltage (V)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 200 k
I
VDDQ
= 10 A
0
100
200
300
400
500
600
700
800
0 2 4 6 8 10 12 14 16 18 20
VDDQ Output Current (A)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 100 k
VIN = 12 V
0
2
4
6
8
10
−50 −25 0 25 50 75 100 125 Junction Temperature (°C)
VTT Discharge Current (mA)
200
300
400
500
600
700
800
6 8 10 12 14 16 18 20 22
Input Voltage (V)
Switching Frequency (kHz)
V
VDDQ
= 1.20 V
V
VDDQ
= 1.35 V
V
VDDQ
= 1.50 V
R
MODE
= 100 k
I
VDDQ
= 10 A
TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
Figure 7. VTT Discharge Current vs Junction Temperature Figure 8. Switching Frequency vs Input Voltage
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Figure 9. Switching Frequency vs Input Voltage Figure 10. Switching Frequency vs Load Current
Figure 11. Switching Frequency vs Load Current Figure 12. Load Regulation
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0.710
0.720
0.730
0.740
0.750
0.760
0.770
0.780
0.790
−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 VTT Current (V)
VTT Voltage (V)
V
VDDQ
= 1.5 V
0.635
0.645
0.655
0.665
0.675
0.685
0.695
0.705
0.715
−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 VTT Current (V)
VTT Voltage (V)
V
VDDQ
= 1.35 V
0.650
0.655
0.660
0.665
0.670
0.675
0.680
0.685
0.690
0.695
−10 −5 0 5 10 VTTREF Current (mA)
VTTREF Voltage (V)
V
VDDQ
= 1.35 V
0.580
0.585
0.590
0.595
0.600
0.605
0.610
0.615
0.620
−10 −5 0 5 10 VTTREF Current (mA)
VTTREF Voltage (V)
V
VDDQ
= 1.2 V
1.45
1.46
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
1.55
6 8 10 12 14 16 18 20 22
Input Voltage (V)
VDDQ Output Voltage (V)
I
VDDQ
= 0 A
I
VDDQ
= 20 A
R
MODE
= 200 k
0.730
0.735
0.740
0.745
0.750
0.755
0.760
0.765
0.770
−10 −5 0 5 10 VTTREF Current (mA)
VTTREF Voltage (V)
V
VDDQ
= 1.5 V
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TPS51216
SLUSAB9A –NOVEMBER 2010–REVISED APRIL 2013
TYPICAL CHARACTERISTICS (continued)
Figure 13. Line Regulation Figure 14. VTTREF Load Regulation
Figure 15. VTTREF Load Regulation Figure 16. VTTREF Load Regulation
Figure 17. VTT Load Regulation Figure 18. VTT Load Regulation
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