Texas Instruments CY74FCT273TSOCT, CY74FCT273TSOC, CY74FCT273TQCT, CY74FCT273TQC, CY74FCT273CTSOCT Datasheet

8-Bit Register

CY54/74FCT273T

SCCS020 - March 1995 - Revised February 2000

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments Incorporated

Features

• Function, pinout, and drive compatible with FCT and
F logic

• FCT-C speed at 5.8 ns max. (Com’l)
FCT-A speed at 7.2 ns max. (Com’l)

• Reduced V

OH

(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for significantly improved
noise characteristics

• Power-off disable feature

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Extended commercial range of −40˚C to +85˚C

• Sink current 64 mA (Com’l), 32 mA (Mil)
Source current 32 mA (Com’l), 12 mA (Mil)

Functional Description

The FCT273T consists of eight edge-triggered D-type
flip-flops with individual D inputs and Q outputs. The common
buffered clock (CP) and master reset (MR) load and reset all
flip-flops simultaneously. The FCT273T is an edge-triggered
register.The state of each D input (one set-up time before the
LOW-to-HIGH clock transition) is transferred to the corre­sponding flip-flop’sQ output. All outputs will be forcedLOWby
a low voltage level on the

MR input.

The outputs are designed with a power-off disable feature to
allow for liv e insertion of boards.

Note:

1. H = HIGH Voltage Level steady state
h = HIGH Voltage Level one set-up time prior to LOW-to-HIGH clock transition
L = LOW Voltage Level steady state
l = LOW Voltage Level one set-up time prior to the LOW-to-HIGH transition
X = Don’t Care

= LOW-to-HIGH clock transition

Logic Block Diagram

PinConfigurations

FCT273T–1

CP

D Q

D

0

Q

0

R

D

CP

D Q

D

1

Q

1

R

D

CP

D Q

D

2

Q

2

R

D

CP

D Q

D

3

Q

3

R

D

CP

D Q

D

4

Q

4

R

D

CP

D Q

D

5

Q

5

R

D

CP

D Q

D

6

Q

6

R

D

CP

D Q

D

7

Q

7

R

D

CP

MR

FCT273T–2

4

8
9
10
11
12

765

1516 17 18

3
2
1

20

13

14

19

D3D2Q

1

D

6

D

5

D

7

CP

V

CC

GND

Q

5

Top View

D

1

LCC

MR

Q

0

D

0

Q

3

D

4

Q

4

1
2
3
4
5
6
7
8
9
10

11

12

16

17

18

19

20

13

14

V

CC

FCT273T–3

15

Top View

Q

6

Q

2

Q

7

Q

0

D

0

D

1

Q

1

Q

2

D

2

D

3

Q

3

D

7

D

6

Q

6

Q

5

D

5

D

4

Q

4

CP

MR

GND

Q

7

DIP/SOIC/QSOP

FCT273T–4

CP
MR

D

0

Q

0

D

1

Q

1

D

2

Q

2

D

3

Q

3

D

4

Q

4

D

5

Q

5

D

6

Q

6

D

7

Q

7

Logic Symbol

Function Table

[1]

Operating Mode

Inputs Output

MR CP D Q

Reset (clear) L X X L
Load ‘1’ H h H
Load ‘0’ H l L

CY54/74FCT273T

2

Maximum Ratings

[2, 3]

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .....................................−65°C to +150°C

Ambient Temperature with

Power Applied..................................................−65°C to +135°C

Supply Voltage to Ground Potential..................−0.5V to +7.0V

DC Input Voltage .................................................−0.5V to +7.0V

DC Output Voltage..............................................−0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin).......120 mA

Power Dissipation..........................................................0.5W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Operating Range

Range Range

Ambient

Temperature V

CC

Commercial All –40°C to +85°C 5V ± 5%
Military

[4]

All –55°C to +125°C 5V ± 10%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ.

[5]

Max. Unit

V

OH

Output HIGH Voltage VCC=Min., IOH=–32 mA Com’l 2.0 V

VCC=Min., IOH=–15 mA Com’l 2.4 3.3 V
VCC=Min., IOH=–12 mA Mil 2.4 3.3 V

V

OL

Output LOW Voltage VCC=Min., IOL=64 mA Com’l 0.3 0.55 V

VCC=Min., IOL=32mA Mil 0.3 0.55 V

V

IH

Input HIGH Voltage 2.0 V

V

IL

Input LOW Voltage 0.8 V

V

H

Hysteresis

[6]

All inputs 0.2 V

V

IK

Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V

I

I

Input HIGH Current VCC=Max., VIN=V

CC

5 µA

I

IH

Input HIGH Current VCC=Max., VIN=2.7V ±1 µA

I

IL

Input LOW Current VCC=Max., VIN=0.5V ±1 µA

I

OS

Output Short Circuit Current

[7]

VCC=Max., V

OUT

=0.0V –60 –120 –225 mA

I

OFF

Power-Off Disable VCC=0V, V

OUT

=4.5V ±1 µA

Capacitance

[6]

Parameter Description Typ.

[5]

Max. Unit

C

IN

Input Capacitance 5 10 pF

C

OUT

Output Capacitance 9 12 pF

Notes:

2. Unless otherwise noted, these limits are over the operating free-air temperature range.

3. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V

CC

or ground.

4. T

A

is the “instant on” case temperature

5. Typical values are at V

CC

=5.0V, TA=+25˚C ambient.

6. This parameter is specified but not tested.

7. Not more than one output should beshorted at a time.Duration of short should not exceedone second. The use of high-speed testapparatus and/or sample
and hold techniquesare preferable in order tominimize internal chip heating and more accuratelyreflect operational values. Otherwiseprolongedshorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, I

OS

tests should be performed last.

CY54/74FCT273T

3

Power Supply Characteristics

Parameter Description Test Conditions Typ.

[5]

Max. Unit

I

CC

Quiescent Power Supply Current VCC=Max., VIN ≤ 0.2V, VIN≥ VCC-0.2V 0.1 0.2 mA

∆I

CC

Quiescent Power Supply Current
(TTL inputs HIGH)

VCC=Max., VIN=3.4V, f1=0, Outputs Open

[8]

0.5 2.0 mA

I

CCD

Dynamic Power Supply Current

[9]

VCC=Max., One Bit Toggling, 50% Duty Cycle,
Outputs Open,

MR=VCC,

V

IN

≤ 0.2V or VIN≥ VCC-0.2V

0.06 0.12 mA/MHz

I

C

Total Power Supply Current

[10]

VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f

1

=5 MHz,

MR=VCC, VIN≤ 0.2V or VIN≥ VCC-0.2V

0.7 1.4 mA

VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, One Bit Toggling at f

1

=5 MHz,

MR=VCC, VIN=3.4V or VIN=GND

1.2 3.4 mA

VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f

1

=2.5MHz, MR=VCC,

V

IN

≤ 0.2V or VIN≥ VCC-0.2V

1.6 3.2

[11]

mA

VCC=Max., f0=10 MHz, 50% Duty Cycle,
Outputs Open, Eight Bits Toggling
at f

1

=2.5 MHz, MR=VCC,

V

IN

=3.4V or VIN=GND

3.9 12.2

[11]

mA

Notes:

8. Per TTL driven input (V

IN

=3.4V); all other inputs at VCC or GND.

9. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

10. I

C=IQUIESCENT

+ I

INPUTS

+ I

DYNAMIC

IC=ICC+∆ICCDHNT+I

CCD(f0

/2 + f1N1)

I

CC

= Quiescent Current with CMOS input levels

∆I

CC

= Power Supply Current for a TTL HIGH input (VIN=3.4V)

D

H

= Duty Cycle for TTL inputs HIGH

N

T

= Number of TTL inputs at D

H

I

CCD

= Dynamic Current caused by an input transition pair (HLH or LHL)

f

0

= Clock frequency for registered devices, otherwise zero

f

1

= Input signal frequency

N

1

= Number of inputs changing at f

1

All currents are in milliamps and all frequencies are in megahertz.

11. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.