Texas Instruments CY74FCT2646ATQC, CY74FCT2646CTQCT, CY74FCT2646CTQC, CY74FCT2646ATQCT Datasheet

8-Bit Registered Transceive

r

CY74FCT2646T

SCCS043 - September 1994 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments Incorporated

Features

• Function and pinout compatible with FCT and F logic

• FCT-C speed at 5.4 ns max.
FCT-A speed at 6.3 ns max.

• Reduced V

OH

(typically = 3.3V) versions of equivalent

FCT functions

• 25Ωoutputseriesresistorstoreducetransmissionline
reflection noise

• Reduced V

OH

(typically=3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for significantly improved
noise characteristics

• Power-off disable feature permits live insertion

• Matched rise and fall times

• ESD > 2000V

• Fully compatible with TTL input and output logic levels

• Sink current 12 mA
Source current 15 mA

• Independent register for A and B buses

• Extended commercial temp. range of –40˚C to +85˚C

• Three-state output

Functional Description

The FCT2646T consists of a bus transceiver circuit with
three-state, D-type flip-flops, and control circuitry arranged for
multiplexedtransmission of data directly from the input bus or
from the internal registers. Data on the A or B bus will be
clocked into the registers as the appropriate clock pin goes to
a HIGH logic level. Enable Control

G and direction pins are
provided to control the transceiver function. On-chip termina­tionresistorshavebeenadded to the outputs toreduce system
noisecaused by reflections sothat the FCT2646Tcan be used
to replace the FCT646T in an existing design.

In the transceiver mode, data present at the high impedance
port may be stored in either the A or B register, or in both.
Select controls can multiplexstored and real-time (transparent
mode) data. The direction control determines which bus will
receive data when the enable control

G is Active LOW. In the

isolation mode (enable control

G HIGH), A data may be stored

in the B register and/or B data may be stored in the A register.
The outputs are designed with a power-off disable feature to

allow for liv e insertion of boards.

LogicBlock Diagram

P

i

n

C

onfigurations

FCT2646T

–1

C

D

B

1

C

D

A

1

TO 7 OTHERCHANNELS

SAB

CPAB

CPBA

DIR

SBA

G

Functional Block Diagram

1
2
3
4
5
6
7
8
9
10
11
12

16

17

18

19

20

24

23

22

21

13

14

V

CC

FCT2646T–3

15

QSOP

Top View

CPAB

A

1

A

2

A

3

A

4

A

5

A

6

A

7

A

8

B

1

B

2

B

3

B

4

B

5

B

6

B

7

B

8

CPBA

SAB

SBA

DIR

G

GND

FCT2646T–4

CPAB

A

1A2A3A4A5A6A7A8

B1B2B3B4B5B6B7B

8

CPBA

SAB

SBA

DIR

G

CY74FCT2646T

2

Pin Description

Name Description

A Data Register A Inputs, Data Register B Outputs
B Data Register B Inputs, Data Register A Outputs
CPAB, CPBA Clock Pulse Inputs
SAB, SBA Output Data Source Select Inputs
DIR, G Output Enable Inputs

Note:

1. Cannot transfer data to A bus and B bus simultaneously.

BUS BBUS A

DIR

L

GLCPAB

X

CPBAXSABXSBA

X

BUS BBUS A

DIR

H
L
X

G

L
L

H

CPAB

X

CPBAXSAB

X
X
X

SBA

X
X
X

BUS

BBUS A

DIR

H

GLCPAB

X

CPBAXSABLSBA

X

BUS ABUS A

DIR

L

H

G

L
L

CPAB

X

HorL

CPBA
HorL

X

SAB

X
H

SBA

H
X

Real-TimeTransfer

Bus B to Bus A

Real-TimeTransfer

Bus A to Bus B

Storage from

A and/or B

Transfer Stored Data

to A and/or B

[1]

CY74FCT2646T

3

Maximum Ratings

[4, 5]

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature .................................–65°C to +150°C

Ambient Temperature with

Power Applied.............................................–65°C to +135°C

Supply Voltage to Ground Potential............... –0.5V to +7.0V

DC Input Voltage............................................–0.5V to +7.0V

DC Output Voltage......................................... –0.5V to +7.0V

DC Output Current (Maximum Sink Current/Pin) ......120 mA

Power Dissipation..........................................................0.5W

Static Discharge Voltage............................................>2001V

(per MIL-STD-883, Method 3015)

Function Table

[2]

Inputs Data I/O

[3]

Operation or Function

G DIR CPAB CPBA SAB SBA A1 thru A

8

B1 thru B

8

FCT2646T

H
H

X
X

H or L H or L X

X

X
X

Input Input Isolation

Store A and B Data

L
L

L
L

X
X

X

H or L

X
X

L
H

Output Input Real Time B Data to A Bus

Stored B Data to A Bus

L
L

H
H

X

H or L

X
X

L
H

X
X

Input Output Real Time A Data to B Bus

Stored A Data to B Bus

Operating Range

Range

Ambient

Temperature V

CC

Commercial –40°C to +85°C 5V ± 5%

Electrical Characteristics Over the Operating Range

Parameter Description Test Conditions Min. Typ

[6]

Max. Unit

V

OH

Output HIGH Voltage VCC=Min., IOH=–15 mA 2.4 3.3 V

V

OL

Output LOW Voltage VCC=Min., IOL=12 mA 0.3 0.55 V

R

OUT

Output Resistance VCC=Min., IOL=12 mA 20 25 40 Ω

V

IH

Input HIGH Voltage 2.0 V

V

IL

Input LOW Voltage 0.8 V

V

H

Hysteresis

[7]

All inputs 0.2 V

V

IK

Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V

I

IH

Input HIGH Current VCC=Max., VIN=V

CC

5 µA

I

IH

Input HIGH Current VCC=Max., VIN=2.7V ±1 µA

I

IL

Input LOW Current VCC=Max., VIN=0.5V ±1 µA

I

OS

Output Short Circuit Current

[8]

VCC=Max., V

OUT

=0.0V –60 –120 –225 mA

I

OFF

Power-Off Disable VCC=0V, V

OUT

=4.5V ±1 µA

Notes:

2. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care.

3. The data output functions may be enabled or disabled by various signals at the G or DIR inputs. Data input functions are always enabled,i.e.,data at the bus
pins will be stored on every LOW-to-HIGH transition of the clock inputs.

4. Unless otherwise noted, these limits are over the operating free-air temperature range.

5. Unused inputs must always be connected to an appropriate logic voltage level, preferably either V

CC

or ground.

6. Typical values are at VCC=5.0V, TA=+25˚C ambient.

7. This parameter is specified but not tested.

8. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting
ofahigh output may raise thechiptemperature well abovenormal andthereby cause invalid readingsin other parametric tests. In anysequenceof parameter
tests, IOS tests should be performed last.