Texas Instruments CY74FCT163H952CPVC, CY74FCT163H952CPAC, CY74FCT163952CPVCT, CY74FCT163952CPVC, CY74FCT163952CPACT Datasheet

16-Bit Registered Transceivers

CY74FCT163952

CY74FCT163H952

SCCS048 - March 1997 - Revised March 2000

Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.

Copyright © 2000, Texas Instruments Incorporated

1CY74FCT163952

Features

• Low power, pin-compatible replacement for LCX and
LPT families

• 5V tolerant inputs and outputs

• 24 mA balanced drive outputs

• Power-off disable outputs permits live insertion

• Edge-rate control circuitry for reduced noise

• FCT-C speed at 4.4 ns

• Latch-up performance exceedsJEDEC standard no. 17

• Typical output skew < 250 ps

• Industrial temperature range of –40˚C to +85˚C

• TSSOP (19.6-mil pitch) or SSOP (25-mil pitch)

• Typical

V

olp

(groundbounce)performanceexceedsMil

Std 883D

•V

CC

= 2.7V to 3.6V

• ESD (HBM) > 2000V

CY74FCT163H952

• Bus hold on data inputs

• Eliminates the need for external pull-up or pull-down
resistors

• Devices with bus hold are not recommended for trans­lating rail-to-rail CMOS signals to 3.3V logic levels

Functional Description

These 16-bit registered transceivers are high-speed,
low-powerdevices. 16-bit operation is achievedby connecting
the control lines of the two 8-bit registered transceivers
together. For data flow from bus A-to-B,

CEAB must be LOW
to allow data to be stored when CLKAB transitions from
LOW-to-HIGH. The stored data will be present on the output
when

OEAB is LOW.Control of data from B-to-A is similar and

is controlled by using the

CEBA, CLKBA, and OEBA inputs.
The outputs are 24-mA balanced output drivers with current
limiting resistors to reduce the need for external terminating
resistors and provide for minimal undershoot and reduced
ground bounce.

The CY74FCT163H952 has “bus hold” on the data inputs,
whichretains the input’s laststate whenever the sourcedriving
the input goes to high impedance. This eliminates the need for
pull-up/down resistors and prevents floating inputs.

The CY74FCT163952 is designed with inputs and outputs
capable of being driven by 5.0V buses, allowing its use in
mixed voltage systems as a translator. The outputs are also
designed with a power off disable feature enabling its use in
applications requiring live insertion.

Logic Block Diagrams; CY74FCT163952, CY74FCT163H952

Pin Configuration

1

OEAB

SSOP/TSSOP

Top View

1

CLKBA

1B1
1B2

GND

V

CC

GND

GND

1B1

TO7 OTHERCHANNELS

1
2

3
4

5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55

54
53

52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

1

CEBA

1

OEAB

1

CEAB

1

CLKAB

1

OEBA

1A1

D

C

CE

D

C
CE

1

CEAB

1

CLKAB

GND

1A1
1A2

1A3
1A4

GND

2A1
2A2
2A3

2A4

V

CC

1A5

1A6
1A7
1A8

GND

2A5

2A6

2A7
2A8

2

CLKAB

GND

2

OEAB

2

CEAB

V

CC

1

OEBA

1

CEBA

1

CLKBA

GND

2

CLKBA

2

OEBA

2

CEBA

1B3

1B6
1B7
1B8

1B4
1B5

2B1

2B3

2B4

2B2

2B5
2B6

2B7
2B8

V

CC

2

CLKBA

2B1

2

OEAB

2

CEAB

2

CLKAB

2

OEBA

2A1

D

C

CE

D

C
CE

2

CEBA

TO7 OTHERCHANNELS

CY74FCT163952

CY74FCT163H952

2

Maximum Ratings

[5, 6]

(Above which the useful life may be impaired. For user guide­lines, not tested.)

Storage Temperature ..................................–55°C to +125°C

Ambient Temperature with

Power Applied.............................................–55°C to +125°C

Supply Voltage Range......................................0.5V to +4.6V

DC Input Voltage............................................–0.5V to +7.0V

DC Output Voltage .........................................–0.5V to +7.0V

DC Output Current

(Maximum Sink Current/Pin)........................ –60 to +120 mA

Power Dissipation..........................................................1.0W

Pin Description

Name Description

OEAB A-to-B Output Enable Input (Active LOW)
OEBA B-to-A Output Enable Input (Active LOW)
CEAB A-to-B Clock Enable Input (Active LOW)
CEBA B-to-A Clock Enable Input (Active LOW)
CLKAB A-to-B Clock Input
CLKBA B-to-A Clock Input
A A-to-B Data Inputs or B-to-A Three-State

Outputs

[1]

B B-to-A Data Inputs or A-to-B Three-State

Outputs

[1]

Function Table

[2, 3]

For A-to-B (Symmetric with B-to-A)

Inputs Outputs

CEAB CLKAB OEAB A B

H X L X B

[4]

X L L X B

[4]

L L L L
L L H H
X X H X Z

Operating Range

Range

Ambient

Temperature V

CC

Industrial –40°C to +85°C 2.7V to 3.6V

Electrical Characteristics for Non Bus Hold Devices Over the Operating Range V

CC

=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.

[7]

Max. Unit

V

IH

Input HIGH Voltage All Inputs 2.0 5.5 V

V

IL

Input LOW Voltage 0.8 V

V

H

Input Hysteresis

[8]

100 mV

V

IK

Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 –1.2 V

I

IH

Input HIGH Current VCC=Max., VI=5.5 ±1 µA

I

IL

Input LOW Current VCC=Max., VI=GND ±1 µA

I

OZH

High Impedance Output Current
(Three-State Output pins)

VCC=Max., V

OUT

=5.5V ±1 µA

I

OZL

High Impedance Output Current
(Three-State Output pins)

VCC=Max., V

OUT

=GND ±1 µA

I

OS

Short Circuit Current

[9]

VCC=Max., V

OUT

=GND –60 –135 –240 mA

I

OFF

Power-Off Disable VCC=0V, V

OUT

≤4.5V ±100 µA

I

CC

Quiescent Power Supply Current VIN≤0.2V,

V

IN>VCC

–0.2V

VCC=Max. 0.1 10 µA

∆I

CC

Quiescent Power Supply Current
(TTL inputs HIGH)

VIN=VCC–0.6V

[10]

VCC=Max. 2.0 30 µA

Notes:

1. On the CY74FCT163H952, these pins have bus hold.

2. A-to-B data flow is shown: B-to-A data flow is similar but uses,

CEBA, CLKBA, and OEBA.

3. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. = LOW-to-HIGH Transition. Z = HIGH Impedance.

4. Level of B before the indicated steady-state input conditions were established.

5. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature.

6. With the exception of inputs with bus hold, unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground,

7. Typical values are at VCC=3.3V, TA = +25˚C ambient.

8. This parameter is specified but not tested.

9. Not more than one output should be shortedat a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample
and hold techniques are preferable in order to minimize internalchip heating and more accurately reflect operational values. Otherwise prolonged shorting of
a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter
tests, IOS tests should be performed last.

10. Per TTL driven input; all other inputs at VCC or GND.

CY74FCT163952

CY74FCT163H952

3

Electrical Characteristics For Bus Hold Devices Over the Operating Range V

CC

=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.

[7]

Max. Unit

V

IH

Input HIGH Voltage All Inputs 2.0 V

CC

V

V

IL

Input LOW Voltage 0.8 V

V

H

Input Hysteresis

[8]

100 mV

V

IK

Input Clamp Diode Voltage VCC=Min., IIN=–18 mA –0.7 – 1.2 V

I

IH

Input HIGH Current VCC=Max., VI=V

CC

±100 µA

I

IL

Input LOW Current ±100 µA

I

BBH

I

BBL

Bus Hold Sustain Current on Bus Hold Input

[11]

VCC=Min. VI=2.0V –50 µA

VI=0.8V +50 µA

I

BHHO

I

BHLO

Bus Hold Overdrive Current on Bus Hold Input

[11]

VCC=Max., VI=1.5V ±500 µA

I

OZH

High Impedance Output Current
(Three-State Output pins)

VCC=Max., V

OUT=VCC

±1 µA

I

OZL

High Impedance Output Current
(Three-State Output pins)

VCC=Max., V

OUT

=GND ±1 µA

I

OS

Short Circuit Current

[9]

VCC=Max., V

OUT

=GND –60 –135 –240 mA

I

OFF

Power-Off Disable VCC=0V, V

OUT

≤4.5V ±100 µA

I

CC

Quiescent Power Supply Current VIN≤0.2V V

CC

VIN>VCC–0.2V

VCC=Max. +40 µA

∆

ICC

Quiescent Power supply Current
(TTL inputs HIGH)

VIN=VCC–0.6V

[10]

VCC=Max. +350 µA

Electrical Characteristics For Balanced Drive Devices Over the Operating Range V

CC

=2.7V to 3.6V

Parameter Description Test Conditions Min. Typ.

[7]

Max. Unit

I

ODL

Output LOW Dynamic Current

[9]

VCC=3.3V, VIN=V

IH

or VIL, V

OUT

=1.5V

50 90 200 mA

I

ODH

Output HIGH Dynamic Current

[9]

VCC=3.3V, VIN=V

IH

or VIL, V

OUT

=1.5V

–36 –60 –110 mA

V

OH

Output HIGH Voltage VCC=Min., IOH= –0.1 mA VCC–0.2 V

VCC=Min., IOH= –8 mA 2.4

[12]

3.0 V

VCC=3.0V, IOH= –24 mA 2.0 3.0 V

V

OL

Output LOW Voltage VCC=Min., IOL= 0.1mA 0.2 V

VCC=Min., IOL= 24 mA 0.3 0.55

Notes:

11. Pins with bus hold are described in Pin Description.

12. V

OH=VCC

–0.6 V at rated current

Capacitance

[8]

(TA = +25˚C, f = 1.0 MHz)

Parameter Description Test Conditions Typ.

[7]

Max. Unit

C

IN

Input Capacitance VIN = 0V 4.5 6.0 pF

C

OUT

Output Capacitance V

OUT

= 0V 5.5 8.0 pF

CY74FCT163952

CY74FCT163H952

4

Power Supply Characteristics

Parameter Description Test Conditions Typ.

[7]

Max. Unit

I

CCD

Dynamic Power Supply
Current

[13]

VCC=Max., One Input Toggling,
50% Duty Cycle,
Outputs Open,

OE=GND

VIN=VCCor
V

IN

=GND

50 75 µA/MHz

I

C

Total Power Supply
Current

[14]

VCC=Max., f1=10 MHz, 50%
DutyCycle, Outputs Open, One
Bit Toggling,

OE=GND

VIN=VCC or
V

IN

=GND

0.5 0.8 mA

VIN=VCC–0.6V or
V

IN

=GND

0.5 0.8 mA

VCC=Max., f1=2.5 MHz, 50%
Duty Cycle, Outputs Open, Six­teen Bits Toggling,

OE=GND

VIN=VCC or
V

IN

=GND

2.0 3.0

[15]

mA

VIN=VCC–0.6V or
V

IN

=GND

2.0 3.3

[15]

mA

Switching Characteristics Over the Operating Range V

CC

=3.0V to 3.6V

[16,17]

Parameter Description

CY74FCT163952A

CY74FCT163952C

CY74FCT163H952C

Min. Max. Min. Max. Unit Fig. No.

[18]

t

PLH

t

PHL

Propagation Delay Data to
Output

1.5 4.8 1.5 4.4 ns 1, 3

t

PZH

t

PZL

Output Enable Time 1.5 6.2 1.5 5.8 ns 1, 7, 8

t

PHZ

t

PLZ

Output Disable Time 1.5 5.6 1.5 5.2 ns 1, 7, 8

t

SK(O)

Output Skew

[19]

0.5 0.5 ns —

Notes:

13. This parameter is not directly testable, but is derived for use in Total Power Supply calculations.

14. I

C

=I

QUIESCENT

+ I

INPUTS

+ I

DYNAMIC

IC=ICC+∆ICCDHNT+I

CCD(f0

/2 + f1N1)

I

CC

= Quiescent Current with CMOS input levels

∆I

CC

= Power Supply Current for a TTL HIGH input (VIN=3.4V)

D

H

= Duty Cycle for TTL inputs HIGH

N

T

= Number of TTL inputs at D

H

I

CCD

= Dynamic Current caused by an input transition pair (HLH or LHL)

f

0

= Clock frequency for registered devices, otherwise zero

f

1

= Input signal frequency

N

1

= Number of inputs changing at f

1

All currents are in milliamps and all frequencies are in megahertz.

15. Values for these conditions are examples of the ICC formula. These limits are specified but not tested.

16. Minimum limits are specified but not tested on Propagation Delays.

17. For V

CC

=2.7, propagation delay, output enable and output disable times should be degraded by 20%.

18. See “Parameter Measurement Information” in the General Information section.

19. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design.

Ordering Information CY74FCT163952

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

4.1 CY74FCT163952CPACT Z48 48-Lead (240-Mil) TSSOP Industrial
CY74FCT163952CPVC/PVCT O48 48-Lead (300-Mil) SSOP

4.8 CY74FCT163952APVC/PVCT O48 48-Lead (300-Mil) SSOP Industrial

Ordering Information CY74FCT163H952

Speed

(ns) Ordering Code

Package

Name Package Type

Operating

Range

4.1 74FCT163H952CPACT Z48 48-Lead (240-Mil) TSSOP Industrial
CY74FCT163H952CPVC O48 48-Lead (300-Mil) SSOP
74FCT163H952CPVCT O48 48-Lead (300-Mil) SSOP

CY74FCT163952

CY74FCT163H952

5

Package Diagrams

56-Lead Shrunk Small Outline Package O56

56-Lead Thin Shrunk Small Outline Package Z56

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