Texas Instruments CD74HCT08M96, CD74HCT08M, CD74HCT08E, CD74HC08M96, CD74HC08M Datasheet

CD54HC08, CD54HCT08,

/
j

[ /Title
(CD54H
C08,
CD54H
CT08,
CD74H
C08,
CD74H
CT08)

Sub­ect

(High

Data sheet acquired from Harris Semiconductor
SCHS118

August 1997

Features

• Buffered Inputs

• Typical Propagation Delay: 7ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

• CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

CC

= 5V,

o

C to 125oC

CC

OH

CD74HC08, CD74HCT08

High Speed CMOS Logic

Description

The Harris CD54HC08, CD54HCT08, CD74HC08 and
CD74HCT08 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC08E -55 to 125 14 Ld PDIP E14.3
CD74HCT08E -55 to 125 14 Ld PDIP E14.3
CD74HC08M -55 to 125 14 Ld SOIC M14.15
CD74HCT08M -55 to 125 14 Ld SOIC M14.15
CD54HC08F -55 to 125 14 Ld CERDIP F14.3
CD54HCT08F -55 to 125 14 Ld CERDIP F14.3
CD54HC08W -55 to 125 Wafer
CD54HCT08W -55 to 125 Wafer

(oC) PACKAGE

PKG.

NO.

Pinout

CD54HC08H -55 to 125 Die
CD54HCT80H -55 to 125 Die

NOTE:

1. When ordering, use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.

CD54HC08, CD54HCT08, CD74HC08, CD74HCT08

(PDIP, CERDIP, SOIC)

TOP VIEW

1A
1B
1Y
2A
2B
2Y

GND

1
2
3
4
5
6
7

V

14

CC

4B

13

4A

12

4Y

11

3B

10

3A

9

3Y

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1549.1

Functional Diagram

CD54HC08, CD54HCT08, CD74HC08, CD74HCT08

1A

1B

1Y

2A

2B

2Y

GND

1

2

3

4

5

6

7

14

V

CC

13

4B

12

4A

11

4Y

10

3B

9

3A

8

3Y

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLL
LHL
HLL
HHH

NOTE: H = High Voltage Level, L = Low Voltage Level

HC Logic Symbol HCT Logic Symbol

nA

nA
nB

nY

nB

nY

2

CD54HC08, CD54HCT08, CD74HC08, CD74HCT08

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 100 N/A

CERDIP Package . . . . . . . . . . . . . . . . 130 55

SOIC Package. . . . . . . . . . . . . . . . . . . 180 N/A

Maximum Junction Temperature (Hermetic Pac kage or Die) . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC (V)

o

25

C -40oC TO 85oC -55oC TO 125oC

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

UNITSV

3

CD54HC08, CD54HCT08, CD74HC08, CD74HCT08

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

I

CC

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

0 6 - - 2 - 20 - 40 µA

GND

HCT TYPES

High Level Input

V

IH

- - 4.5 to

Voltage
Low Level Input

V

IL

- - 4.5 to

Voltage
High Level Output

Voltage

V

OH

VIH or

V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

CMOS Loads
High Level Output

-4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

0 5.5 - ±0.1 - ±1-±1µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

VCC or

GND

∆I

CC

V

CC

- 2.1

0 5.5 - - 2 - 20 - 40 µA

- 4.5 to

Input Pin: 1 Unit Load
(Note)

NOTE: For dual-supply systems theorectical worst case (V

HCT Input Loading Table

INPUT UNIT LOADS

All 0.6

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.

o

25

C -40oC TO 85oC -55oC TO 125oC

V

(V)

CC

2-- 2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Input to Output (Figure 1)

PropagationDelay,DataInputto
Output Y

t

PLH

t

PLH

, tf = 6ns

r

, t

PHLCL

, t

PHLCL

TEST

CONDITIONS

V

CC

(V)

25oC -40oC TO 85oC -55oCTO125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

= 50pF 2 - - 90 - 115 - 135 ns

4.5 - - 18 - 23 - 27 ns
6 - - 15 - 20 - 23 ns

= 15pF 5 - 7 - ----ns

4

CD54HC08, CD54HCT08, CD74HC08, CD74HCT08

Switching Specifications Input t

PARAMETER SYMBOL

Transition Times (Figure 1) t

, tf = 6ns (Continued)

r

CONDITIONS

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

TEST

V

CC

(V)

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C
Power Dissipation Capacitance

C

I

PD

- - - - 10 - 10 - 10 pF

- 5-37-----pF

(Note 3, 4)

HCT TYPES

Propagation Delay, Input to

t

PLH

, t

PHLCL

= 50pF 4.5 - - 25 - 31 - 38 ns

Output Y (Figure 2)
PropagationDelay,DataInputto

t

PLH

, t

PHLCL

= 15pF 5 - 10 - ----ns

Output Y
Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capacitance

TLH

, t

I

C

PD

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

CL= 50pF - - - 10 - 10 - 10 pF

- 5-51-----pF

(Notes 3, 4)

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = V

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

25oC -40oC TO 85oC -55oCTO125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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