Texas Instruments CD74HCT04M96, CD74HCT04M, CD74HCT04E, CD74HC04M96, CD74HC04M Datasheet

1

Data sheet acquired from Harris Semiconductor
SCHS117

Features

• Buffered Inputs

• Typical Propagation Delay: 6ns at V

CC

= 5V,

C

L

= 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

o

C to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

= 30%, NIH = 30% of V

CC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, I

l

≤ 1µA at VOL, V

OH

Description

The Harris CD54HC04, CD54HCT04, CD74HC04 and
CD74HCT04 logic gates utilize silicon gate CMOS technol­ogy to achieve operating speeds similar to LSTTL gates with
the low power consumption of standard CMOS integrated
circuits. All devices have the ability to drive 10 LSTTL loads.
The 74HCT logic family is functionally pin compatible with
the standard 74LS logic family.

Pinout

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

(PDIP, CERDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP.RANGE

(oC) PACKAGE

PKG.

NO.

CD74HC04E -55 to 125 14 Ld PDIP E14.3
CD74HCT04E -55 to 125 14 Ld PDIP E14.3
CD74HC04M -55 to 125 14 Ld SOIC M14.15
CD74HCT04M -55 to 125 14 Ld SOIC M14.15
CD54HC04F -55 to 125 14 Ld CERDIP F14.3
CD54HCT04F -55 to 125 14 Ld CERDIP F14.3
CD54HC04W -55 to 125 Wafer
CD54HCT04W -55 to 125 Wafer
CD54HC04H -55 to 125 Die
CD54HCT04H -55 to 125 Die

NOTE:

1. When ordering, use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.

1A

1Y

2A

2Y

3A

3Y

GND

V

CC

6A
6Y
5A
5Y
4A
4Y

1
2
3
4
5
6
7

14
13
12
11
10

9
8

August 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

File Number 1471.1

CD54HC04, CD54HCT04,

CD74HC04, CD74HCT04

High Speed CMOS Logic Hex Inverter

[ /Title
(CD54H
C04,
CD54H
CT04,
CD74H
C04,
CD74H
CT04)
/

Subject
(High
Speed

2

Functional Diagram

Logic Symbol

TRUTH TABLE

INPUTS

nA nY

LH

HL

NOTE: H = High Voltage Level, L = Low Voltage Level

1A

1Y

2Y

3A

3Y

GND

1

2

3

4

5

6

14

13

12

11

V

CC

5A

4Y

5Y

6Y

6A

10

8

7

9

4A

2A

nA nY

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04