Texas Instruments CD74HCT04M96, CD74HCT04M, CD74HCT04E, CD74HC04M96, CD74HC04M Datasheet

1

Data sheet acquired from Harris Semiconductor
SCHS117

Features

• Buffered Inputs

• Typical Propagation Delay: 6ns at V

CC

= 5V,

C

L

= 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

o

C to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

= 30%, NIH = 30% of V

CC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, I

l

≤ 1µA at VOL, V

OH

Description

The Harris CD54HC04, CD54HCT04, CD74HC04 and
CD74HCT04 logic gates utilize silicon gate CMOS technol­ogy to achieve operating speeds similar to LSTTL gates with
the low power consumption of standard CMOS integrated
circuits. All devices have the ability to drive 10 LSTTL loads.
The 74HCT logic family is functionally pin compatible with
the standard 74LS logic family.

Pinout

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

(PDIP, CERDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP.RANGE

(oC) PACKAGE

PKG.

NO.

CD74HC04E -55 to 125 14 Ld PDIP E14.3
CD74HCT04E -55 to 125 14 Ld PDIP E14.3
CD74HC04M -55 to 125 14 Ld SOIC M14.15
CD74HCT04M -55 to 125 14 Ld SOIC M14.15
CD54HC04F -55 to 125 14 Ld CERDIP F14.3
CD54HCT04F -55 to 125 14 Ld CERDIP F14.3
CD54HC04W -55 to 125 Wafer
CD54HCT04W -55 to 125 Wafer
CD54HC04H -55 to 125 Die
CD54HCT04H -55 to 125 Die

NOTE:

1. When ordering, use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.

1A

1Y

2A

2Y

3A

3Y

GND

V

CC

6A
6Y
5A
5Y
4A
4Y

1
2
3
4
5
6
7

14
13
12
11
10

9
8

August 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

File Number 1471.1

CD54HC04, CD54HCT04,

CD74HC04, CD74HCT04

High Speed CMOS Logic Hex Inverter

[ /Title
(CD54H
C04,
CD54H
CT04,
CD74H
C04,
CD74H
CT04)
/

Subject
(High
Speed

2

Functional Diagram

Logic Symbol

TRUTH TABLE

INPUTS

nA nY

LH

HL

NOTE: H = High Voltage Level, L = Low Voltage Level

1A

1Y

2Y

3A

3Y

GND

1

2

3

4

5

6

14

13

12

11

V

CC

5A

4Y

5Y

6Y

6A

10

8

7

9

4A

2A

nA nY

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

3

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

CC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 2) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 100 N/A

CERDIP Package . . . . . . . . . . . . . . . . 130 55

SOIC Package. . . . . . . . . . . . . . . . . . . 180 N/A

Maximum Junction Temperature (Hermetic Pac kage or Die) . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25

o

C -40oC TO +85oC -55oC TO 125oC

UNITSV

I

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input
Voltage

V

IH

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

Low Level Input
Voltage

V

IL

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

High Level Output
Voltage
CMOS Loads

V

OH

VIH or

V

IL

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output
Voltage
TTL Loads

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output
Voltage
CMOS Loads

V

OL

VIH or

V

IL

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output
Voltage
TTL Loads

---------V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage
Current

I

I

VCC or

GND

-6--±0.1 - ±1-±1µA

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

4

Quiescent Device
Current

I

CC

VCC or

GND

0 6 - - 2 - 20 - 40 µA

HCT TYPES

High Level Input
Voltage

V

IH

- - 4.5 to

5.5

2-- 2 - 2 - V

Low Level Input
Voltage

V

IL

- - 4.5 to

5.5

- - 0.8 - 0.8 - 0.8 V

High Level Output
Voltage
CMOS Loads

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output
Voltage
TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output
Voltage
CMOS Loads

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output
Voltage
TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage
Current

I

I

V

CC

and

GND

0 5.5 - ±0.1 - ±1-±1µA

Quiescent Device
Current

I

CC

VCC or

GND

0 5.5 - - 2 - 20 - 40 µA

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note)

∆I

CC

V

CC

- 2.1

- 4.5 to

5.5

- 100 360 - 450 - 490 µA

NOTE: For dual-supply systems theorectical worst case (V

I

= 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C -40oC TO +85oC -55oC TO 125oC

UNITSV

I

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

nB 1.2

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.

Switching Specifications Input t

r

, tf = 6ns

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C -40oC TO 85oC -55oCTO125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay,
Input to Output (Figure 1)

t

PLH

, t

PHLCL

= 50pF 2 - - 85 - 105 - 130 ns

4.5 - - 7 - 21 - 67 ns
6 - - 14 - 18 - 22 ns

PropagationDelay,DataInputto
Output Y

t

PLH

, t

PHLCL

= 15pF 5 - 6 - ----ns

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

5

Transition Times (Figure 1) t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 18 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C

I

- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance
(Notes 3, 4)

C

PD

- 5-21-----pF

HCT TYPES

Propagation Delay, Input to
Output (Figure 2)

t

PLH

, t

PHLCL

= 50pF 4.5 - - 19 - 24 - 29 ns

PropagationDelay,DataInputto
Output Y

t

PLH

, t

PHLCL

= 15pF 5 - 7 - ----ns

Transition Times (Figure 2) t

TLH

, t

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance C

I

- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance
(Notes 3, 4)

C

PD

- 5-24-----pF

NOTES:

3. C

PD

is used to determine the dynamic power consumption, per gate.

4. PD = V

CC

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

Switching Specifications Input t

r

, tf = 6ns (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C -40oC TO 85oC -55oCTO125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

t

PHL

t

PLH

t

THL

t

TLH

90%
50%
10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

V

CC

tr = 6ns tf = 6ns

90%

t

PHL

t

PLH

t

THL

t

TLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

tr = 6ns

t

f

= 6ns

90%

CD54HC04, CD54HCT04, CD74HC04, CD74HCT04

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