Texas Instruments CD74ACT280M96, CD74ACT280M, CD74ACT280E, CD74AC280M96, CD74AC280M Datasheet

CD74AC280,

Data sheet acquired from Harris Semiconductor
SCHS250

August 1998

Features

• Buffered Inputs

• Typical Propagation Delay

- 10ns at V

= 5V, TA = 25oC, CL = 50pF

CC

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Pinout

CD74AC280, CD74ACT280

(PDIP, SOIC)

TOP VIEW

I6

NC

∑E
∑O

GND

1
2

I7

3
4

I8

5
6
7

14

V

CC

I5

13
12

I4

11

I3

10

I2

9

I1

8

I0

CD74ACT280

9-Bit Odd/Even Parity Generator/Checker

Description

The CD74AC280 and CD74ACT280 9-bit odd/even parity
generator/checkers that utilize the Harris Advanced CMOS
Logic technology. Bothe even and odd parity outputs are
available for checking or generating parity for words up to
nine bits long. Even parity is indicated (∑Eoutput is HIGH)
when an even number of data inputs is HIGH. Odd parity is
indicated (∑O output is HIGH) when an odd number of data
inputs is HIGH. Parity checking for words larger than nine
bits can be accomplished by tying the ∑E output to any input
of an additional AC/ACT280 parity checker.

Ordering Information

PART

NUMBER

CD74AC280E 0 to 70oC, -40 to 85,

CD74ACT280E 0 to 70oC, -40 to 85,

CD74AC280M 0 to 70oC, -40 to 85,

CD74ACT280M 0 to 70oC, -40 to 85,

NOTES:

1. Whenordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is availablewhich meets all elec­trical specifications. Please contact your local sales office or Harris
customer service for ordering information.

Functional Diagram

I0

I1

I2

I3

I4

I5

I6

I7
I8

TEMP.

RANGE (oC) PACKAGE

14 Ld PDIP E14.3

-55 to 125
14 Ld PDIP E14.3

-55 to 125
14 Ld SOIC M14.15

-55 to 125
14 Ld SOIC M14.15

-55 to 125

8

9

10

11

12

13

1

2
4

5

6

GND = 7
V
NC = 3

CC

PKG.

NO.

∑ EVEN

∑ ODD

= 14

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

1

File Number 1957.1

CD74AC280, CD74ACT280

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ___

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

2

CD74AC280, CD74ACT280

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Quiescent Supply Current
MSI

AdditionalSupplyCurrent per
Input Pin TTL Inputs High

I

CC

VCC or

GND

∆I

CC

V

CC

-2.1

0 5.5 - 8 - 80 - 160 µA

- 4.5 to

- 2.4 - 2.8 - 3 mA

5.5

1 Unit Load

NOTES:

6. Testone output at a time for a1-second maximum duration. Measurement is made by forcingcurrent and measuring voltage to minimize
power dissipation.

o

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

All 1.43

NOTE: Unitload is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

3

CD74AC280, CD74ACT280

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case)

r

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL V

CC

(V)

AC TYPES

Propagation Delay,
Any Input to ∑O

t

PLH

, t

PHL

1.5 - - 239 - - 263 ns

3.3

7.5 - 26 7.3 - 29 ns

(Note 9)

5

5.4 - 19.1 5.3 - 21 ns

(Note 10)

Propagation Delay,
Any Input to ∑E

t

PLH

, t

PHL

1.5 - - 227 - - 250 ns

3.3 7.2 - 25 7 - 28 ns
5 5.2 - 18.2 5 - 20 ns

Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 115 - - 115 - pF

(Note 11)

ACT TYPES

Propagation Delay,
Any Input to ∑O

Propagation Delay,

t

PLH

t

PLH

, t

PHL

5

5.6 - 19.6 5.4 - 21.6 ns

(Note 10)

, t

PHL

5 5.6 - 19.6 5.4 - 21.6 ns

Any Input to ∑E
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 115 - - 115 - pF

(Note 11)

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per package.
AC: PD = V
ACT: PD = V

2

fi(CPD + CL)

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

UNITSMIN TYP MAX MIN TYP MAX

INPUT

LEVEL

I

n

0V

ΣO

0V

ΣE

0V

10%

OUTPUT

DUT

OUTPUT

LOAD

R

L

C

L

50pF

(NOTE)
500Ω

V

S

V

tr = 3ns

t

PHL

S

tf = 3ns

V

S

10%

t

PLH

V

S

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

CD74AC CD74ACT

t

PLH

V

S

FIGURE 1.

t

PHL

V

S

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

3V

1.5V

0.5 V

CC

FIGURE 2. PROPAGATION DELAY TIMES

4

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