Texas Instruments CD74ACT175M96, CD74ACT175M, CD74ACT175E, CD74AC175M96, CD74AC175M Datasheet

1

Data sheet acquired from Harris Semiconductor
SCHS242

Features

• Buffered Inputs

• Typical Propagation Delay

- 6.4ns at V

CC

= 5V, TA = 25oC, CL = 50pF

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Description

The CD74AC175 and CD74ACT175 are quad D flip-flops
with reset that utilize the Harris Advanced CMOS Logic tech­nology. Information at the D input is transferred to the Q and
Q outputs on the positive-going edge of the clock pulse. All
four flip-flops are controlled by a common clock (CP) and a
common reset (

MR). Resetting is accomplished by a LOW

logic level independent of the clock.

Pinout

CD74AC175, CD74ACT175

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART

NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CD74AC175E -55 to 125 16 Ld PDIP E16.3
CD74ACT175E -55 to 125 16 Ld PDIP E16.3
CD74AC175M -55 to 125 16 Ld SOIC M16.15
CD74ACT175M -55 to 125 16 Ld SOIC M16.15

NOTES:

13. Whenordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

14. W aferand diefor this part numberis availab lewhich meets all elec­trical specifications. Please contact your local sales office or Harris
customer service for ordering information.

14

15

16

9

13
12
11
10

1
2
3
4
5

7

6

8

MR

Q0
Q0
D0
D1
Q1

GND

Q1

V

CC

Q3
D3
D2
Q2
Q2
CP

Q3

September 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

CD74AC175,

CD74ACT175

Quad D Flip-Flop with Reset

File Number 1964.1

[ /Title
(CD74
AC175
,
CD74
ACT17
5
)
/

Sub-

j

ect
(Quad
D Flip­Flop
with
Reset)
/

Autho
r ()
/

Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan
ced
TTL)
/

Cre­ator ()
/

DOCI
NFO

2

Functional Diagram

TRUTH TABLE (EACH FLIP-FLOP)

INPUTS OUTPUTS

RESET

(MR)

CLOCK

CP

DATA

Dn Qn Qn

LXXLH
H↑HHL
H↑LLH
HLXQ0Q0

H = High Level (Steady State)
L = Low Level (Steady State)
X = Irrelevant
↑ = Transition from Low to High level
Q0, Q0 = Levelbefore the Indicated Steady-State Input conditions
were established.

CP

D

R

2

Q0

9

4

D0
CP

Q

Q

3

Q0

MR

1

CP

D

R

7

Q1

5

D1

Q

Q

6

Q1

CP

D

R

10

Q2

12

D2

Q

Q

11

Q2

CP

D

R

15

Q3

13

D3

Q

Q

14

Q3

GND = 8

V

CC

= 16

CD74AC175, CD74ACT175

3

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature (Plastic Package) . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

15. For up to 4 outputs per device, add ±25mA for each additional output.

16. Unless otherwise specified, all voltages are referenced to ground.

17. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSV

I

(V) IO(mA) MIN MAX MIN MAX MIN MAX

AC TYPES

High Level Input Voltage V

IH

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

Low Level Input Voltage V

IL

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

High Level Output Voltage V

OH

VIH or V

IL

-0.05 1.5 1.4 - 1.4 - 1.4 - V

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

5.5 - - 3.85 - - - V

-50

(Note 6, 7)

5.5----3.85 - V

CD74AC175, CD74ACT175

4

Low Level Output Voltage V

OL

VIH or V

IL

0.05 1.5 - 0.1 - 0.1 - 0.1 V

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

(Note 6, 7)

5.5 - - - 1.65 - - V

50

(Note 6, 7)

5.5-----1.65 V

Input Leakage Current I

I

VCC or

GND

- 5.5 - ±0.1 - ±1-±1µA

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

5.5

2-2-2-V

Low Level Input Voltage V

IL

- - 4.5 to

5.5

- 0.8 - 0.8 - 0.8 V

High Level Output Voltage V

OH

VIH or V

IL

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

5.5 - - 3.85 - - - V

-50

(Note 6, 7)

5.5----3.85 - V

Low Level Output Voltage V

OL

VIH or V

IL

0.05 4.5 - 0.1 - 0.1 - 0.1 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

(Note 6, 7)

5.5 - - - 1.65 - - V

50

(Note 6, 7)

5.5-----1.65 V

Input Leakage Current I

I

VCC or

GND

- 5.5 - ±0.1 - ±1-±1µA

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

AdditionalSupply Current per
Input Pin TTL Inputs High
1 Unit Load

∆I

CC

V

CC

-2.1

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

NOTES:

18. Testone output at a time for a1-second maximumduration. Measurement is made by forcing current and measuring voltage tominimize
power dissipation.

19. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

ACT Input Load Table

INPUT UNIT LOAD

Dn 0.58
MR 0.67
CP 0.92

NOTE: Unitload is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSV

I

(V) IO(mA) MIN MAX MIN MAX MIN MAX

CD74AC175, CD74ACT175

5

Prerequisite For Switching Function

PARAMETER SYMBOL VCC (V)

-40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX

AC TYPES

Data to CP Set-Up Time t

SU

1.5 2 - 2 - ns

3.3

(Note 8)

2-2-ns

5

(Note 9)

2-2-ns

Hold Time t

H

1.5 2 - 2 - ns

3.3 2 - 2 - ns
52-2-ns

Removal Time, MR to CP t

REM

1.5 1 - 1 - ns

3.3 1 - 1 - ns
51-1-ns

MR Pulse Width t

W

1.5 44 - 50 - ns

3.3 4.9 - 5.6 - ns
5 3.5 - 4 - ns

CP Pulse Width t

W

1.5 55 - 63 - ns

3.3 6.1 - 7 - ns
5 4.4 - 5 - ns

CP Frequency f

MAX

1.5 9 - 8 - MHz

3.3 81 - 71 - MHz
5 114 - 100 - MHz

ACT TYPES

Data to CP Set-Up Time t

SU

5

(Note 9)

2-2-ns

Hold Time t

H

52-2-ns

Removal Time, MR to CP t

REM

51-1-ns

MR Pulse Width t

W

5 3.5 - 4 - ns

Clock Pulse Width t

W

5 4.4 - 5 - ns

CP Frequency f

MAX

5 114 - 114 - MHz

NOTES:

20. 3.3V Min is at 3V.

21. 5V Min is at 4.5V.

Switching Specifications Input t

r

, tf = 3ns, CL= 50pF (Worst Case)

PARAMETER SYMBOL VCC (V)

-40

o

C TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX

AC TYPES

Propagation Delay, CP to Q,

Qt

PLH

, t

PHL

1.5 - - 139 - - 153 ns

3.3

(Note 11)

4.4 - 15.5 4.3 - 17.1 ns

5

(Note 12)

3.2 - 11.1 3.1 - 12.2 ns

CD74AC175, CD74ACT175

6

Propagation Delay, MR to Q, Qt

PLH

, t

PHL

1.5 - - 139 - - 153 ns

3.3 4.4 - 15.5 4.3 - 17.1 ns
5 3.2 - 11.1 3.1 - 12.2 ns

Input Capacitance C

I

- - -10- -10pF

Power Dissipation Capacitance C

PD

(Note 13)

- - 55 - - 55 - pF

ACT TYPES

Propagation Delay, CP to Qn t

PLH

, t

PHL

5

(Note 12)

3 - 10.5 2.9 - 11.5 ns

Propagation Delay,

MR to Qn t

PLH

, t

PHL

5 3.3 - 11.8 3.3 - 13 ns

Input Capacitance C

I

- - -10- -10pF

Power Dissipation Capacitance C

PD

(Note 13)

- - 55 - - 55 - pF

NOTES:

22. Limits tested 100%.

23. 3.3V Min is at 3.6V, Max is at 3V.

24. 5V Min is at 5.5V, Max is at 4.5V.

25. C

PD

is used to determine the dynamic power consumption per flip-flop.

PD=CPDV

CC

2

fi+ Σ (CL+VCC2fo)+VCC∆ICCwhere fi= input frequency, fo= output frequency, CL= output load capacitance, VCC=

supply voltage.

FIGURE 5. PROPAGATION DELAYS FIGURE 6. RESET OR SET PREREQUISITE AND

PROPAGATION DELAYS

FIGURE 7. FIGURE 8. PROPAGATION DELAY TIMES

Switching Specifications Input t

r

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

PARAMETER SYMBOL VCC (V)

-40

o

C TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX

INPUT LEVEL

CP

GND

V

S

t

W

t

PHL

t

PLH

V

S

V

S

V

S

V

S

INPUT LEVEL

GND

INPUT

CP

MR

V

S

t

W

t

REM

t

PHL

Q

V

S

V

S

V

S

Q

INPUT LEVEL

GND

D

CP

V

S

tSU(L)

t

H

(L)

tH(H)

t

SU

(H)

V

S

V

S

V

S

V

S

V

S

INPUT LEVEL

GND

DUT

OUTPUT

R

L

(NOTE)

OUTPUT

LOAD

500Ω

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

CD74AC CD74ACT

Input Level V

CC

3V

Input Switching Voltage, V

S

0.5 V

CC

1.5V

Output Switching Voltage, V

S

0.5 V

CC

0.5 V

CC

CD74AC175, CD74ACT175

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated