Texas Instruments CD74ACT164M96, CD74ACT164M, CD74ACT164E, CD74AC164M96, CD74AC164M Datasheet

Data sheet acquired from Harris Semiconductor

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SCHS240A

CD54/74AC164,

CD54/74ACT164

[ /Title
(CD74
AC164
,
CD74
ACT16

4)
Sub­ect (8-

Bit
Serial­In/Par­allel­Out
Shift
Regis­ter)

Autho

r ()

Key-

words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan
ced
TTL)

Cre-

ator ()

September 1998 - Revised May 2000

Features

• Buffered Inputs

• Typical Propagation Delay

- 6ns at V

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

= 5V, TA = 25oC, CL = 50pF

CC

Pinout

DS1
DS2

GND

8-Bit Serial-In/Parallel-Out Shift Register

Description

The ’AC164 and ’ACT164 are 8-bit serial-in/parallel-out shift
registers with asynchronous reset that utilize Advanced
CMOS Logic technology. Data is shifted on the positive edge
of the clock (CP). A LOW on the Master Reset (
resets the shift register and all outputs go to the LOW state
regardless of the input conditions. Two Serial Data inputs
(DS1 and DS2) are provided; either one can be used as a
Data Enable control.

Ordering Information

PART

NUMBER

CD54AC164F3A -55 to 125 14 Ld CERDIP
CD74AC164E -55 to 125 14 Ld PDIP
CD74AC164M -55 to 125 14 Ld SOIC
CD54ACT164F3A -55 to 125 14 Ld CERDIP
CD74ACT164E -55 to 125 14 Ld PDIP
CD74ACT164M -55 to 125 14 Ld SOIC

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waferanddief orthispart number is availablewhich meets all elec­trical specifications.Please contact your local TI sales office or cus­tomer service for ordering information.

CD54AC164, CD54ACT164

(CERDIP)

CD74AC164, CD74ACT164

(PDIP, SOIC)

TOP VIEW

Q0
Q1
Q2
Q3

1
2
3
4
5
6
7

14

V
Q7

13
12

Q6

11

Q5

10

Q4
MR

9
8

CP

MR) pin

TEMP.

RANGE (oC) PACKAGE

CC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

1

Functional Diagram

CD54/74AC164, CD54/74ACT164

3

DS1

DS2

1

2

Q0

4

Q1

5

Q2

6

Q3

10

Q4

11

Q5

12

Q6

13

Q7

MR
CP

98

GND = 7
V

= 14

CC

MODE SELECT - TRUTH TABLE

INPUTS OUTPUTS

OPERATING MODE

MR CP DS1 DS2 Q0 Q1 - Q7

RESET (CLEAR) L X X X L L - L

SHIFT H ↑ l l L q0 - q6

H ↑ l h L q0 - q6
H ↑ h l L q0 - q6
H ↑ h h H q0 - q6

H = HIGH voltage level steady state.
L = LOW voltage level steady state.
h = HIGH voltage level one setup time prior to the LOW-to_HIGH clock transition.
l = LOW voltage level one setup time prior to the LOW-to-HIGH clock transition.
X = Don’t care.
q = Lowercase letters indicate the state of the referenced output prior to the LOW-to-HIGH clock transition.
↑ = LOW-to-HIGH clock transition.

2

CD54/74AC164, CD54/74ACT164

I

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

UNITSV

3

CD54/74AC164, CD54/74ACT164

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

OL

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or V

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

AdditionalSupply Currentper
Input Pin TTL Inputs High

I

CC

VCC or

GND

∆I

CC

V

CC

-2.1

0 5.5 - 8 - 80 - 160 µA

- 4.5 to

- 2.4 - 2.8 - 3 mA

5.5

1 Unit Load

NOTES:

6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

DS1, DS2 0.5

MR 0.74
CP 0.71

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

4

CD54/74AC164, CD54/74ACT164

Prerequisite For Switching Function

PARAMETER SYMBOL VCC (V)

AC TYPES

Max. Clock Frequency f

MR Pulse Width t

CP Pulse Width t

Set-up Time t

Hold Time t

MR to CP Removal Time t

ACT TYPES

Max. Clock Frequency f

MR Pulse Width t
CP Pulse Width t
Set-up Time t
Hold Time t
MR to CP Removal Time t

MAX

W

W

SU

H

REM

MAX

W
W

SU

H

REM

-40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX

1.5 7 - 6 - MHz

3.3

62 - 54 - MHz

(Note 9)

5

86 - 75 - MHz

(Note 10)

1.5 49 - 56 - ns

3.3 5.5 - 6.3 - ns
5 3.9 - 4.5 - ns

1.5 73 - 84 - ns

3.3 8.2 - 9.4 - ns
5 5.9 - 6.7 - ns

1.5 27 - 31 - ns

3.3 3.1 - 3.5 - ns
5 2.2 - 2.5 - ns

1.5 27 - 31 - ns

3.3 3.1 - 3.5 - ns
5 2.2 - 2.5 - ns

1.5 1 - 1 - ns

3.3 1 - 1 - ns
51-1-ns

5

80 - 70 - MHz

(Note 10)

5 3.9 - 4.5 - ns
5 6.2 - 7.1 - ns
5 2.2 - 2.5 - ns
5 2.6 - 3 - ns
50-0-ns

Switching Specifications Input t

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay,
CP to Qn

t

PLH

, tf = 3ns, CL= 50pF (Worst Case)

r

, t

PHL

1.5 - - 143 - - 157 ns

3.3

4.5 - 15.9 4.4 - 17.5 ns

(Note 9)

5

3.2 - 11.4 3.1 - 12.5 ns

(Note 10)

5

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

CD54/74AC164, CD54/74ACT164

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case) (Continued)

r

PARAMETER SYMBOL VCC (V)

Propagation Delay,
MR to Qn

t

PLH

, t

PHL

1.5 - - 158 - - 174 ns

3.3 5 - 17.7 4.9 - 19.5 ns
5 3.6 - 12.6 3.5 - 13.9 ns

Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 150 - - 150 - pF

(Note 11)

ACT TYPES

Propagation Delay, CP to Qn t

PLH

, t

PHL

5

3.8 - 13.5 3.7 - 14.9 ns

(Note 10)
Propagation Delay, MR to Qn t
Input Capacitance C
Power Dissipation Capacitance C

PLH

, t

PD

I

PHL

5 4.1 - 14.4 4 - 15.8 ns

- - -10- -10pF

- - 150 - - 150 - pF

(Note 11)

NOTES:

8. Limits tested at 100%.

9. 3.3V Min at 3.6V, Max at 3V.

10. 5V Min at 5.5V, Max at 4.5V.

11. CPD is used to determine the dynamic power consumption per device.
PD=CPDV

CC

2

fiΣ (CLV

2

fo)+VCC∆ICC, where fi= input frequency, fo= output frequency, CL= output load capacitance, VCC=

CC

supply voltage.

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

DS2 (1)

DS1 (2)

CP

CP

ANY

OUTPUT

90%

10%

90%

10%

t

r

t

w

1/f

t

PLHtPHL

t

TLHtTHL

MAX

t

f

INPUT

V

S

GND

V

S

MR

ANY

INPUT

CP

t

PHL

V

S

FIGURE 1. FIGURE 2.

V

S

t

SU

t

SU

VALID

V

S

t

H

V

S

t

H

t

REC

INPUT
LEVEL

GND

INPUT
LEVEL

GND

INPUT
LEVEL

GND

DS2 (1)

CP

V

S

t

SU

V

S

t

REC

t

w

V

S

t

H

V

S

INPUT LEVEL

GND

INPUT LEVEL

GND

INPUT LEVEL

GND

INPUT LEVEL

GND

FIGURE 3. FIGURE 4.

6

DUT

OUTPUT

R

L

CD54/74AC164, CD54/74ACT164

(NOTE)
500Ω

OUTPUT

LOAD

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

AC ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 5. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

CC

7

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pertaining to warranty, patent infringement, and limitation of liability.

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
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Copyright  2000, Texas Instruments Incorporated