Texas Instruments BQ4017YMC-70, BQ4017MC-70 Datasheet

bq4017/bq4017Y

2048Kx8 Nonvolatile SRAM

Features

Data retention in the absence of

➤

power

Automatic write-protection dur

➤

ing power-up/power-down cycles

Conventional SRAM operation;

➤

unlimited write cycles

5-year minimum data retention

➤

in absence of power

Battery internally isolated until

➤

power is applied

Pin Connections

36

V

CC

A

35

19

NC

34

A

33

15

A

32

17

31

WE
A

30

13

A

29

8

A

28

9

A

27

11

26

OE
A

25

10

24

CE
DQ

23
22

DQ
DQ

21
20

DQ

19

DQ

DQ
DQ
DQ
V

NC

1

A

2

20

A

3

18

A

4

16

A

5

14

A

6

12

A

7

7

A

8

6

9

A

5

A

10

4

11

A

3

A

12

2

A

13

1

A

14

0

15

0

16

1

17

2

18

SS

General Description

The CMOS bq4017 is a nonvolatile
16,777,216-bit static RAM organized
as 2,097,152 words by 8 bits. The

­integral control circuitry and lith

ium energy source provide reliable
nonvolatility coupled with the un
limited write cycles of standard
SRAM.

The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When V
falls out of tolerance, the SRAM is

At this time the integral energy
source is switched on to sustain the
memory until after V

returns valid.

CC

The bq4017 uses extremely low
standby current CMOS SRAMs, cou

­pled with small lithium coin cells to

provide nonvolatility without long

­write-cycle times and the write-cycle

limitations associated with EE
PROM.

The bq4017 has the same interface
as industry-standard SRAMs and

CC

requires no external circuitry.

-

-

unconditionally write-protected to
prevent an inadvertent write opera

-

tion.

Pin Names

A0–A

DQ

0

CE

OE

WE

V

CC

7
6
5
4
3

V

SS

NC No connect

Address inputs

20

–DQ7Data input/output

Chip enable input

Output enable input

Write enable input

Supply voltage input

Ground

Block Diagram

36-Pin DIP Module

PN401701.eps

Selection Guide

Part

Number

Maximum

Access

Time (ns)

Negative

Supply

Tolerance

Part

Number

Maximum

Access

Time (ns)

bq4017MC -70 70 -5% bq4017YMC -70 70 -10%

5/95

1

Negative

Supply

Tolerance

bq4017/bq4017Y

Functional Description

When power is valid, the bq4017 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4017 acts as a nonvolatile memory, automatically
protecting and preserving the memory contents.

Power-down/power-up control circuitry constantly moni
tors the V
V

. The bq4017 monitors for V

PFD

use in systems with 5% supply tolerance. The bq4017Y
monitors for V
with 10% supply tolerance.

When V
automatically write-protects the data. All outputs be
come high impedance, and all inputs are treated as
“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com
pletion. If the memory cycle fails to terminate within
time t

WPT

supply for a power-fail-detect threshold

CC

= 4.37V typical for use in systems

PFD

falls below the V

CC

= 4.62V typical for

PFD

threshold, the SRAM

PFD

, write-protection takes place.

As V

falls past V

CC

circuitry switches to the internal lithium backup supply,
which provides data retention until valid V

When V

returns to a level above the internal backup

CC

cell voltage, the supply is switched back to V
V

ramps above the V

CC

continues for a time t

­processor stabilization. Normal memory operation may
resume after this time.

The internal coin cells used by the bq4017 have an ex
tremely long shelf life. The bq4017 provides data reten
tion for more than 5 years in the absence of system
power.

­As shipped from Unitrode, the integral lithium cells are

electrically isolated from the memory. (Self-discharge in
this condition is approximately 0.5% per year.) Follow

­ing the first application of V

and the lithium backup provides data retention on sub
sequent power-downs.

and approaches 3V, the control

PFD

is applied.

CC

threshold, write-protection

PFD

(120ms maximum) to allow for

CER

, this isolation is broken,

CC

CC

Truth Table

Mode CE WE OE I/O Operation Power

Not selected H X X High Z Standby

Output disable L H H High Z Active

Read L H L D

Write L L X D

OUT

IN

Active

Active

. After

-

-

-

-

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

V

CC

V

T

T

OPR

T

STG

T

BIAS

T

SOLDER

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation

DC voltage applied on VCCrelative to V

SS

DC voltage applied on any pin excluding V
relative to V

SS

CC

-0.3 to 7.0 V

-0.3 to 7.0 V

V

+ 0.3

V

≤

T

CC

Operating temperature 0 to +70 °C

Storage temperature -40 to +70 °C

Temperature under bias -10 to +70 °C

Soldering temperature +260 °C For 10 seconds

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con
ditions beyond the operational limits for extended periods of time may affect device reliability.

2

-

bq4017/bq4017Y

Recommended DC Operating Conditions (T

= 0 to 70°C)

A

Symbol Parameter Minimum Typical Maximum Unit Notes

V

CC

V

SS

V

IL

V

IH

Supply voltage

Supply voltage 0 0 0 V

Input low voltage -0.3 - 0.8 V

Input high voltage 2.2 - VCC+ 0.3 V

4.5 5.0 5.5 V bq4017Y

4.75 5.0 5.5 V bq4017

Note: Typical values indicate operation at TA= 25°C.

DC Electrical Characteristics (T

= 0 to 70°C, V

A

CCmin

V

CC

V

≤

≤

CCmax

)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

I

I

V

V

I

I

LI

LO

OH

OL

SB1

SB2

Input leakage current - -

Output leakage current - -

Output high voltage 2.4 - - V IOH= -1.0 mA

Output low voltage - - 0.4 V IOL= 2.1 mA

Standby supply current - 7 17 mA CE = V

Standby supply current - 2.5 5 mA

4

±

4

±

AVIN= VSSto V

µ

= VIHor OE = VIHor

CE

A

µ

WE

= V

IL

IH

0V≤V

IN

CE

V

≥

CC

or V

V

≥

IN

0.2V,

≤

- 0.2V,

CC

CC

- 0.2

Min. cycle, duty = 100%,

= VIL,I

I

CC

Operating supply current - 75 115 mA

CE
A19 < V
A20 < V

V

PFD

V

SO

Power-fail-detect voltage

Supply switch-over voltage - 3 - V

4.55 4.62 4.75 V bq4017

4.30 4.37 4.50 V bq4017Y

= 0mA,

I/O

or A19 > VIH,

IL

or A20 > V

IL

IH

Note: Typical values indicate operation at TA= 25°C, VCC= 5V.

3

bq4017/bq4017Y

Capacitance (T

= 25°C, F = 1MHz, VCC= 5.0V)

A

Symbol Parameter Minimum Typical Maximum Unit Conditions

C

I/O

C

IN

Input/output capacitance - - 40 pF Output voltage = 0V

Input capacitance - - 40 pF Input voltage = 0V

Note: These parameters are sampled and not 100% tested.

AC Test Conditions

Parameter Test Conditions

Input pulse levels 0V to 3.0V

Input rise and fall times 5 ns

Input and output timing reference levels 1.5 V (unless otherwise specified)

Output load (including scope and jig) See Figures 1 and 2

Figure 1. Output Load A

Read Cycle

Symbol Parameter

t

RC

t

AA

t

ACE

t

OE

t

CLZ

t

OLZ

t

CHZ

t

OHZ

t

OH

(TA= 0 to 70°C, V

CCmin

Read cycle time 70 - ns

Address access time - 70 ns Output load A

Chip enable access time - 70 ns Output load A

Output enable to output valid - 35 ns Output load A

Chip enable to output in low Z 5 - ns Output load B

Output enable to output in low Z 5 - ns Output load B

Chip disable to output in high Z 0 25 ns Output load B

Output disable to output in high Z 0 25 ns Output load B

Output hold from address change 10 - ns Output load A

Figure 2. Output Load B

V

CC

V

≤

≤

CCmax

)

-70

Min. Max.

4

Unit Conditions