Texas Instruments BQ4016YMC-70, BQ4016MC-70 Datasheet

bq4016/bq401 6Y

1024Kx8 Nonvolatile SRAM

Features

➤ Data retention in the absence of

power

➤ Automatic write-protection

during power-up/power-down
cycles

➤ Conventional SRAM operation;

unlimited write cycles

➤ 10-year minimum data retention

in absence of power

➤ Battery internally isolate d until

power is applied

Pin Connections

General Descrip ti on

The CMOS bq4016 is a nonvolatile
8,388,608-bit static RAM organized
as 1,048,576 words by 8 bits. The in­tegral control circuitry and lithium
energy source provide reliable non­volatility coupled with the unlimited
write cycles of standard SRAM.

The control circuitry constantly
monitors the single 5V supply for an
out-of-tolerance condition. When V
falls out of tolerance, the SRAM is
unconditionally write-protected to
prevent an inadvertent write
operation.

CC

Pin Names

A0–A

DQ

0

CE Chip enable input

OE Output enable input

WE Write enable input

Address inputs

19

–DQ7Data input/output

At this time the integral energy
source is swit ched on to sustain the
memory until after V
valid.

The bq4016 uses extremely low
standby current CMOS SRAMs,
coupled with a small lithium coin
cell to provide nonvolatility without
long w rit e-cy cl e tim es an d th e wri te­cycle limitations associated with
EEPROM.

The bq4016 has the same interface
as industry-standard SRAMs and re­quires no external circuitry.

returns

CC

Block Diagram

Selection Guide

Part

Number

bq4016MC -70

Sept. 1996 B

V

CC

V

SS

NC No connect

Maximum

Access

Time (ns)

70 -5%

+5 volt supply input

Ground

Negative

Supply

Tolerance

Part

Number

bq4016 Y MC -70

1

Maximum

Access

Time (ns)

70 -10%

Negative

Supply

Tolerance

bq4016/bq4016Y

Functional Description

When power is valid, the bq4016 operates as a standard
CMOS SRAM. During power-down and power-up cycles,
the bq4 016 ac ts as a no nvolati le memo ry, automa tically
protecting and preserving the memory contents.

Power-down/power-up control circuitry constantly
monit ors t he V

. The bq4016 monitors for V

V

PFD

use in sy stems wi th 5% sup ply tolera nce. The bq4016 Y
monitors f or V
10% supply tolerance.

When V

CC

automatically write-protects the data. All outputs
become high impedance, and all inputs are treated as

“don’t care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com­pletion. If the memory cycle fails to terminate within
time t

WPT

supply for a power-fail-detect threshold

CC

= 4.37V typical for use in systems with

PFD

falls below the V

= 4.62V typical for

PFD

threshold, the SRAM

PFD

, write-protection takes place.

falls past V

As V

CC

circuitry switches to the internal lithium backup supply,
which provides data retention until valid V

When V

retur ns to a level abov e the interna l backup

CC

cell voltage, the supply is switched back to V

ramps above the V

V

CC

continues for a time t
processo r stabil ization. Normal m emory ope ration may
resume aft er this time.

The internal coin cells used by the bq4016 have an
extremely long shelf life. The bq4016 provides data
retention for more than 10 years in the absence of sys­tem power.

As shipped from Benchmarq, the integral lithium cells
are electrically isolated from the memory. (Self-discharge
in this condition is approximately 0.5% per year.)
Following the first application of V
broken, and the li thium back up provide s data rete ntion
on subseq uent power-downs.

and approaches 3V, the control

PFD

is applied.

CC

threshold, write-protection

PFD

(120ms maxi mum) t o al low for

CER

CC

CC

, this isolation is

Truth Table

Mode CE WE OE I/O Op e r at ion Powe r

Not selected H X X High Z Standby
Output disable L H H High Z Active
Read L H L D
Write L L X D

OUT

IN

Active
Active

. After

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

V

CC

V

T

T

OPR

T

STG

T

BIAS

T

SOLDER

DC voltage applied on VCC relative to V

SS

DC voltage applied on any pin excluding V
relative to V

SS

CC

-0.3 to 7.0 V

-0.3 to 7.0 V

V

≤ VCC + 0.3

T

Operati ng temperature 0 to +70 °C
Storage temperature -40 to +70 °C
Temperature under bias -10 to +70 °C
Soldering temperature +260 °C For 10 se c onds

Note: Permanent device damage may occ ur if Absolute Maximum Ratings are exceeded. Functional operation

should be limited to the Recommended DC Operating Conditions detailed in t his data sheet. Exposure to
conditions beyond the operational limits for extended periods of time may affect device reliability.

Sept. 1996 B

2

bq4016/bq4016Y

Recommended DC Operating Conditions (T

= 0 to 70°C)

A

Symbol Parameter Minimum Typical Maximum Unit Notes

4.5 5.0 5.5 V bq4016Y

V

CC

V

SS

V

IL

V

IH

Note: Typical va lues indic ate op e ra t io n at T

DC Electrical Characteristics (T

Supp l y volta ge

4.75 5. 0 5.5 V bq4 01 6
Supp l y volta ge 0 0 0 V
Input low voltage -0.3 - 0.8 V
Input high voltage 2.2 - VCC + 0.3 V

= 25°C.

A

= 0 to 70°C, V

A

CCmin

≤ VCC ≤ V

CCmax

)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

I

I
V

V
I

I

LI

LO

OH
OL

SB1

SB2

Input leakage current

--

Output leakage current - -

± 2 µA

± 2 µA

= VSS to V

V

IN

CE = VIH or OE = V
WE = V

IL

Output high voltage 2.4 - - V IOH = -1.0 mA
Output low voltage - - 0.4 V IOL = 2.1 mA
Standby supply current - 5 12 mA CE = V

Standby supply current - 2.5 5 mA

IH

0V ≤ V

≤ 0.2V,

IN

CE ≥ VCC - 0.2V,

≥ VCC - 0.2

or V

IN

CC

Min. cycle, duty = 100%,

I

CC

V

PFD

Operating supply c urrent - 75 115 mA

Power-fail-detect voltage

4.55 4.62 4.75 V bq4016

CE = VIL ,I
A19 < V

IL

= 0mA,

I/O

or A19 > VIH,

4.30 4.37 4.50 V bq4016Y

V

SO

Note: Typical va lues indic ate op e ra t io n at T

Supply switch-over voltage - 3 - V

= 25°C, VCC = 5V.

A

IH

or

Sept. 1996 B

3

bq4016/bq4016Y

Capacitance (T

= 25°C, F = 1MHz, VCC = 5.0V)

A

Symbol Parameter Minimum Typical Maximum Unit Conditions

C

I/O

C

IN

Input/output capacitance - - 20 pF Output voltage = 0V
Input capacitance - - 20 pF Input voltage = 0V

Note: These parameters are sampled and not 100% tested.

AC Test Conditions

Parameter Test Conditions

Input pulse levels 0V to 3.0V
Input rise and fall ti mes 5 ns
Input and output timing reference levels 1.5 V (unless otherwise specified)

Figure 1. Output Load A

Read Cycle (T

Symbol Parameter

t
t
t
t
t
t
t
t
t

RC
AA
ACE
OE
CLZ
OLZ
CHZ
OHZ
OH

Read cycle time 70 - ns
Address access time - 70 ns Output load A
Chip enable access time - 70 ns Output load A
Output enable to output valid - 35 ns Output load A
Chip enable to output in low Z 5 - ns Output load B
Output enable to output in low Z 5 - ns Output load B
Chip disable to output in high Z 0 25 ns Output load B
Output disable to output in high Z 0 25 ns Output load B
Output hold from address change 10 - ns Output load A

= 0 to 70°C, V

A

CCmin

≤ VCC ≤ V

CCmax

)

-70

Min. Max.

4

Figure 2. Output Load B

Unit Conditions

Sept. 1996 B