Texas Instruments BQ4013YMA-85, BQ4013YMA-70N, BQ4013YMA-70, BQ4013YMA-120, BQ4013MA-85 Datasheet

bq4013/Y

128Kx8 Nonvolatile SRAM

Features

Data retention for at least 10

➤

years without power

Automatic write-protection during

➤

power-up/power-down cycles

Conventional SRAM operation,

➤

including unlimited write cycles

Internal isolation of battery be

➤

fore power application

Industry standard 32-pin DIP

➤

pinout

Pin Connections

General Description

The CMOS bq4013/Y is a nonvolatile
1,048,576-bit static RAM organized as
131,072 words by 8 bits. The integral
control circuitry and lithium energy
source provide reliable nonvolatility
coupled with the unlimited write cy
cles of standard SRAM.

The control circuitry constantly

­monitors the single 5V supply for an

out-of-tolerance condition. When
V

falls out of tolerance, the SRAM

CC

is unconditionally write-protected to
prevent inadvertent write operation.

At this time the integral energy
source is switched on to sustain the
memory until after V

returns valid.

CC

Pin Names

A0–A

DQ

CE

0

Address inputs

16

–DQ7Data input/output

Chip enable input

The bq4013/Y uses an extremely
low standby current CMOS SRAM,
coupled with a small lithium coin
cell to provide nonvolatility without
long write-cycle times and the
write-cycle limitations associated
with EEPROM.

­The bq4013/Y requires no external

circuitry and is socket-compatible
with industry-standard SRAMs and
most EPROMs and EEPROMs.

WE

NC No connect

V

CC

Write enable input

Supply voltage input

OE

Output enable input

V

SS

Ground

Selection Guide

Maximum

Part

Number

bq4013MA -85 85 -5% bq4013YMA -85 85 -10%

bq4013MA-120 120 -5% bq4013YMA-120 120 -10%

9/96 D

Access

Time (ns)

Negative

Supply

Tolerance

Part

Number

bq4013YMA -70 70 -10%

Maximum

Access

Time (ns)

1

Negative

Supply

Tolerance

bq4013/Y

Functional Description

When power is valid, the bq4013/Y operates as a stan
dard CMOS SRAM. During power-down and power-up
cycles, the bq4013/Y acts as a nonvolatile memory, auto
matically protecting and preserving the memory con
tents.

Power-down/power-up control circuitry constantly moni
tors the V
V

. The bq4013 monitors for V

PFD

use in systems with 5% supply tolerance. The bq4013Y
monitors for V
with 10% supply tolerance.

When V
tomatically write-protects the data. All outputs become
high impedance, and all inputs are treated as “don’t
care.” If a valid access is in process at the time of
power-fail detection, the memory cycle continues to com
pletion. If the memory cycle fails to terminate within
time t

WPT

supply for a power-fail-detect threshold

CC

= 4.37V typical for use in systems

PFD

falls below the V

CC

, write-protection takes place.

PFD

= 4.62V typical for

PFD

threshold, the SRAM au

Block Diagram

As V
circuitry switches to the internal lithium backup supply,
which provides data retention until valid V

-

When V

­cell voltage, the supply is switched back to V

­V

continues for a time t
processor stabilization. Normal memory operation may

­resume after this time.

The internal coin cell used by the bq4013/Y has an ex
tremely long shelf life and provides data retention for
more than 10 years in the absence of system power.

As shipped from Unitrode, the integral lithium cell of

­the MA-type module is electrically isolated from the

memory. (Self-discharge in this condition is approxi
mately 0.5% per year.) Following the first application of
V

­provides data retention on subsequent power-downs.

falls past V

CC

returns to a level above the internal backup

CC

ramps above the V

CC

, this isolation is broken, and the lithium backup cell

CC

and approaches 3V, the control

PFD

is applied.

CC

threshold, write-protection

PFD

(120ms maximum) to allow for

CER

. After

CC

-

-

OE

WE

Power

CE

128K x 8

SRAM

Block

Power-Fail

Control

A0–A

DQ0–DQ

CE

CON

V

Lithium
Cell

2

16

7

CC

BD-42

bq4013/Y

Truth Table

Mode CE WE OE I/O Operation Power

Not selected H X X High Z Standby

Output disable L H H High Z Active

Read L H L D

Write L L X D

OUT

IN

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

V

CC

V

T

T

OPR

T

STG

T

BIAS

T

SOLDER

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation

DC voltage applied on VCCrelative to V

SS

DC voltage applied on any pin excluding V
relative to V

SS

Operating temperature

Storage temperature

Temperature under bias

CC

-0.3 to 7.0 V

-0.3 to 7.0 V

V

T

0 to +70 °C Commercial

-40 to +85 °C Industrial “N”

-40 to +70 °C Commercial

-40 to +85 °C Industrial “N”

-10 to +70 °C Commercial

-40 to +85 °C Industrial “N”

Soldering temperature +260 °C For 10 seconds

should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to con
ditions beyond the operational limits for extended periods of time may affect device reliability.

Active

Active

+ 0.3

V

≤

CC

-

3

bq4013/Y

Recommended DC Operating Conditions (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

V

V

V

Supply voltage

CC

Supply voltage 0 0 0 V

SS

Input low voltage -0.3 - 0.8 V

IL

Input high voltage 2.2 - VCC+ 0.3 V

IH

4.5 5.0 5.5 V bq4013Y

4.75 5.0 5.5 V bq4013

Note: Typical values indicate operation at TA= 25°C.

DC Electrical Characteristics (T

A=TOPR, VCCmin

V

CC

V

≤

CCmax)

≤

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

I

I

V

V

I

I

I

V

V

LI

LO

OH

OL

SB1

SB2

CC

PFD

SO

Input leakage current - -

Output leakage current - -

1

±

1

±

AVIN=VSSto V

µ

=VIHor OE =VIHor

CE

A

µ

WE

=V

IL

Output high voltage 2.4 - - V IOH= -1.0 mA

Output low voltage - - 0.4 V IOL= 2.1 mA

Standby supply current - 4 7 mA CE =V

Standby supply current - 2.5 4 mA

Operating supply current - 75 105 mA

Power-fail-detect voltage

4.55 4.62 4.75 V bq4013

4.30 4.37 4.50 V bq4013Y

IH

V

CE
0V≤V
or V

- 0.2V,

≥

CC

0.2V,

≤

IN

V

≥

IN

CC

Min. cycle, duty = 100%,
CE

=VIL,I

I/O

Supply switch-over voltage - 3 - V

CC

- 0.2V

= 0mA

Note: Typical values indicate operation at TA= 25°C, VCC= 5V.

Capacitance (T

= 25°C, F = 1MHz, VCC= 5.0V)

A

Symbol Parameter Minimum Typical Maximum Unit Conditions

C

I/O

C

IN

Input/output capacitance - - 10 pF Output voltage = 0V

Input capacitance - - 10 pF Input voltage = 0V

Note: These parameters are sampled and not 100% tested.

4

AC Test Conditions

Parameter Test Conditions

Input pulse levels 0V to 3.0V

Input rise and fall times 5 ns

Input and output timing reference levels 1.5 V (unless otherwise specified)

Output load (including scope and jig) See Figures 1 and 2

bq4013/Y

Read Cycle (T

A=TOPR, VCCmin

Symbol Parameter

t

RC

t

AA

t

ACE

t

OE

t

CLZ

t

OLZ

t

CHZ

t

OHZ

t

OH

Read cycle time 70 - 85 - 120 - ns

Address access time - 70 - 85 - 120 ns Output load A

Chip enable access time - 70 - 85 - 120 ns Output load A

Output enable to output valid - 35 - 45 - 60 ns Output load A

Chip enable to output in low Z 5 - 5 - 5 - ns Output load B

Output enable to output in low Z 0 - 0 - 0 - ns Output load B

Chip disable to output in high Z 0 25 0 35 0 45 ns Output load B

Output disable to output in high Z 0 25 0 25 0 35 ns Output load B

Output hold from address change 10 - 10 - 10 - ns Output load A

Figure 2. Output Load BFigure 1. Output Load A

V

≤

V

≤

CC

CCmax)

-70/-70N -85/-85N -120

Min. Min. Min. Max. Min. Max.

5

Unit Conditions

bq4013/Y

Read Cycle No. 1 (Address Access)

Read Cycle No. 2 (CE Access)

Read Cycle No. 3 (OE Access)

1,3,4

1,5

1,2

Notes: 1. WE is held high for a read cycle.

2. Device is continuously selected: CE

3. Address is valid prior to or coincident with CE

4. OE

=VIL.

5. Device is continuously selected: CE

=OE=VIL.

transition low.

=VIL.

6

bq4013/Y

Write Cycle (T

A=TOPR , VCCmin

Symbol Parameter

t

WC

t

CW

t

AW

t

AS

t

WP

t

WR1

t

WR2

t

DW

t

DH1

t

DH2

t

WZ

t

OW

Write cycle time 70 - 85 - 120 - ns

Chip enable to end of
write

Address valid to end of
write

Address setup time 0 - 0 - 0 - ns

Write pulse width 55 - 65 - 85 - ns

Write recovery time
(write cycle 1)

Write recovery time
(write cycle 2)

Data valid to end of
write

Data hold time
(write cycle 1)

Data hold time
(write cycle 2)

Write enabled to output
in high Z

Output active from end
of write

V

CC

V

≤

≤

CCmax

)

-70/-70N -85/-85N -120

Min. Max. Min. Max. Min. Max.

Units

Conditions/Notes

65 - 75 - 100 - ns (1)

65 - 75 - 100 - ns (1)

Measured from address valid
to beginning of write. (2)

Measured from beginning of
write to end of write. (1)

5-5-5-ns

15 - 15 - 15 - ns

30 - 35 - 45 - ns

0-0-0-ns

10 - 10 - 10 - ns

Measured from WE going high
to end of write cycle. (3)

Measured from CE going high
to end of write cycle. (3)

Measured to first low-to-high
transition of either CE

or WE.

Measured from WE going high
to end of write cycle. (4)

Measured from CE going high
to end of write cycle. (4)

0 25 0 30 0 40 ns I/O pins are in output state. (5)

0 - 0 - 0 - ns I/O pins are in output state. (5)

Notes: 1. A write ends at the earlier transition of CE going high and WE going high.

2. A write occurs during the overlap of a low CE
of CE

going low and WE going low.

3. Either t

4. Either t

5. If CE

or t

or t

must be met.

WR2

must be met.

DH2

WR1

DH1

goes low simultaneously with WE going low or after WE going low, the outputs remain in

and a low WE. A write begins at the later transition

high-impedance state.

7

bq4013/Y

Write Cycle No. 1 (WE-Controlled)

Write Cycle No. 2 (CE-Controlled)

1,2,3

1,2,3,4,5

Notes: 1. CE or WE must be high during address transition.

2. Because I/O may be active (OE
outputs must not be applied.

3. If OE

4. Either t

5. Either t

is high, the I/O pins remain in a state of high impedance.

or t

or t

must be met.

WR2

must be met.

DH2

WR1

DH1

low) during this period, data input signals of opposite polarity to the

8

bq4013/Y

Power-Down/Power-Up Cycle (T

A=TOPR)

Symbol Parameter Minimum Typical Maximum Unit Conditions

t

PF

t

FS

t

PU

VCCslew, 4.75 to 4.25 V 300 - -

VCCslew, 4.25 to V

VCCslew, VSOto V

SO

(max.) 0 - -

PFD

10 - -

s

µ

s

µ

s

µ

Time during which
SRAM is

t

CER

Chip enable recovery time 40 80 120 ms

write-protected after
V

passes V

CC

PFD

on

power-up.

t

DR

t

DR-N

t

WPT

Data-retention time in
absence of V

CC

Data-retention time in
absence of V

CC

10 - - years

6 - - years

Write-protect time 40 100 150

T

= 25°C. (2)

A

= 25°C (2); industrial

T

A

temperature range only

Delay after V
down past V

s

µ

SRAM is

CC

PFD

slews
before

write-protected.

Notes: 1. Typical values indicate operation at TA= 25°C, VCC= 5V.

2. Battery is disconnected from circuit until after V

is applied for the first time. tDRis the

CC

accumulated time in absence of power beginning when power is first applied to the device.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Power-Down/Power-Up Timing

9

bq4013/Y

MA: 32-Pin A-Type Module

Dimension Minimum Maximum

A 0.365 0.375

A1 0.015 -

B 0.017 0.023
C 0.008 0.013
D 1.670 1.700
E 0.710 0.740

e 0.590 0.630
G 0.090 0.110
L 0.120 0.150
S 0.075 0.110

All dimensions are in inches.

MS: 34-Pin Leaded Chip carrier for LIFETIME LITHIUM Module

34-Pin LCR LIFETIME LITHIUM Module

Dimension Minimum Maximum

A 0.920 0.930
B 0.980 0.995

C - 0.080
D 0.052 0.060
E 0.045 0.055
F 0.015 0.025
G 0.020 0.030
H - 0.090

J 0.053 0.073

All dimensions are in inches.

1

Centerline of lead within ±0.005 of true position.

2

Leads coplanar within ±0.004 at seating plane.

3

Components and location may vary.

10

MS: LIFETIME LITHIUM Module Housing

LIFETIME LITHIUM Module Housing

Dimension Minimum Maximum

All dimensions are in inches.

1

Edges coplanar within ±0.025.

MS: LIFETIME LITHIUM Module with LCR attached

bq4013/Y

A 0.845 0.855
B 0.955 0.965
C 0.210 0.220
D 0.065 0.075
E 0.065 0.075

11

LIFETIME LITHIUM Module

Dimension Minimum Maximum

A 0.955 0.965
B 0.980 0.995
C 0.240 0.250

D 0.052 0.060

E 0.045 0.055
F 0.015 0.025

All dimensions are in inches.

1

Leads coplanar within ±0.004 at seating plane.

2

Components and location may vary.

bq4013/Y

Data Sheet Revision History

Change No. Page No. Description

1 2, 3, 4, 6, 8, 9 Added industrial temperature range.

2 1, 4, 6, 9 Added 70ns speed grade for bq4013Y-70.

3 Removed industrial temperature range for bq4013YMA-120N

Notes: Change 1 = Sept. 1992 B changes from Sept. 1990 A.

Change 2 = Aug. 1993 C changes from Sept. 1991 B.
Change 3 = Sept. 1996 D changes from Aug. 1993 C.

Ordering Information

bq4013 xx -

Temperature:

blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)

Speed Options:

70 = 70 ns
85 = 85 ns

120 = 120 ns

Package Option:

MA = A-type Module

1

Supply Tolerance:

no mark = 5% negative supply tolerance
Y = 10% negative supply tolerance

Device:

bq4013 128K x 8 NVSRAM

Notes: 1. Only 10% supply MA module (“Y-MA”) version is available in industrial

temperature range; contact factory for speed grade availability.

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