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DUAL J-K
54ACT11109, 74ACT11109
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993
• Inputs Are TTL-Voltage Compatible
• Flow-Through Architecture Optimizes
PCB Layout
• Center-Pin V
and GND Configurations
CC
Minimize High-Speed Switching Noise
•
EPIC
(Enhanced-Performance Implanted
CMOS) 1-µm Process
• 500-mA Typical Latch-Up Immunity
at 125°C
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and
Ceramic 300-mil DIPs
description
These devices contain two independent J-K
positive-edge-triggered flip-flops. A low level at
the preset (1PRE or 2PRE) or clear (1CLR or
2CLR) input sets or resets the outputs regardless
of the levels of the other inputs. When PRE
CLR are inactive (high), data at the J and K inputs
meeting the setup time requirements are
transferred to the outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at
a voltage level and is not directly related to the rise
time of the clock pulse. Following the hold-time
interval, data at the J and K
changed without affecting the levels at the
outputs. These versatile flip-flops can perform as
toggle flip-flops by grounding K
They also can perform as D-type flip-flops if J and
K are tied together.
inputs may be
and tying J high.
and
54ACT11109 ...J PACKAGE
74ACT11109 ...D OR N PACKAGE
1PRE
2PRE
54ACT11109 . . . FK PACKAGE
1K
1CLK
NC
1PRE
1Q
NC – No internal connection
1Q
1Q
GND
2Q
2Q
2CLK
3 2 1 20 19
4
5
6
7
8
910111213
(TOP VIEW)
16
1
15
2
14
3
13
4
12
5
11
6
10
7
8
(TOP VIEW)
1J
NC
1CLR
1Q
NC
GND
9
V
CC
2Q
1CLK
1K
1J
1CLR
V
CC
2CLR
2J
2K
2CLR
18
17
16
15
14
2Q
2J
2K
NC
2CLK
2PRE
The 54ACT1 1 109 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT11109 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
PRE CLR CLK J K Q Q
L H X X X H L
H LXXXLH
L LXXXH†H
H H ↑ LLL
H H ↑ H L Toggle
H H ↑ LHQ0Q
H H ↑ HHHL
H H L X X Q
†
This configuration is nonstable; that is, it will not persist when
either PRE
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
INPUTS
or CLR returns to the inactive (high) level.
OUTPUTS
Q
0
†
H
0
0
Copyright 1993, Texas Instruments Incorporated
2–1
54ACT11109, 74ACT11109
UNIT
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
†
1PRE
1J
1CLK
1K
1CLR
2PRE
2J
2CLK
2K
2CLR
1
14
16
15
13
7
10
8
9
11
S
1J
1K
R
C1
2
1Q
3
1Q
6
2Q
5
2Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
Output clamp current, IOK (VO < 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(VI < 0 or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
‡
recommended operating conditions
54ACT11109 74ACT11109
MIN MAX MIN MAX
V
CC
V
IH
V
IL
V
I
V
O
I
OH
I
OL
∆t/∆v Input transition rise or fall rate 0 10 0 10 ns/V
T
A
2–2
Supply voltage 4.5 5.5 4.5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
Output voltage 0 V
High-level output current –24 –24 mA
Low-level output current 24 24 mA
Operating free-air temperature –55 125 –40 85 °C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
CC
0 V
0 V
CC
CC
V
V
54ACT11109, 74ACT11109
PARAMETER
TEST CONDITIONS
V
UNIT
I
A
VOHI
mA
V
I
A
VOLI
mA
V
UNIT
twPulse duration
ns
tsuSetup time before CLK↑
ns
PARAMETER
UNIT
PRE or CLR
Q
Q
ns
CLK
Q
Q
ns
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
CC
= –50 µ
OH
= –24
OH
IOH = – 50 mA
IOH = –75 mA
= 50 µ
OL
= 24
OL
IOL = 50 mA
IOL = 75 mA
I
I
I
CC
∆I
CC
C
i
†
Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA
VI = VCC or GND, IO = 0 5.5 V 4 80 40 µA
One input at 3.4 V ,
‡
Other inputs at VCC or GND
VI = VCC or GND 5 V 3.5 pF
†
†
†
†
4.5 V 4.4 4.4 4.4
5.5 V 5.4 5.4 5.4
4.5 V 3.94 3.7 3.8
5.5 V 4.94 4.7 4.8
5.5 V 3.85
5.5 V 3.85
4.5 V 0.1 0.1 0.1
5.5 V 0.1 0.1 0.1
4.5 V 0.36 0.5 0.44
5.5 V 0.36 0.5 0.44
5.5 V 1.65
5.5 V 1.65
5.5 V 0.9 1 1 mA
TA = 25°C 54ACT11109 74ACT11109
MIN TYP MAX MIN MAX MIN MAX
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C 54ACT11109 74ACT11109
MIN MAX MIN MAX MIN MAX
f
clock
t
h
Clock frequency 0 100 0 100 0 100 MHz
PRE or CLR low 5.5 5.5 5.5
CLK high or low 5 5 5
p
Hold time, data after CLK↑ 0 0 0 ns
Data high or low 5.5 5.5 5.5
PRE or CLR inactive 2 2 2
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
TA = 25°C 54ACT11109 74ACT11109
MIN TYP MAX MIN MAX MIN MAX
100 125 100 100 MHz
1.5 5.5 8.6 1.5 9.8 1.5 9.2
1.5 6 10.8 1.5 12.6 1.5 11.8
1.5 6 8.3 1.5 9.7 1.5 9.1
1.5 5.5 7.6 1.5 9 1.5 8.3
f
max
t
PLH
t
PHL
t
PLH
t
PHL
FROM TO
(INPUT) (OUTPUT)
or
or
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–3
54ACT11109, 74ACT11109
DUAL J-K
POSITIVE-EDGE-TRIGGERED FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS451 – FEBRUARY 1987 – REVISED APRIL 1993
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
pd
Power dissipation capacitance per flip-flop CL = 50 pF, f = 1 MHz 31 pF
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
Input
t
w
1.5 V 1.5 V
3 V
0 V
LOAD CIRCUIT
Timing Input
(see Note B)
t
su
Data Input
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
1.5 V
VOLTAGE WAVEFORMS
1.5 V
t
h
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
3 V
0 V
3 V
0 V
Input
(see Note B)
In-Phase
Output
Out-of-Phase
Output
VOLTAGE WAVEFORMS
1.5 V 1.5 V
t
PLH
50% V
t
PHL
50% V
VOLTAGE WAVEFORMS
CC
CC
t
PHL
50% V
t
PLH
50% V
CC
CC
3 V
0 V
V
V
V
V
OH
OL
OH
OL
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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